CN108831861A - Stacked chip packages method and encapsulating structure - Google Patents
Stacked chip packages method and encapsulating structure Download PDFInfo
- Publication number
- CN108831861A CN108831861A CN201810904094.3A CN201810904094A CN108831861A CN 108831861 A CN108831861 A CN 108831861A CN 201810904094 A CN201810904094 A CN 201810904094A CN 108831861 A CN108831861 A CN 108831861A
- Authority
- CN
- China
- Prior art keywords
- chip
- wiring layer
- electric connection
- connection terminal
- electrical connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004806 packaging method and process Methods 0.000 claims abstract description 29
- 229910000679 solder Inorganic materials 0.000 claims description 37
- 230000006698 induction Effects 0.000 claims description 16
- 239000011159 matrix material Substances 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 5
- 238000011900 installation process Methods 0.000 claims description 5
- 239000004744 fabric Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 12
- 230000008901 benefit Effects 0.000 abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 18
- 239000010949 copper Substances 0.000 description 18
- 230000006872 improvement Effects 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000001259 photo etching Methods 0.000 description 10
- 238000005520 cutting process Methods 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 229910018487 Ni—Cr Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical compound [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
Abstract
Present invention discloses a kind of stacked chip packages method and encapsulating structure, the packaging method includes：First chip is provided, there is white space on first chip surface；The second chip is provided, second chip is flip-chip；Second flip-chip is packaged on the white space of first chip.Stacked chip packages method and encapsulating structure of the invention by by the second chip package in the white space of the first chip, stacked package takes full advantage of the white space of the first chip back, the area of plane for reducing encapsulating structure realizes the area of plane miniaturization of encapsulation.
Description
Technical field
The invention belongs to field of semiconductor manufacture technology more particularly to a kind of stacked chip packages method and encapsulation knots
Structure.
Background technique
With the trend of electronic product multifunction and miniaturization, high density microelectronic mounting technology is produced in electronics of new generation
Mainstream is increasingly becoming on product.In order to cooperate the development of electronic product of new generation, the size of chip is higher to density, speed faster,
Smaller, the more low direction of cost is developed.
Currently, crystal wafer chip dimension encapsulation (Wafer Level Chip Size Packaging, WLCSP) is usually
The weld pad of semiconductor core on piece periphery arrangement is scattered in a large amount of metal soldered balls that face battle array arranges, metal welding by redistribution process
Ball is also referred to as pedestal.Since crystal wafer chip dimension encapsulation first carries out packaging and testing on full wafer wafer, then again
Cutting, thus have more obvious advantage：It is that technique process optimizes significantly first, wafer is directly entered packaging process, and traditional
Technique before encapsulation will cut wafer, be classified；Also, the crystal wafer chip dimension encapsulation is all integrated circuits
Primary encapsulation, marking work carry out directly on wafer, and packaging and testing are once completed, and are different from traditional packaging technology, so that raw
It produces the period and production cost declines to a great extent.
In existing crystal wafer chip dimension encapsulation when needing integrated multiple chips, more cores need to be formed in wafer plane
Piece, and by the interconnection of the realization chip chamber of wiring layer again, the terminal finally by pedestal as multiple chips.Using above-mentioned
Although scheme can carry out the integrated of multi-chip, the chip in same plane considerably increases the plane face of entire encapsulating structure
Product, is unfavorable for the miniaturization of chip package.
Therefore, it is necessary to provide a kind of stacked chip packages method and encapsulating structures in view of the above technical problems.
Summary of the invention
The purpose of the present invention is to provide a kind of stacked chip packages method, this method is sealed by stacking the second chip
In white space loaded on the first chip surface, the area of plane of encapsulation can be reduced, realize the miniaturization of chip package.
Another object of the present invention is to provide a kind of encapsulating structures of semiconductor chip.
For achieving the above object, the present invention adopts the following technical scheme that,
A kind of stacked chip packages method, the packaging method include：
First chip is provided, there is white space on first chip surface；
The second chip is provided, second chip is flip-chip；
Second flip-chip is packaged on the white space of first chip.
As a further improvement of the present invention, the packaging method includes：
Wafer is provided, the wafer has the first chip of more grids arrangement, and first chip has relative to each other
First surface and second surface, first chip have positioned at the first surface induction zone and with induction zone electricity
The weld pad of coupling；
The through-hole extended towards first surface is formed in the second surface of first chip, the via bottoms expose
The weld pad；
Remove the part of matrix of the first chip edge；
Form the first wiring layer again on first chip, described first again wiring layer prolong from the bottom and side wall of through-hole
Extend to the second surface of first chip, described first again wiring layer be electrically connected with the weld pad；
Electrical connection section is not formed in the first white space that wiring layer covers again on first chip；
Form the second wiring layer again in the white space, described second again wiring layer be electrically connected with the electrical connection section
Connect, and second again wiring layer enclose the region for setting and being formed from electrical connection section and extend outwardly；
Second chip is packaged on the white space of the first chip by reverse installation process, second chip is upside-down mounting core
Piece, and the second chip and electrical connection section contraposition encapsulate；
Solder mask is formed in the second surface top of first chip and the through-hole, the solder mask covers institute
State the first wiring layer and the second wiring layer again again；
Electrical connection described first first electric connection terminal of wiring layer and electrical connection described second again are formed on solder mask
Second electric connection terminal of wiring layer again；
Wafer is cut, multiple independent stack type chip packaging structures are obtained.
As a further improvement of the present invention, " the second chip is packaged in the blank area of the first chip by reverse installation process
On domain " before further include：
Third wiring layer again is formed on the second surface of first chip, wiring layer is direct or indirect again for the third
Corresponding weld pad and electrical connection section is connected.
As a further improvement of the present invention, one end of third wiring layer again is electrically connected to weld pad or the first cloth again
Line layer, the other end are electrically connected to electrical connection section or the second wiring layer again.
As a further improvement of the present invention, " on solder mask formed electrical connection described first again wiring layer first electricity
Further include after second electric connection terminal of the described second wiring layer again of connection terminal and electrical connection " step：
Electrically conduct corresponding first electric connection terminal and the second electric connection terminal.
As a further improvement of the present invention, " electrically conduct corresponding first electric connection terminal and the second electric connection terminal "
Specially：
Corresponding first electric connection terminal and the second electric connection terminal are connected by electric connection line.
As a further improvement of the present invention, " electrically conduct corresponding first electric connection terminal and the second electric connection terminal "
Specially：
Wiring board is provided, the wiring board is equipped with line layer；
Wiring board is packaged on stack type chip packaging structure, corresponding first electric connection terminal is connected by line layer
With the second electric connection terminal.
As a further improvement of the present invention, first electric connection terminal is formed on the first chip second surface extremely
Few side.
As a further improvement of the present invention, be packaged in the white space on each first chip second surface one or
Multiple second chips.
As a further improvement of the present invention, the packaging method further includes：
The solder mask of formation is toasted；
Remove the part of solder mask of the first chip edge.
For the another object for realizing foregoing invention, the present invention is adopted the following technical scheme that, a kind of stacked chip packages knot
Structure, the encapsulating structure include：
First chip has white space on first chip surface；
Second chip, second chip are flip-chip, and second flip-chip is packaged in first chip
On white space.
As a further improvement of the present invention, the encapsulating structure includes：
First chip, first chip have each other relative first surface and the second surface, first chip
With the weld pad for being located at the induction zone of the first surface and being electrically coupled with induction zone；
The through-hole for being formed in the second surface of first chip and extending towards first surface, the via bottoms exposure
The weld pad；
The first wiring layer again being formed on first chip, the described first bottom and side wall of the wiring layer from through-hole again
Extend to the second surface of first chip, described first again wiring layer be electrically connected with the weld pad；
It is formed on first chip not by the electrical connection section in the first white space that wiring layer covers again；
The second wiring layer again being formed in the white space, described second again wiring layer be electrically connected with the electrical connection section
Connect, and second again wiring layer enclose the region for setting and being formed from electrical connection section and extend outwardly；
Second chip, second chip are packaged on the white space of the first chip by reverse installation process, and described second
Chip is flip-chip, and the second chip and electrical connection section contraposition encapsulate；
The second surface top for being formed in first chip and the solder mask in the through-hole, the solder mask covering
Described first wiring layer and the second wiring layer again again；
Be formed on the solder mask and be electrically connected described first again the first electric connection terminal of wiring layer and electrical connection institute
State the second electric connection terminal of the second wiring layer again.
As a further improvement of the present invention, third wiring layer again, institute are formed on the second surface of first chip
Stating third, corresponding weld pad and electrical connection section is directly or indirectly connected in wiring layer again.
As a further improvement of the present invention, one end of third wiring layer again is electrically connected to weld pad or the first cloth again
Line layer, the other end are electrically connected to electrical connection section or the second wiring layer again.
As a further improvement of the present invention, the encapsulating structure includes electrically conduct corresponding first electric connection terminal and the
The electric connection line of two electric connection terminals.
As a further improvement of the present invention, the encapsulating structure further includes being packaged on the first chip and the second chip
Wiring board, the wiring board are equipped with the line layer of electrically conduct corresponding first electric connection terminal and the second electric connection terminal.
As a further improvement of the present invention, first electric connection terminal is formed on the first chip second surface extremely
Few side.
As a further improvement of the present invention, be packaged in the white space on each first chip second surface one or
Multiple second chips.
As a further improvement of the present invention, the solder mask with a thickness of 10 μm~50 μm.
Compared with prior art, stacked chip packages method of the invention and encapsulating structure are by by the second chip package
In in the white space of the first chip, stacked package takes full advantage of the white space of the first chip back, reduces encapsulation
The area of plane of structure realizes the area of plane miniaturization of encapsulation.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts,
It is also possible to obtain other drawings based on these drawings.
Fig. 1 is the planar structure schematic diagram of wafer in first embodiment of the invention；
Fig. 2 is the structural schematic diagram of the first chip in first embodiment of the invention；
Fig. 3 is that the first chip forms through-hole and removes the structural representation after part of matrix in first embodiment of the invention
Figure；
Fig. 4 is to form the first structural schematic diagram after wiring layer again in first embodiment of the invention on the first chip；
Fig. 5 is to form electrical connection section and the second structure after wiring layer again in first embodiment of the invention on the first chip
Schematic diagram；
Fig. 6 is the structural schematic diagram in first embodiment of the invention after the second chip of flip-chip packaged；
Fig. 7 is the side structure schematic view of stack type chip packaging structure in first embodiment of the invention；
Fig. 8 is the overlooking structure diagram of stack type chip packaging structure in first embodiment of the invention；
Fig. 9 is the overlooking structure diagram of stack type chip packaging structure in second embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It should be noted that the purpose for providing these attached drawings is in order to help to understand the embodiment of the present invention, without answering
It is construed to improper restriction of the invention.For the sake of becoming apparent from, size as shown in the figure is not necessarily to scale, and may be put
Greatly, it reduces or other changes.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.In addition,
Structure of the fisrt feature described below in the "upper" of second feature may include that the first and second features are formed as directly contacting
Embodiment, also may include the embodiment that other feature is formed between the first and second features, such first and second
Feature may not be direct contact.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
To join shown in Fig. 1, wafer 100 has the first chip 10 of more grids arrangement in first embodiment of the invention, the
One chip 10 can be image sensor dice, fingerprint chip etc., have cutting channel, subsequent completion between the first chip 10
After packaging technology and test, the first chip is separated along cutting channel.It should be noted that two neighboring first chip 10 it
Between cutting channel be only reserved between two the first chips 10 be left white region for cutting, cut the of channel and two sides
Do not have actual boundary line between one chip 10.
As shown in connection with fig. 2, the first chip 10 has each other relative first surface 101 and second surface 102, the first table
Face 101 and second surface 102 are it is also assumed that be two surfaces of the substrate of wafer 100, every one first chip 10 has induction
Area 11 and the multiple weld pads 12 being electrically coupled with induction zone 11, weld pad 12 be located at the periphery of induction zone 11 and with the equal position of induction zone 11
In on the first surface 101 of the first chip 10, induction zone 11 and weld pad 12 are set to the front of the first chip 10, the first chip
The corresponding second surface 102 with the first chip 10 in 10 back side.
Join shown in Fig. 2 to Fig. 8, the first wiring layer 15 again is formed in the second surface 102 of the first chip 10, at least for electricity
Connect weld pad 12.First is provided with the first electric connection terminal 17 on wiring layer 15 again, and in present embodiment preferably, first is electrically connected
Connecting terminal is configured to solder-bump (BGA), naturally it is also possible to it is formed in the first plane weld pad (LGA) on wiring layer 15 again,
The contact terminal being made of a part of the first wiring layer 15 again.First electric connection terminal 17 by first again wiring layer 15 with
Weld pad 12 is electrically connected, and for being electrically connected with external circuit.The metal line materials being routed again are copper, then be routed copper and weld pad 12 it
Between there is enhancing to be routed copper again and weld pad 12 is attached to each other the metal or alloy film of power, which can be
Nickel, titanium, nickel chromium triangle, titanium tungsten etc..The forming method of first wiring layer 15 again include metal film, photoetching, copper facing, striping, copper/titanium erosion
The sequence technique carved.
The second surface 102 of first chip 10 is provided with the through-hole 13 of the matrix through the first chip 10, and through-hole 13 is used for
Expose weld pad 12, in order to realize being electrically connected for the first electric connection terminal 17 and weld pad 12.Wherein, through-hole 13 can be double-deck logical
Hole, inverted trapezoidal hole or straight hole.Specifically, straight hole can be cylindrical or prismatic through-hole.At this point, through-hole 13 is by first
Surface 101 is directed toward on the direction of second surface 102, and the aperture of through-hole is gradually constant.Certainly, the cross section of straight hole can also be square
Shape, ellipse or other shapes.Through-hole 13 and weld pad 12 correspond, and through-hole 13 is for exposing corresponding weld pad 12.It is formed
The method of through-hole 13 has laser boring, photoetching etc..
First electric connection terminal 17 passes through first be arranged in through-hole 13, and wiring layer 15 is electrically connected with weld pad 12 again.First
Also there is between wiring layer 15 and the matrix of the first chip 10 insulating layer 14 again.Insulating layer 14 covers the side wall of through-hole 13, and reveals
The bottom of through-hole 13 out, in order to first, wiring layer 15 and weld pad 12 are electrically connected again.First again wiring layer 15 cover through-hole 13
Bottom and insulating layer 14.Insulating layer 14 is preferably configured to insulation/dielectric film, and insulation/dielectric film is the exhausted of photaesthesia
Edge/dielectric film, such as SU-8.Photaesthesia dielectric film can pass through a sequence process deposits of rotary coating or press mold, photoetching
At the back side of the first chip 10.
Join shown in Fig. 7, Fig. 8, on the second surface 102 of the first chip 10 in present embodiment, the first wiring layer 15 again
It is distributed in the side of second surface 102 with the first electric connection terminal 17, on the second surface 102 of the first chip 10 again not by first
The region of wiring layer 15 and the covering of the first electric connection terminal 17 is white space, is packaged with the second chip 20 in white space.It is excellent
Selection of land is illustrated in present embodiment by taking second chip 20 as an example, can also encapsulate in other embodiments multiple
Second chip 20.In addition, first wiring layer 15 and the first electric connection terminal 17 are also not necessarily limited to be distributed in the one of second surface 102 again
Side, all embodiments that the white space for encapsulating the second chip 20 is formed on second surface 102 belong to the present invention
The range protected.
Second chip 20 can be control chip, control chip, or image sensor dice, fingerprint chip etc..
The second chip 20 in present embodiment is flip-chip (FC, Flip Chip), and the is packaged in by the way of flip-chip packaged
On one chip 10 in the white space of second surface 102.
Specifically, several electrical connection sections 21 are formed in white space, when the second 20 flip-chip packaged of chip and electrical connection section
21 are aligned, to realize being electrically connected for electrical connection section 21 and the second chip 20.
The second wiring layer 22 again are formed in the second surface 102 of the first chip 10, at least for being electrically connected electrical connection section 21.
Second is provided with the second electric connection terminal 23 on wiring layer 22 again, in present embodiment preferably, the second electric connection terminal construction
For solder-bump (BGA), naturally it is also possible to be formed in the second plane weld pad (LGA) on wiring layer 22 again, i.e., again by second
The contact terminal that a part of wiring layer 22 is constituted.Second electric connection terminal 23 passes through the second wiring layer 22 and electrical connection section 21 again
Electrical connection, and for being electrically connected with external circuit.The metal line materials being routed again are copper, then are routed between copper and electrical connection section 21
There is enhancing to be routed copper again and electrical connection section 21 is attached to each other the metal or alloy film of power, which can be
Nickel, titanium, nickel chromium triangle, titanium tungsten etc..The forming method of second wiring layer 22 again include metal film, photoetching, copper facing, striping, copper/titanium erosion
The sequence technique carved.
Specifically, first again wiring layer 15 and second again 22 surface of wiring layer be additionally provided with solder mask 16, solder mask 16
Surface has the opening for being provided with the first electric connection terminal 17 and the second electric connection terminal 23, in order to which the first electric connecting terminal is arranged
Son 17 and second electric connection terminal 23, so that the first of the first electric connection terminal 17 and the second electric connection terminal 23 and opening again
Wiring layer 15 and the second electrical connection of wiring layer 22 again.The method for forming solder mask 16 includes deposition, photoetching, chemical plating nickel aluminum
One sequence technique.In actual technique, the thickness of the solder mask 16 between two chips can be greater than the resistance in the middle part of each chip
The thickness of layer can toast solder mask to prevent solder mask excessive in chip edge accumulation and be removed first
The part of solder mask of chip edge so that solder mask with a thickness of 10 μm~50 μm.
Further, third wiring layer again is also formed on the second surface 102 of the first chip 10 in the present embodiment
24, corresponding weld pad 12 and electrical connection section 21 is directly or indirectly connected in wiring layer 24 to third again, specifically, third wiring layer 24 again
One end be electrically connected to weld pad 12 or first wiring layer 15, the other end are electrically connected to electrical connection section 21 or second and are routed again again
Layer 22, can so be connected corresponding weld pad 12 and electrical connection section 21.The forming method of third wiring layer 24 again includes metal
Film, photoetching, copper facing, striping, one sequence technique of copper/titanium etching.
Specifically, stacked chip packages method involved in present embodiment, specific step is as follows for the packaging method：
Join shown in Fig. 1, Fig. 2, wafer 100 is provided, wafer 100 has the first chip 10 of more grids arrangement, the first core
Piece 10 can be image sensor dice, fingerprint chip etc., and the first chip 10 has each other relative first surface 101 (front)
And second surface 102 (back side), the first chip 10 have the induction zone 11 for being located at first surface and are electrically coupled with induction zone
Weld pad 12, induction zone 11 is set to first surface 101, has cutting channel between the first adjacent chip 10, in order to
Cutting process is carried out in subsequent cutting technique.
Join shown in Fig. 3, by photoetching and plasma etching process, forms direction in the second surface 102 of the first chip 10
The through-hole 13 that first surface extends, 13 bottom-exposed of through-hole go out weld pad 12, then remove the part base at 10 edge of the first chip again
Body (matrix between the adjacent welding-pad of i.e. adjacent encapsulating structure).One way in which is that second surface 102 is made to form step
Surface, in this way, the thickness of the substrate of the first part of encapsulating structure is less than the thickness of the substrate of second part, that is to say, that through-hole
The thickness of the matrix of 13 peripheries is greater than the thickness of the matrix of 13 inside of through-hole, so that the depth of through-hole 13 becomes smaller accordingly,
And then avoid the opening of through-hole 13 in the next steps clogging by insulating materials or metal, it can avoid empty (void) occur
Or linear slit (seam), the reliability of product is improved, is conducive to carry out large-scale production.Also, due to eliminating part of matrix,
So that the outer dimension of encapsulating structure becomes smaller, chip signal delay can be reduced, reduce power consumption, improve the performance of semiconductor devices.
In the specific embodiment of the present invention, part of matrix is removed using the mode of machine cuts, to ensure outside through-hole 13
The matrix thickness enclosed becomes smaller.
Join shown in Fig. 4, the back side of the first chip 10 after photoetching and plasma etching is formed by gas phase deposition technology
The surface of insulating layer 14, covering is all faces for exposing the back side of the first chip 10, i.e. insulating layer 14 is covered in the first core
In the upper and lower surface of the ledge surface at the back side of piece 10 and side, through-hole 13.Next, in the second surface of the first chip 10
102 form the first wiring layer 15 again that the second surface 102 of the first chip 10 is extended to from the bottom and side wall of through-hole 12, and first
Again the forming method of wiring layer 15 include metal film, photoetching, copper facing, striping, the etching of copper/titanium a sequence technique.First core
On the second surface 102 of piece 10 not by the first region that wiring layer 15 covers again be white space.
Join shown in Fig. 5, form electrical connection section 21 in white space, and forms the second wiring layer again in white space
22, second again wiring layer 22 be electrically connected with electrical connection section 21, and second again wiring layer 22 area for setting and being formed is enclosed from electrical connection section 21
Domain extends outwardly, the forming method of the second wiring layer 22 again include metal film, photoetching, copper facing, striping, copper/titanium etching one
Sequence technique.
In addition, third wiring layer 24 again, third are formed on the second surface 102 of the first chip 10 in the present embodiment
Corresponding weld pad 12 and electrical connection section 21 is directly or indirectly connected in wiring layer 24 again, specifically, one end of third wiring layer 24 again
It is electrically connected to weld pad 12 or the first wiring layer 15 again, the other end is electrically connected to electrical connection section 21 or the second wiring layer 22 again,
Corresponding weld pad 12 and electrical connection section 21 can so be connected.The forming method of third wiring layer 24 again include metal film, light
Quarter, copper facing, striping, one sequence technique of copper/titanium etching.
Join shown in Fig. 6, the second chip 20 is provided, the second chip 20 can be control chip, control chip, or shadow
As sensor chip, fingerprint chip etc..Second chip 20 be flip-chip (FC, Flip Chip), by the second chip 20 be electrically connected
Socket part 21 is aligned, then the second chip 20 is packaged in second surface 102 on the first chip 10 by way of flip-chip packaged
White space in.
Join shown in Fig. 7, forms solder mask 16, solder mask in 102 top of second surface of the first chip 10 and through-hole
16 coverings first wiring layer 22 and third wiring layer 24 again again of wiring layer 15, second again.Using spraying process in ledge surface
Upper and lower surface and side, the side wall of through-hole 13 and bottom form solder mask 16, facilitate subsequent upper soldered ball technique, play welding resistance, protection
The effect of chip.
After completing above-mentioned technique, the solder mask 16 first to the encapsulating structure of formation can be toasted, then be removed
The part of solder mask of first chip edge, or it is first removed the part of solder mask 16 of chip edge, then carry out to solder mask
Baking, final solder mask with a thickness of 10 μm~50 μm.
It is then open on solder mask 16, opening is for exposed portion first wiring layer 15 and the second wiring layer again again
22, the first electric connection terminal 17 is formed in opening and the second electric connection terminal 23, the first electric connection terminal 17 and second are electrically connected
Connecting terminal 23 respectively with first again wiring layer 15 and second again wiring layer 22 be electrically connected.First electric connection terminal 17 and second is electrically connected
Connecting terminal 23 and can be solder-bump or plane weld pad.
Cutting separation finally is carried out to wafer 100, obtains multiple independent stack type chip packaging structures, stacked chips
Encapsulating structure is as shown in Figure 7, Figure 8.
Join shown in Fig. 9, in second embodiment of the present invention, the first cloth again is simply formed on the back side of the first chip 10
Line layer 15 and the second wiring layer 22 again, and and the third of the corresponding weld pad of not set conducting and electrical connection section wiring layer 24 again.Phase
The weld pad and electrical connection section answered pass through external circuit board electrical connection, specifically, the stacked chip packages in present embodiment
Structure is packaged with external wiring board, and wiring board passes through weld pad and the first electric connection terminal 17 and the second electric connecting terminal respectively
Son 23 is electrically connected, meanwhile, line layer is equipped on wiring board between corresponding weld pad, corresponding first electrical connection is realized by line layer
The electrical connection of terminal 17 and the second electric connection terminal 23, to realize the communication between the first chip 10 and the second chip 20.
In third embodiment of the present invention, all fours in stack type chip packaging structure and second embodiment,
Also not set third wiring layer 24 again, but corresponding first electric connecting terminal is directly directly connected to by electric connection line (conducting wire etc.)
Son 17 and the second electric connection terminal 23, are directly realized by the first electric connection terminal 17 and the second electric connection terminal 23 by electric connection line
Electrical connection, to realize the communication between the first chip 10 and the second chip 20.
It should be understood that in the respective embodiments described above, the first electric connection terminal 17 and first again wiring layer 15 be distributed in
The side at 10 back side of the first chip, rest part are white space, in other embodiments the first electric connection terminal 17 and
Wiring layer 15 can also be distributed in the one side or the multi-lateral at 10 back side of the first chip again and again, can also be distributed in 10 back side of the first chip
Intermediate region, other regions are to be used to encapsulate the white space of the second chip 20, and no longer citing is described in detail herein.
Stacked chip packages method and encapsulating structure of the invention by by the second chip package in the sky of the first chip
In white region, stacked package takes full advantage of the white space of the first chip back, reduces the area of plane of encapsulating structure,
Realize the area of plane miniaturization of encapsulation.
Although this specification is described in terms of embodiments, but not each embodiment only includes an independent skill
Art scheme, this description of the specification is merely for the sake of clarity, and those skilled in the art should be using specification as one
A entirety, the technical solution in each embodiment may also be suitably combined to form it will be appreciated by those skilled in the art that its
His embodiment.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (19)
1. a kind of stacked chip packages method, which is characterized in that the packaging method includes：
First chip is provided, there is white space on first chip surface；
The second chip is provided, second chip is flip-chip；
Second flip-chip is packaged on the white space of first chip.
2. stacked chip packages method according to claim 1, which is characterized in that the packaging method includes：
There is provided wafer, the wafer has the first chip of more grids arrangement, and first chip has relative to each other the
One surface and second surface, first chip have the induction zone for being located at the first surface and are electrically coupled with induction zone
Weld pad；
The through-hole extended towards first surface is formed in the second surface of first chip, the via bottoms expose described
Weld pad；
Remove the part of matrix of the first chip edge；
Form the first wiring layer again on first chip, described first again wiring layer extended to from the bottom and side wall of through-hole
The second surface of first chip, described first again wiring layer be electrically connected with the weld pad；
Electrical connection section is not formed in the first white space that wiring layer covers again on first chip；
Form the second wiring layer again in the white space, described second again wiring layer be electrically connected with the electrical connection section, and
Second again wiring layer enclose the region for setting and being formed from electrical connection section and extend outwardly；
Second chip is packaged on the white space of the first chip by reverse installation process, second chip is flip-chip,
And second chip and the electrical connection section contraposition encapsulate；
Form solder mask in the second surface top of first chip and the through-hole, the solder mask covering described the
Wiring layer and the second wiring layer again again and again；
The described second cloth again of first electric connection terminal of wiring layer and electrical connection again of electrical connection described first is formed on solder mask
Second electric connection terminal of line layer；
Wafer is cut, multiple independent stack type chip packaging structures are obtained.
3. stacked chip packages method according to claim 2, which is characterized in that " the second chip is passed through upside-down mounting work
Skill is packaged on the white space of the first chip " before further include：
Third wiring layer again is formed on the second surface of first chip, wiring layer is directly or indirectly connected the third again
Corresponding weld pad and electrical connection section.
4. stacked chip packages method according to claim 3, which is characterized in that one end of third wiring layer again
It is electrically connected to weld pad or the first wiring layer again, the other end is electrically connected to electrical connection section or the second wiring layer again.
5. stacked chip packages method according to claim 2, which is characterized in that " form electrical connection on solder mask
Second electric connection terminal of described first the described second wiring layer again of first electric connection terminal of wiring layer and electrical connection again " step
After further include：
Electrically conduct corresponding first electric connection terminal and the second electric connection terminal.
6. stacked chip packages method according to claim 5, which is characterized in that " electrically conduct corresponding first electricity
Connection terminal and the second electric connection terminal " is specially：
Corresponding first electric connection terminal and the second electric connection terminal are connected by electric connection line.
7. stacked chip packages method according to claim 5, which is characterized in that " electrically conduct corresponding first electricity
Connection terminal and the second electric connection terminal " is specially：
Wiring board is provided, the wiring board is equipped with line layer；
Wiring board is packaged on stack type chip packaging structure, corresponding first electric connection terminal and are connected by line layer
Two electric connection terminals.
8. stacked chip packages method according to claim 2, which is characterized in that first electric connection terminal is formed
In at least side on the first chip second surface.
9. stacked chip packages method according to claim 2, which is characterized in that on each first chip second surface
White space in be packaged with one or more second chips.
10. stacked chip packages method according to claim 2, which is characterized in that the packaging method further includes：
The solder mask of formation is toasted；
Remove the part of solder mask of the first chip edge.
11. a kind of stack type chip packaging structure, which is characterized in that the encapsulating structure includes：
First chip has white space on first chip surface；
Second chip, second chip are flip-chip, and second flip-chip is packaged in the blank of first chip
On region.
12. stack type chip packaging structure according to claim 11, which is characterized in that the encapsulating structure includes：
First chip, first chip have each other relative first surface and the second surface, and first chip has
Induction zone positioned at the first surface and the weld pad that is electrically coupled with induction zone；
The through-hole for being formed in the second surface of first chip and extending towards first surface, described in via bottoms exposure
Weld pad；
The first wiring layer again being formed on first chip, described first again wiring layer extend from the bottom and side wall of through-hole
To first chip second surface, described first again wiring layer be electrically connected with the weld pad；
It is formed on first chip not by the electrical connection section in the first white space that wiring layer covers again；
The second wiring layer again being formed in the white space, described second again wiring layer be electrically connected with the electrical connection section,
And second again wiring layer enclose the region for setting and being formed from electrical connection section and extend outwardly；
Second chip, second chip are packaged on the white space of the first chip by reverse installation process, second chip
For flip-chip, and the second chip and electrical connection section contraposition encapsulate；
The second surface top for being formed in first chip and the solder mask in the through-hole, described in solder mask covering
First wiring layer and the second wiring layer again again；
It is formed on the solder mask and is electrically connected described first and the first electric connection terminal of wiring layer and be electrically connected described the again
Second electric connection terminal of two wiring layers again.
13. stack type chip packaging structure according to claim 12, which is characterized in that the second table of first chip
Third wiring layer again is formed on face, corresponding weld pad and electrical connection section is directly or indirectly connected in wiring layer to the third again.
14. stack type chip packaging structure according to claim 13, which is characterized in that the third again wiring layer one
End is electrically connected to weld pad or the first wiring layer again, and the other end is electrically connected to electrical connection section or the second wiring layer again.
15. stack type chip packaging structure according to claim 12, which is characterized in that the encapsulating structure includes electrically
The electric connection line of corresponding first electric connection terminal and the second electric connection terminal is connected.
16. stack type chip packaging structure according to claim 12, which is characterized in that the encapsulating structure further includes envelope
Loaded on the wiring board on the first chip and the second chip, the wiring board be equipped with electrically conduct corresponding first electric connection terminal and
The line layer of second electric connection terminal.
17. stack type chip packaging structure according to claim 12, which is characterized in that the first electric connection terminal shape
At in at least side on the first chip second surface.
18. stack type chip packaging structure according to claim 12, which is characterized in that each first chip second surface
On white space in be packaged with one or more second chips.
19. stack type chip packaging structure according to claim 12, which is characterized in that the solder mask with a thickness of 10
μm~50 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810904094.3A CN108831861A (en) | 2018-08-09 | 2018-08-09 | Stacked chip packages method and encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810904094.3A CN108831861A (en) | 2018-08-09 | 2018-08-09 | Stacked chip packages method and encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108831861A true CN108831861A (en) | 2018-11-16 |
Family
ID=64152079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810904094.3A Pending CN108831861A (en) | 2018-08-09 | 2018-08-09 | Stacked chip packages method and encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108831861A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990082267A (en) * | 1996-12-04 | 1999-11-25 | 야스카와 히데아키 | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| US20020025587A1 (en) * | 2000-06-27 | 2002-02-28 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
| CN101800207A (en) * | 2010-03-12 | 2010-08-11 | 晶方半导体科技（苏州）有限公司 | Packaging structure of semiconductor element and manufacture method thereof |
| CN102931173A (en) * | 2011-08-10 | 2013-02-13 | 台湾积体电路制造股份有限公司 | Multi-chip wafer level package |
| US20140377909A1 (en) * | 2013-06-21 | 2014-12-25 | Samsung Electronics Co., Ltd. | Semiconductor packages having through electrodes and methods for fabricating the same |
| CN106611715A (en) * | 2015-10-21 | 2017-05-03 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN106711118A (en) * | 2015-11-16 | 2017-05-24 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN107533985A (en) * | 2015-04-23 | 2018-01-02 | 苹果公司 | Vertical stacking system in package and its manufacture method including first order nude film, the second level nude film of back-to-back stacking and third level nude film and corresponding first redistribution layer, the second redistribution layer and the 3rd redistribution layer |
| WO2018054315A1 (en) * | 2016-09-26 | 2018-03-29 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN208580738U (en) * | 2018-08-09 | 2019-03-05 | 苏州晶方半导体科技股份有限公司 | Stack type chip packaging structure |
-
2018
- 2018-08-09 CN CN201810904094.3A patent/CN108831861A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990082267A (en) * | 1996-12-04 | 1999-11-25 | 야스카와 히데아키 | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| US20020025587A1 (en) * | 2000-06-27 | 2002-02-28 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
| CN101800207A (en) * | 2010-03-12 | 2010-08-11 | 晶方半导体科技（苏州）有限公司 | Packaging structure of semiconductor element and manufacture method thereof |
| CN102931173A (en) * | 2011-08-10 | 2013-02-13 | 台湾积体电路制造股份有限公司 | Multi-chip wafer level package |
| US20140377909A1 (en) * | 2013-06-21 | 2014-12-25 | Samsung Electronics Co., Ltd. | Semiconductor packages having through electrodes and methods for fabricating the same |
| CN107533985A (en) * | 2015-04-23 | 2018-01-02 | 苹果公司 | Vertical stacking system in package and its manufacture method including first order nude film, the second level nude film of back-to-back stacking and third level nude film and corresponding first redistribution layer, the second redistribution layer and the 3rd redistribution layer |
| CN106611715A (en) * | 2015-10-21 | 2017-05-03 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN106711118A (en) * | 2015-11-16 | 2017-05-24 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| WO2018054315A1 (en) * | 2016-09-26 | 2018-03-29 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN208580738U (en) * | 2018-08-09 | 2019-03-05 | 苏州晶方半导体科技股份有限公司 | Stack type chip packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100833589B1 (en) | Stack package | |
| US7880310B2 (en) | Direct device attachment on dual-mode wirebond die | |
| KR101211044B1 (en) | Semiconductor integrated circuit having multi-chip structure | |
| KR102556517B1 (en) | Stack package include bridge die | |
| KR101190744B1 (en) | Semiconductor integrated circuit having multi-chip structure | |
| JP2010245536A (en) | Semiconductor device and manufacturing method of the same | |
| CN103794569A (en) | Package structure and method for fabricating the same | |
| US20210280563A1 (en) | Semiconductor device, fabrication method thereof, package and fabrication method thereof | |
| KR20010018694A (en) | Manufacturing method for three demensional stack chip package | |
| CN110335859A (en) | A kind of encapsulating structure of multi-chip and preparation method thereof based on TSV | |
| CN109300882A (en) | Stack embedded packaging structure and preparation method thereof | |
| TW201532232A (en) | Package assembly and method for manufacturing the same | |
| JP5358089B2 (en) | Semiconductor device | |
| CN108711569A (en) | With the multichip packaging structure and preparation method thereof for accommodating filter chip chamber | |
| KR20020012061A (en) | Wafer level stack package and method of fabricating the same | |
| US8637987B2 (en) | Semiconductor assemblies with multi-level substrates and associated methods of manufacturing | |
| CN210136866U (en) | Fan-out packaging structure | |
| CN103633038B (en) | Encapsulating structure and forming method thereof | |
| CN208655635U (en) | Stack embedded packaging structure | |
| KR101653563B1 (en) | Stack type semiconductor package and method for manufacturing the same | |
| CN208580738U (en) | Stack type chip packaging structure | |
| TWI549203B (en) | Metod for 3d stacking semiconductor packages to avoid bridging of interposer terminals | |
| CN208580737U (en) | Stack type chip packaging structure | |
| CN108831861A (en) | Stacked chip packages method and encapsulating structure | |
| KR20040102414A (en) | semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20231120 Address after: Room 120, Building B, No. 133 Changyang Street, Industrial Park, Suzhou City, Jiangsu Province, 215000 Applicant after: Suzhou Sicui Chegui Semiconductor Industry Technology Research Institute Co.,Ltd. Address before: 215000 No. 29, Tinglan lane, Suzhou Industrial Park, Suzhou City, Jiangsu Province Applicant before: CHINA WAFER LEVEL CSP Co.,Ltd. |
|
| TA01 | Transfer of patent application right |