CN108807178B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108807178B CN108807178B CN201710311595.6A CN201710311595A CN108807178B CN 108807178 B CN108807178 B CN 108807178B CN 201710311595 A CN201710311595 A CN 201710311595A CN 108807178 B CN108807178 B CN 108807178B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a substrate; etching the substrate to form a first groove in the substrate; pretreating the bottom and the side wall of the first groove by using pretreatment gas to form a second groove, wherein the pretreatment gas and the bottom and the side wall of the first groove are subjected to chemical reaction; and forming an epitaxial layer in the second groove. The size of the second groove can be controlled through the flow and the etching time of the introduced pretreatment gas, so that the size of the epitaxial layer can be controlled, and the performance of the formed semiconductor structure is improved. In addition, the energy of the pretreatment gas is low, so that the side wall of the second groove is not easy to lose, and an epitaxial layer with a complete structure can be formed. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. In order to improve the integration level, the density of transistors is increasing and the pitch is gradually reduced.
The development of semiconductor devices toward high integration is accompanied by a problem of a decrease in channel carrier mobility. To increase the transistor channel carrier mobility rate, the prior art has introduced strained silicon technology. The principle of the strained silicon technology is to epitaxially grow a stress layer with a lattice constant different from that of a silicon substrate in the drain region and the source region of a transistor. The stress layer can provide stress for the channel, so that the migration rate of carriers in the channel can be improved, and the performance of the formed transistor can be improved.
However, the stress layer formed by the conventional method for forming the semiconductor structure has poor performance, which results in poor performance of the formed semiconductor structure.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; etching the substrate to form a first groove in the substrate; pretreating the bottom and the side wall of the first groove by using pretreatment gas to form a second groove, wherein the pretreatment gas and the bottom and the side wall of the first groove are subjected to chemical reaction; and forming an epitaxial layer in the second groove.
Optionally, the etching process is one or a combination of a dry etching process and a wet etching process.
Optionally, the pre-treated pre-treatment gas comprises HCl.
Optionally, the parameters of the preprocessing include: the temperature is 650-850 ℃.
Optionally, the pretreated pretreatment gas further comprises GeH 4 。
Optionally, the temperature of the pretreatment is 630-830 ℃.
Optionally, before the etching process, the method further includes: and forming a grid on the substrate, wherein the first grooves are respectively positioned in the substrate at two sides of the grid.
Optionally, the first groove is U-shaped or Σ -shaped; the second groove is of a sigma shape.
Optionally, the depth of the first groove is 40nm to 50nm, and the width of the first groove is 40nm to 55 nm; the side wall of the second groove is provided with a tip, the tip faces the grid, the depth of the second groove is 45 nm-55 nm, the distance from the tip of the side wall of the second groove to the surface of the substrate is 18 nm-22 nm, and the absolute value of the displacement from the side wall of the grid to the adjacent tip is less than 5 nm.
Optionally, the pretreatment process parameters include: the pretreatment gas is HCl, and the flow rate of the pretreatment gas is 130 sccm-170 sccm; the pretreatment time is 80-220 s; alternatively, the pretreatment gas is HCl and GeH 4 The flow rate of HCl is 130 sccm-170 sccm, GeH 4 The flow rate of (2) is 6.5 sccm-8.5 sccm, and the pretreatment time is 20 s-40 s.
Optionally, the epitaxial layer is made of silicon germanium or silicon carbide.
Optionally, the substrate is made of monocrystalline silicon.
Optionally, the substrate surface is a (100) crystal plane.
Optionally, before performing the etching process, the method further includes: respectively forming a first doping area and a second doping area in the substrate, wherein the first doping area is in contact with the second doping area; the number of the first grooves, the number of the second grooves and the number of the epitaxial layers are two; the two epitaxial layers are respectively a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is positioned in the first doped region, and the second epitaxial layer is positioned in the second doped region; the first epitaxial layer and the first doped region have first ions therein, the second epitaxial layer and the second doped region have second ions therein, and the first ions are of opposite conductivity type to the second ions.
Optionally, before the etching process, the method further includes: respectively forming a first doping area, a second doping area and a third doping area in the substrate, wherein the second doping area is positioned between the first doping area and the third doping area, the first doping area is in contact with the second doping area, and the third doping area is in contact with the second doping area; the number of the first grooves, the number of the second grooves and the number of the epitaxial layers are three respectively, the three epitaxial layers are a first epitaxial layer, a second epitaxial layer and a third epitaxial layer respectively, the first epitaxial layer is located in the first doping region, the second epitaxial layer is located in the second doping region, and the third epitaxial layer is located in the third doping region; the first epitaxial layer and the first doped region are provided with first ions, the second epitaxial layer and the second doped region are provided with second ions, the third epitaxial layer and the third doped region are provided with third ions, the conductivity types of the first ions and the third ions are the same, and the conductivity types of the first ions and the second ions are opposite.
Correspondingly, the invention also provides a semiconductor structure formed by the method.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the pretreatment is carried out after the etching treatment. Because the pretreatment is carried out on the bottom and the side wall of the first groove through the pretreatment gas, the pretreatment process can be controlled through the flow and the etching time of the introduced pretreatment gas, so that the size of the second groove is controlled, the size of the epitaxial layer can be controlled, and the performance of the formed semiconductor structure is improved. In addition, the pretreatment gas only pretreats the bottom and the side wall of the first groove through chemical reaction with the bottom and the side wall of the first groove, and the energy of the pretreatment gas is low, so that the side wall of the second groove is not easily lost, and an epitaxial layer with a complete structure can be formed. And the side wall and the bottom of the first groove are pretreated, so that the defects of the side wall and the bottom of the first groove can be reduced. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Furthermore, the pretreatment process enables the second groove to be of a sigma shape, and the tip of the side wall of the second groove is close to the channel of the formed transistor, so that the stress of the epitaxial layer on the channel of the transistor can be increased, the migration rate of carriers in the channel of the transistor can be increased, and the performance of the formed semiconductor structure can be improved.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 6 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The prior art semiconductor structures and methods for forming the same have a number of problems, including: the resulting semiconductor structure has poor performance.
The reason for the poor performance of the formed semiconductor structure is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to 2 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided; a gate structure 110 is formed on the substrate 100.
With continued reference to fig. 1, the substrate 100 on both sides of the gate structure 110 is etched, and a groove 121 is formed in the substrate 100 on both sides of the gate structure.
Referring to fig. 2, an epitaxial layer 120 is formed in the recess 121 through an epitaxial growth process.
The process for forming the groove 121 is one or a combination of a dry etching process and a wet etching process.
In order to enable the epitaxial layer 120 to provide a large channel stress for the PMOS transistor, the process of forming the recess 121 includes wet etching, so that the recess 121 is of a "Σ" type. The substrate 100 is monocrystalline silicon, the atomic density of the (111) crystal plane of the monocrystalline silicon is greater than the atomic density of the (100) crystal plane, so that the etching of the (111) crystal plane of the silicon is difficult, the etching rate of the (111) crystal plane of the silicon is low, and the groove 121 can be made to be in a sigma shape by wet etching. However, as the size of the semiconductor structure is reduced, the width of the gate structure 110 is also reduced, and since the wet etching is not easy to control, the grooves on the two sides of the gate structure 110 are easy to penetrate during the process of forming the groove 121, so that the formed semiconductor structure fails.
In other methods, the groove 121 may also be formed by using a dry etching method, in which the substrate 100 on both sides of the gate structure 110 is bombarded by using plasma with high energy to form the groove 121. Due to the high energy of the plasma, the sidewalls of the recess 121 are easily damaged, resulting in an incomplete structure of the epitaxial layer 120 formed in the recess 121, thereby making it difficult to provide sufficient stress to the transistor channel.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate; etching the substrate to form a first groove in the substrate; pretreating the bottom and the side wall of the first groove by using pretreatment gas to form a second groove, wherein the pretreatment gas is used for carrying out chemical reaction with the bottom and the side wall of the first groove; and forming an epitaxial layer in the second groove.
The etching process can be controlled through the flow and the etching time of the introduced pretreatment gas, so that the size of the second groove is controlled, the size of the epitaxial layer can be controlled, and the performance of the formed semiconductor structure is improved. In addition, because the pretreatment gas etches the bottom and the side wall of the first groove by only carrying out chemical reaction with the bottom and the side wall of the first groove, the side wall of the second groove is not easy to be lost, and an epitaxial layer with a complete structure can be formed. The side wall and the bottom of the first groove are pretreated, so that the defects of the side wall and the bottom of the first groove can be reduced. Therefore, the forming method can improve the performance of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 6 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate is provided.
In this embodiment, the substrate includes a base 200 and a fin 201 on the base 200. In other embodiments, the substrate may also be a planar substrate, for example: a germanium substrate, a silicon on insulator, a germanium on insulator, or a silicon germanium on insulator.
Specifically, the material of the substrate 200 and the fin 201 is silicon. In other embodiments, the material of the substrate and the fin portion may also be germanium or silicon germanium.
In this embodiment, the substrate is used to form a PMOS transistor. In other embodiments, the substrate may also be used to form resistors, diodes, transistors, or NMOS transistors.
Since the surface state density of the (100) crystal plane of silicon is low, the number of surface dangling bonds is small, and the mobility of surface carriers is high, which is beneficial to controlling the threshold voltage of the formed transistor in the switching state, in this embodiment, the crystal plane indexes of the surface of the substrate 200 and the top surface of the fin portion 201 are (100).
In this embodiment, the forming method further includes: an isolation structure (not shown) is formed on the substrate 200, and the isolation structure covers a portion of the sidewall of the fin 201.
The isolation structure is used to achieve isolation between the fins 201.
In this embodiment, the isolation structure is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride.
In this embodiment, the forming method further includes: a gate structure 210 is formed on the substrate. In other embodiments, the substrate is used to form a diode or a triode, the gate structure may not be formed.
Specifically, in the present embodiment, the gate structure 210 crosses over the fin 201, and covers a portion of the sidewall and the top surface of the fin 201.
In this embodiment, the gate structure 210 includes: a gate dielectric layer on the surface of the substrate; a gate electrode on the gate dielectric layer; a mask layer on the gate; and the side walls are positioned on the side wall surfaces of the gate dielectric layer, the grid electrode and the mask layer.
In this embodiment, the gate dielectric layer is made of silicon oxide.
In this embodiment, the gate is made of polysilicon. In other embodiments, the material of the gate may also be poly-germanium.
In this embodiment, the mask layer is made of silicon nitride, silicon oxynitride, or silicon oxide.
In this embodiment, the sidewall spacer is made of silicon nitride or silicon oxynitride.
Referring to fig. 4, the substrate is etched to form a first groove 211 therein.
In this embodiment, the fin portions 201 on both sides of the gate structure 210 are etched, and first grooves 211 are formed in the fin portions 201 on both sides of the gate structure 210.
The first recess 211 is subsequently used to form a second recess.
The etching treatment speed is high, and the production efficiency can be ensured.
The etching treatment process is one or two combination of a dry etching process and a wet etching process. Specifically, in this embodiment, the etching process is an anisotropic dry etching process. The anisotropic dry etching has a good line width control, and can easily control the size of the second groove 211, so that the first grooves 211 on both sides of the gate structure 210 can be prevented from being penetrated. In other embodiments, the etching process may further be isotropic dry etching, isotropic wet etching, or anisotropic wet etching.
It should be noted that, in the dry etching process, the substrate surface is bombarded by high-energy plasma, and the first groove 211 is formed in the substrate. The surface of the first recess 211 is easily damaged due to the high plasma energy.
In this embodiment, the first groove 211 is a U-shaped groove. In other embodiments, when the etching process is isotropic dry etching or isotropic wet etching, the first groove may also be bowl-shaped; when the etching process is anisotropic wet etching or a combination of dry etching and anisotropic wet etching, the first groove may also be a sigma-shaped groove.
In order to prevent the first grooves 211 on both sides of the gate structure 210 from being penetrated, the size of the first grooves 211 is not easily too large; if the size of the first groove 211 is too small, the process difficulty of the subsequent pretreatment is easily increased. Specifically, in this embodiment, the depth of the first groove 211 is 40nm to 50nm, and the width of the first groove 211 is 45nm to 55nm, for example, 50 nm.
In this embodiment, the distance y between the sidewall of the adjacent first recess 211 and the sidewall of the gate is 5nm to 7 nm.
Referring to fig. 5, the bottom and the sidewall of the first recess 211 are pre-treated by a pre-treatment gas to form a second recess 212, and the pre-treatment gas chemically reacts with the bottom and the sidewall of the first recess 211.
Because the pretreatment is performed on the bottom and the side wall of the first groove 211 by using the pretreatment gas, the pretreatment process can be controlled by the flow rate and the etching time of the introduced pretreatment gas, so that the size of the second groove 212 can be controlled, the size of the subsequently formed epitaxial layer can be controlled, and the performance of the formed semiconductor structure can be improved. In addition, because the pretreatment gas etches the bottom and the side wall of the first groove 211 through chemical reaction with the bottom and the side wall of the first groove 211, the energy of the pretreatment gas is low, so that the side wall of the second groove 212 is not easy to lose, and an epitaxial layer with a complete structure can be formed. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Note that the crystal plane index of the top surfaces of the substrate 200 and the fin 201 is (100). Since the atomic density of the (100) crystal plane of silicon is smaller than that of the (111) crystal plane, the processing rate of the (100) crystal plane by the pretreatment gas is greater than that of the (111) crystal plane. Therefore, after the sidewalls and the bottom of the first groove 211 are pretreated, the sidewall surface of the second groove 212 is easily pointed 213, and the second groove 212 is made to be of a "Σ" shape. The Σ -shaped second groove 212 is beneficial to complete the structure of the subsequently formed epitaxial layer, thereby improving the quality of the formed epitaxial layer.
In this embodiment, the dry etching has a good line width control, and the size of the second recess 211 can be easily controlled, so that the first recesses 211 at two sides of the gate structure 210 can be prevented from being penetrated through. However, the pre-treatment can repair or remove plasma damage to the sidewalls and bottom of the first recess 211.
The pretreatment can make the tip 213 of the second groove 212 closer to the formed transistor channel, so that the stress applied to the transistor channel by the subsequently formed epitaxial layer can be increased, the migration rate of carriers in the channel is increased, and the performance of the formed semiconductor structure is improved.
In this embodiment, the pretreatment gas includes HCl, which can react with silicon, thereby pretreating the sidewall and the bottom of the first groove 211 to form the second groove 212.
If the flow rate of the pretreatment gas is too large, the pretreatment rate is easily too fast, so that the pretreatment process is not easily controlled, and the second grooves 212 on the two sides of the gate structure 210 are easily penetrated through; if the flow rate of the pretreating gas is too small, the rate of the pretreatment is easily made too small, thereby lowering the production efficiency. Specifically, the flow rate of the pretreatment gas is 130sccm to 170sccm, such as 150 sccm.
The temperature of the pre-treatment affects the reaction rate of the pre-treatment gas with the sidewall and the bottom of the first recess 211. If the temperature of the pretreatment is too low, the reaction rate of the pretreatment gas with the bottom and the side wall of the first groove 211 is too low, which easily reduces the treatment efficiency; the requirement for the pretreatment apparatus is easily increased if the temperature of the pretreatment is too high. Specifically, in this embodiment, the temperature is 650 ℃ to 850 ℃, for example, 750 ℃.
The size of the second recess 212 may be controlled by controlling the time of the pre-treatment, thereby improving the performance of the formed semiconductor structure. Specifically, if the time for the pretreatment is too short, the size of the second groove 212 is easily too small, which affects the performance of the formed semiconductor structure; if the time for the pretreatment is too long, the second grooves 212 on both sides of the gate structure 210 are easily penetrated. Specifically, in this embodiment, the time for the pretreatment is 80s to 220s, for example, 200 s.
In other embodiments, the pretreatment gas is HCl and GeH 4 The flow rate of HCl is 130sccm to 170sccm, such as 150sccm, GeH 4 The flow rate of (2) is 6.5sccm to 8.5sccm, for example, 7.5 sccm; the temperature of the pretreatment is 630-830 ℃, for example, 730 ℃; the pretreatment time is 20s to 40sec, for example 30 s.
In this embodiment, the depth of the second groove 212 is 45nm to 55nm, specifically, the depth of the second groove 212 is 48nm, and the distance from the tip 213 of the sidewall of the second groove 212 to the surface of the substrate is 18nm to 22 nm. In other embodiments, the pretreatment gas is HCl and GeH 4 The depth of the second groove is 54 nm.
In this embodiment, the displacement x of the gate sidewall to the adjacent tip 213 is positive away from the center of the channel, and the displacement x of the gate sidewall to the adjacent tip 213 is negative toward the center of the channel.
In this embodiment, the absolute value of the displacement x of the gate sidewall to the adjacent tip is less than 5 nm. Specifically, the displacement x from the gate sidewall to the adjacent tip is-2 nm. In other embodiments, the displacement x of the gate sidewall to the adjacent tip is 3 nm.
Referring to fig. 6, an epitaxial layer 220 is formed in the second recess 212.
In this embodiment, the epitaxial layer 220 is used as a source-drain doped region of the formed PMOS transistor. In other embodiments, the epitaxial layer is used to form a diode, and the epitaxial layer is used as the anode or cathode of the diode. Or the epitaxial layer is used for forming the triode, and the epitaxial layer is used as a collector, an emitter or a base of the triode.
In this embodiment, the epitaxial layer 220 is made of silicon germanium. In other embodiments, the epitaxial layer is used as a source-drain doped region of the NMOS transistor, and the epitaxial layer is made of silicon carbide.
The lattice constant of silicon germanium is greater than that of silicon, which enables the epitaxial layer 220 to provide compressive stress to the channel of the PMOS transistor formed, thereby increasing the mobility rate of carriers in the PMOS transistor and improving the performance of the semiconductor structure formed.
Because the second groove 212 is of a sigma shape, the epitaxial layer 220 with a complete structure can be formed in the second groove 212, so that the epitaxial layer 220 can provide a larger stress for a transistor channel, and the performance of the formed semiconductor structure can be improved.
In this embodiment, the epitaxial layer 220 is formed through an epitaxial growth process, and during the epitaxial growth process, the epitaxial layer 220 is doped in situ, and doping ions are doped into the epitaxial layer 220.
In this embodiment, the dopant ions are P-type ions, such as boron ions or BF 2- Ions. In other embodiments, the outer layer is used to form an NMOS transistor, and the dopant ions may also be N-type ions, such as phosphorous ions or arsenic ions.
In addition, this embodiment is described by taking the formation of a MOS transistor as an example. In other embodiments, the forming method of the invention can also be used for forming a diode or a triode. When the forming method is used for forming a diode, before the etching treatment, the forming method further comprises the following steps: respectively forming a first doped region and a second doped region in the substrate, wherein the first doped region and the second doped region are contacted; the number of the first grooves, the second grooves and the epitaxial layers is two; the two epitaxial layers are respectively a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is positioned in the first doping region, and the second epitaxial layer is positioned in the second doping region; the first epitaxial layer and the first doped region have first ions therein, the second epitaxial layer and the second doped region have second ions therein, and the first ions are of opposite conductivity type to the second ions. When the forming method is used for forming the triode, before the etching treatment, the forming method further comprises the following steps: respectively forming a first doped region, a second doped region and a third doped region in the substrate, wherein the second doped region is positioned between the first doped region and the third doped region;
the number of the first grooves, the number of the second grooves and the number of the epitaxial layers are respectively three, the three epitaxial layers are respectively a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, the first epitaxial layer is positioned in the first doping region, the second epitaxial layer is positioned in the second doping region, the third epitaxial layer is positioned in the third doping region, the first doping region is in contact with the second doping region, and the third doping region is in contact with the second doping region; the first epitaxial layer and the first doped region are provided with first ions, the second epitaxial layer and the second doped region are provided with second ions, the third epitaxial layer and the third doped region are provided with third ions, the conductivity types of the first ions and the third ions are the same, and the conductivity types of the first ions and the second ions are opposite.
In summary, in the semiconductor structure provided by the embodiment of the invention, the sidewall and the bottom of the first groove are pretreated, so that the defects of the sidewall and the bottom of the first groove can be reduced. Because the pretreatment gas etches the bottom and the side wall of the first groove through chemical reaction with the bottom and the side wall of the first groove, the energy of the pretreatment gas is low, so that the loss of the side wall of the second groove is not easy to cause, and an epitaxial layer with a complete structure can be formed. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Embodiments of the present invention also provide a semiconductor structure formed by the method of forming a semiconductor structure shown in fig. 3 to 6.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
etching the substrate to form a first groove in the substrate, wherein the first groove is U-shaped, and the etching process is an anisotropic dry etching process;
pretreating the bottom and the side wall of the first groove by using pretreatment gas, wherein the pretreatment gas reacts with the bottom and the side wall of the first groove to etch the bottom and the side wall of the first groove so that the first groove is converted into a second groove, and the second groove is of a sigma shape;
forming an epitaxial layer in the second groove;
before the etching treatment, the method further comprises the following steps: forming a grid electrode on the substrate, wherein the first grooves are respectively positioned in the substrate at two sides of the grid electrode; the pretreatment process parameters comprise: the pretreatment gas is HCl, and the flow rate of the pretreatment gas is 130 sccm-170 sccm; the pretreatment time is 80-220 s; or the pretreatment gas is HCl and GeH 4 The flow rate of HCl is 130 sccm-170 sccm, GeH 4 The flow rate of (2) is 6.5 sccm-8.5 sccm, and the pretreatment time is 20 s-40 s.
2. The method of forming a semiconductor structure of claim 1, wherein the pre-treated pre-treatment gas comprises HCl, and the pre-treatment parameters comprise: the temperature is 650-850 ℃.
3. The method of forming a semiconductor structure of claim 1, wherein the pre-treated pre-treatment gas comprises HCl and GeH 4 The temperature of the pretreatment is 630-830 ℃.
4. The method for forming a semiconductor structure according to claim 1, wherein a depth of the first groove is 40nm to 50nm, and a width of the first groove is 40nm to 55 nm; the side wall of the second groove is provided with a tip, the tip faces the grid, the depth of the second groove is 45 nm-55 nm, the distance from the tip of the side wall of the second groove to the surface of the substrate is 18 nm-22 nm, and the absolute value of the displacement from the side wall of the grid to the adjacent tip is less than 5 nm.
5. The method of forming a semiconductor structure of claim 1, wherein the epitaxial layer is formed of silicon germanium or silicon carbide.
6. The method of forming a semiconductor structure of claim 1, wherein the material of the substrate is monocrystalline silicon.
7. The method of forming a semiconductor structure of claim 6, wherein the substrate surface is a (100) crystal plane.
8. The method of forming a semiconductor structure of claim 1, further comprising, prior to performing the etching process: respectively forming a first doping area and a second doping area in the substrate, wherein the first doping area is in contact with the second doping area;
the number of the first grooves, the number of the second grooves and the number of the epitaxial layers are two; the two epitaxial layers are respectively a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is positioned in the first doping region, and the second epitaxial layer is positioned in the second doping region; the first epitaxial layer and the first doped region have first ions therein, the second epitaxial layer and the second doped region have second ions therein, and the first ions are of opposite conductivity type to the second ions.
9. The method of forming a semiconductor structure of claim 1, further comprising, prior to performing the etching process: respectively forming a first doped region, a second doped region and a third doped region in the substrate, wherein the second doped region is positioned between the first doped region and the third doped region, the first doped region is in contact with the second doped region, and the third doped region is in contact with the second doped region;
the number of the first grooves, the number of the second grooves and the number of the epitaxial layers are respectively three, the three epitaxial layers are respectively a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, the first epitaxial layer is positioned in the first doping region, the second epitaxial layer is positioned in the second doping region, and the third epitaxial layer is positioned in the third doping region;
the first epitaxial layer and the first doped region are provided with first ions, the second epitaxial layer and the second doped region are provided with second ions, the third epitaxial layer and the third doped region are provided with third ions, the conductivity types of the first ions and the third ions are the same, and the conductivity types of the first ions and the second ions are opposite.
10. A semiconductor structure formed by the method of forming a semiconductor structure of any one of claims 1 to 9.
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