CN108803176A - Array substrate - Google Patents
Array substrate Download PDFInfo
- Publication number
- CN108803176A CN108803176A CN201810784035.7A CN201810784035A CN108803176A CN 108803176 A CN108803176 A CN 108803176A CN 201810784035 A CN201810784035 A CN 201810784035A CN 108803176 A CN108803176 A CN 108803176A
- Authority
- CN
- China
- Prior art keywords
- layer
- array substrate
- opening portion
- protective layer
- flatness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 146
- 239000011241 protective layer Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000007769 metal material Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 230000035515 penetration Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 229910010272 inorganic material Inorganic materials 0.000 claims description 3
- 239000011147 inorganic material Substances 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims 1
- 150000002927 oxygen compounds Chemical class 0.000 claims 1
- 238000000034 method Methods 0.000 description 16
- -1 IZO) Chemical compound 0.000 description 9
- 229910052738 indium Inorganic materials 0.000 description 9
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 4
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 3
- 229910001195 gallium oxide Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QTPKWWJYDWYXOT-UHFFFAOYSA-N [W+4].[O-2].[In+3] Chemical compound [W+4].[O-2].[In+3] QTPKWWJYDWYXOT-UHFFFAOYSA-N 0.000 description 1
- HXFVOUUOTHJFPX-UHFFFAOYSA-N alumane;zinc Chemical compound [AlH3].[Zn] HXFVOUUOTHJFPX-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- ATFCOADKYSRZES-UHFFFAOYSA-N indium;oxotungsten Chemical compound [In].[W]=O ATFCOADKYSRZES-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001706 oxygenating effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
An array substrate has a display region and a circuit region. The array substrate comprises a metal layer, a flat layer, a first protective layer and a conductive layer. The flat layer is located on the metal layer. The first protective layer is located on the flat layer and provided with an opening portion, the opening portion is located in the display area, and the opening portion exposes the flat layer but not exposes the metal layer. The conductive layer is located on the first protective layer and filled in the opening part to cover the exposed flat layer of the opening part.
Description
Technical field
This disclosure relates to a kind of array substrate, and more particularly to a kind of electrical array base for maintaining to stablize in viewing area
Plate.
Background technology
Semiconductor element there are many being carried in display panel, these semiconductor elements are especially in the presence of in array substrate
In.In the manufacturing process of display panel, aqueous vapor is often rich in ambiance.Once the aqueous vapor in process environments is excessive, hold
Easily these elements are generated to electrical adverse effect.Therefore, how to maintain the stabilization of semiconductor element in array substrate electrical,
Then become one of the direction that industry is made great efforts.
Invention content
This disclosure relates to which a kind of array substrate, has an opening portion.Flatness layer is only exposed to technique ring from this opening portion
In border, suitable aqueous vapor can enter flatness layer during technique, to promote the electrical of semiconductor element in array substrate.
According to the one side of the disclosure, a kind of array substrate is proposed.Array substrate has a viewing area and a circuit region.Battle array
Row substrate includes a metal layer, a flatness layer, one first protective layer and a conductive layer.Flatness layer is located on metal layer.First
Protective layer is located on flatness layer, and there is the first protective layer an opening portion, opening portion to be located in viewing area, and opening portion exposing is flat
Layer and do not expose metal layer.Conductive layer is located on the first protective layer and inserts in opening portion, to cover the flat of opening portion exposing
Layer.
More preferably understand in order to which the above-mentioned and other aspect to the disclosure has, special embodiment below, and coordinates appended attached
Detailed description are as follows for figure：
Description of the drawings
Fig. 1 is the top view of the display panel of one embodiment of the disclosure.
Fig. 2A and Fig. 2 B are the sectional views for the array substrate tested before.
Fig. 3 A and Fig. 3 B are painted the electrical testing curve graph of the active member of Fig. 2A and Fig. 2 B respectively.Fig. 4 is that edge is cut in Fig. 1
The sectional view of line 4-4 '.
Fig. 5 A are the top views of the array substrate of one embodiment of the disclosure.Fig. 5 B are the tangentially section views of 5B-5B ' in Fig. 5 A
Figure.
Fig. 6 A are the top views of the array substrate of another embodiment of the disclosure.Fig. 6 B are that tangentially 6B-6B ' is cutd open in Fig. 6 A
View.
Wherein, the reference numerals are as follows：
1：Display panel
10,20,30,40,50：Array substrate
100：Substrate
110：Grid
111,SLn,SLn+1：Scan line
112,CH1,CH2：Channel layer
113,DLn,DLn+1：Data line
114：Source electrode
116,D1：Drain electrode
120,220,320,420,520：Flatness layer
122,222,322,422,522：Contact window
130,230,330,430,530：First protective layer
132,232,332,432：Central opening
134,234,334：Opening portion
140：Conductive layer
150,250,350：Second protective layer
240,342,440,540,PE：Pixel electrode
260：Reflecting layer
341：Share electricity
532：Offset opening
GI：Gate insulation layer
M1：First metal material layer
M2：Second metal material layer
P：Sub-pixel structure
PA：Pel array
R1：Viewing area
R2：Periphery circuit region
R3：Drive circuit area
RF：Reflector space
T,T1,T2：Active member
TR：Penetration region
Specific implementation mode
This disclosure relates to a kind of array substrates.In some embodiments, one first protective layer is located on a flatness layer,
Flatness layer is located on a metal layer.There is first protective layer an opening portion, opening portion to be located in the viewing area of array substrate, and this
Opening portion is through the first protective layer and until extending up to flatness layer.Then, re-form a conductive layer on the first protective layer simultaneously
Opening portion is filled up, to cover the flatness layer exposed from opening portion.Thereby, before forming conductive layer, suitable aqueous vapor can be through
It is diffused into flatness layer by opening portion；And after conductive layer formation, excessive aqueous vapor can be stopped by conductive layer, avoid further
It diffuses into flatness layer.It has been found that by way of controlling appropriate aqueous vapor and entering flatness layer, can be promoted half in array substrate
Conductor element it is electrical.
Various embodiments set forth below are described in detail, the disclosure not show all possible embodiment, not in
Other state sample implementations that the disclosure proposes can also be applied.Furthermore the dimension scale on attached drawing is not according to the ratios such as actual product
Example is drawn.Therefore, specification and diagramatic content are only described herein embodiment and are used, rather than as limit disclosure protection domain it
With.In addition, the attached drawing clipped element in embodiment, to clearly show that the technical characterstic of the disclosure.It is with identical/class below
As identical/similar element or step of symbolic indication explain.
Fig. 1 is please referred to, is the top view of the display panel 1 of one embodiment of the disclosure.Display panel 1 includes array substrate
10.Array substrate 10 has viewing area R1 and circuit region, and circuit region includes periphery circuit region R2 and drive circuit area R3.Array base
Plate 10 includes pel array PA, and pel array PA is located in the R1 of viewing area.Pel array PA includes several sub-pixel structure P, number
Data line DLn, DLn+1 ... and several scan lines SLn, SLn+1 ....It include an active element in each sub-pixel structure P
A part T and pixel electrode PE, and active member T is electrically connected at corresponding data line (such as DLn) and corresponding scan line
(such as SLn).
Include multiple semiconductor elements in array substrate 1, such as in pel array PA, that is, contains multiple active members
T.When manufacturing array substrate 1, need to often be under a variety of different process environments.Certain semiconductor elements in array substrate 1
It is especially extremely sensitive to aqueous vapor, once full of excessive aqueous vapor in process environments, then these semiconductor elements may be generated to electricity
The adverse effect of property.
Fig. 2A and Fig. 2 B are the sectional views for the array substrate 40,50 tested before.Fig. 3 A and Fig. 3 B be painted respectively Fig. 2A and
The electrical testing curve graph of active member T1, T2 of Fig. 2 B.
Fig. 2A and Fig. 2 B are please referred to, array substrate 40 includes active member T1, flatness layer 420, the first protective layer 430 and picture
Plain electrode 440, array substrate 50 include active member T2, flatness layer 520, the first protective layer 530 and pixel electrode 540.
In this example, active member T1 and active member T2 is oxide semiconductor-type transistor, the crystal of this type
Pipe is often applied in viewing area.Since oxide semiconductor-type transistor has low leakage current, when be used in frame updating frequency
Under the low operation of rate, the power consumption of display panel can be saved.However, oxide semiconductor-type transistor is easily influenced by aqueous vapor,
Once diffusion of moisture will so that channel layer CH1, CH2's is electrical to channel layer CH1, CH2 for being made of oxide semiconductor material
Characteristic changing.
In fig. 2, there is the first protective layer 430 central opening 432, central opening 432 to be formed in contact window
422 center electrically connects so that pixel electrode 440 can extend in contact window 422 and central opening 432 with drain D 1
It connects.Here, the first protective layer 430 has the effect of blocking water, and by the configuration of central opening 432, not yet forming pixel electricity
Before pole 440, the aqueous vapor in process environments just can not be diffused to via flatness layer 420 in channel layer CH1.However, such as Fig. 3 A institutes
Show, if in blocking diffusion of moisture to channel layer CH1, grid bias V can be caused insteadGIt is deviated toward positive value direction.
In fig. 2b, there is the first protective layer 530 an offset opening 532, offset opening 532 to deviate from contact window
522 centre also partly overlaps that is, offseting mouth 532 with contact window 522, therefore flatness layer 520 can be open from offset
532 expose.By deviating the configuration of opening 532, before not yet forming pixel electrode 540, the part aqueous vapor in process environments
It will be diffused in channel layer CH2 via flatness layer 520.As shown in Figure 3B, the electrical stability of active member T2 is changed instead
It is kind.In other words, if suitable diffusion of moisture can be made to the channel layer of oxide semiconductor-type transistor, contribute to instead electrically
Promotion.
However, in the setting of Fig. 2 B, it is necessary to accurately control offset opening 532 and deviate from the center of contact window 522
The offset of centre, also that is, the photomask formed used in such offset opening 532 allows for accurate contraposition.If offset is too
It is more, cause excessive diffusion of moisture to channel layer CH2, grid bias V can be made insteadGIt is deviated toward negative value direction.If offset
Very little, then diffusing to the aqueous vapor of channel layer CH2 will be not enough to make up grid bias VGThe problem of toward positively biased.
In view of this, applicant propose it is a kind of independently of above-mentioned central opening 432 or offset opening 532 another opening
Portion allows aqueous vapor that can enter flatness layer during technique, in this way, diffusion of moisture can be efficiently controlled to the amount of channel layer.Also, shape
Can not be interfered by the landform of flatness layer at such opening portion, also can not by causing offset excessive because photomask misplaces or
Very few influence.
Fig. 4 is please referred to, is the tangentially sectional view of 4-4 ' in Fig. 1.Active member T is formed in substrate 100.Active element
Part T includes grid 110, channel layer 112, source electrode 114 and drain electrode 116.Grid 110 between substrate 100 and channel layer 112,
And gate insulation layer GI is more configured between grid 110 and channel layer 112, it is directly connected to avoid the two.Furthermore source electrode 114 and leakage
Pole 116 is all electrically connected at channel layer 112.The structure design of above-mentioned active member T be illustrate by taking bottom-gate type configuration as an example, but
It is not limited to the disclosure.
Grid 110, source electrode 114 and the material of drain electrode 116 can be conductive materials, e.g. various metals, conductive metal
Oxide, organic conductive material etc..Channel layer 112 is, for example, oxide semiconductor layer, and material includes selected from by indium oxide
Zinc (Indium Zinc Oxide, IZO), indium tin zinc oxide (Indium-Tin-Zinc Oxide, ITZO), indium gallium
(Indium Gallium Oxide, IGO), indium gallium zinc (Indium Gallium Zinc Oxide, IGZO), indium oxide
Tungsten (Indium tungsten Oxide, IWO), zinc oxide (ZnO), tin oxide (SnO), gallium oxide zinc (Gallium-Zinc
Oxide, GZO), zinc-tin oxide (Zinc-Tin Oxide, ZTO) and tin indium oxide (Indium-Tin Oxide, ITO) formed
At least one of group material.
Grid 110, channel layer 112, source electrode 114 and the production method of drain electrode 116 include film deposition step (such as chemical gas
Mutually deposition, physical vapour deposition (PVD), film coated etc.), patterning step (such as photolithographic etching step, laser-induced thermal etching step or shells
Except step etc.) or above-mentioned steps combination.For example, grid 110 can be by one first metal material layer M1 via photolithographic etching step
And pattern and formed, source electrode 114 can pattern shape by one second metal material layer M2 with drain electrode 116 via photolithographic etching step
At.
Then, in forming flatness layer 120 in substrate 100, to cover active member T.Flatness layer 120 has contact window
122, contact window 122 exposes the drain electrode 116 of a part.
After forming contact window 122, then, the first protective layer 130 is formed on flatness layer 120, wherein the first protection
Layer 130 is more covered in the side wall of contact window 122.First protective layer 130 has central opening 132, the formation of central opening 132
In the center of contact window 122, local drain electrode 116 is made to be exposed from central opening 132.In addition, the first protective layer 130 is more
With opening portion 134, opening portion 134 exposes the local area of flatness layer 120, but does not expose remaining film layer, such as grid
110, channel layer 112, source electrode 114 and drain electrode 116.In other words, opening portion 134 through the first protective layer 130 and extends up to put down
Until smooth layer 120.
The material of flatness layer 120 may include organic material, be easy to absorb aqueous vapor.The material of first protective layer 130 can wrap
Include inorganic material, e.g. silicon nitride (SiNx).Silicon nitride is the material of densification, therefore the first protective layer 130 has the energy to block water
Power.Here, flatness layer 120 is only exposed to from opening portion 134 in process environments, the aqueous vapor in process environments can opening
134 enter flatness layer 120.Suitable aqueous vapor can spread to channel layer 112 as a result, thus can help to the electrical of active member T
Promotion.
In some embodiments, size≤10 micron (μm) of opening portion 134, the size of opening portion 134 are, for example, to be open
Length, width or the diameter in portion 134 etc..In some embodiments, total face of the area of opening portion 134 and the first protective layer 130
Long-pending ratio≤10%, e.g. 0.01%~10%.In this way, suitable diffusion of moisture can be further ensured that channel layer
112。
Then, form pixel electrode PE on the first protective layer 130, and pixel electrode PE by contact window 122 and
Central opening 132 and with drain electrode 116 be electrically connected.In addition, a conductive layer 140 can be formed on the first protective layer 130 and insert
In opening portion 134, to cover the flatness layer 120 exposed opening portion 134.
Here, aqueous vapor penetrance≤10 of the material of conductive layer 140-1g/m2R for 24 hours, it is further to avoid excessive aqueous vapor
Into in flatness layer 120.In some embodiments, the material of conductive layer 140 can be metal, it is opaque conductive material, transparent
Conductive material etc..Transparent conductive material can be the mixing of the oxide of the element of the race of the 2nd, 3 and 4 in the periodic table of chemical element
Object, e.g. tin indium oxide (Indium-Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), oxidation
Aluminium zinc (Aluminum-doped Zinc Oxide, AZO), indium gallium (Indium Gallium Oxide, IGO), indium oxide
Gallium zinc (Indium Gallium Zinc Oxide, IGZO), indium tin zinc oxide (Indium-Tin-Zinc Oxide, ITZO),
The materials such as indium gallium tin (Indium Gallium Tin Oxide, IGTO).In some embodiments, conductive layer 140 and picture
Plain electrode PE is formed by same film pattern.In some embodiments, conductive layer 140 is pixel electrode PE.
In addition, array substrate 10 can further include the second protective layer 150, it is located on gate insulation layer GI, and be covered in raceway groove
Layer 112.The material of second protective layer 150 may include inorganic material, e.g. silica (SiOx), silicon oxynitride (SiOxNy) etc.
Material.Second protective layer 150 has the ability of stop portions aqueous vapor, and can be used as oxygenating and be used, and thereby promotes active member T's
Electrically.
Fig. 5 A are the top views of the array substrate 20 of one embodiment of the disclosure.Fig. 5 B are that tangentially 5B-5B ' is cutd open in Fig. 5 A
View.In the present embodiment, array substrate 20 can be applied in semi-penetrated semi-reflected liquid crystal display (TR LCD).
The array substrate 20 of Fig. 5 A and Fig. 5 B can have opening portion 234, effect to be similar to the opening portion 134 described in Fig. 4.
As fig. 5 a and fig. 5b, pel array PA (being shown in Fig. 1) may include penetration region TR and reflector space RF.Scan line 111
And grid 110 can be patterned by the first metal material layer M1 and be formed.Data line 113, source electrode 114 can be by the second gold medals with drain electrode 116
Belong to material layer M2 to pattern to be formed.
In the present embodiment, the material of flatness layer 220, the first protective layer 230, pixel electrode 240, the second protective layer 250
It can be similar to flatness layer 120, the first protective layer 130, pixel electrode PE, the second protective layer 150 of Fig. 4.
After forming active member T, the second protective layer 250 can be formed on active member T and gate insulation layer GI.Then,
Flatness layer 220 is formed on the second protective layer 250, and the thickness of the flatness layer 220 in reflector space RF is more than penetration region
The thickness of flatness layer 220 in TR.It, can be anti-also, in order to promote the display effect of semi-penetrated semi-reflected liquid crystal display
The local surfaces for the flatness layer 220 penetrated in the RF of region form several raised designs.In addition, flatness layer 220 has contact window
222, contact window 222 is located in reflector space RF, and contact window 222 exposes the local surfaces of the second protective layer 250.
Then, the first protective layer 230 is formed on flatness layer 220, is opened wherein the first protective layer 230 is more covered in contact hole
The side wall of mouth 222.Then, the centre using a photomask in contact window 222 forms central opening 232, makes local
Drain electrode 116 is exposed from central opening 232.Meanwhile opening portion 234 is formed in penetration region TR.Opening portion 234 exposes flat
The local area of smooth layer 220, but do not expose remaining film layer.
Here, flatness layer 220 is only exposed to from opening portion 234 in process environments, the aqueous vapor in process environments can pass through
Opening portion 234 enters flatness layer 220.Suitable aqueous vapor can spread to channel layer 112 as a result, thus can help to active member T
Electrical promotion.
Then, pixel electrode 240 is formed on the first protective layer 230, and pixel electrode 240 passes through contact window 222
And central opening 232 and with drain electrode 116 be electrically connected.Also, pixel electrode 240 is more inserted in opening portion 234, to cover opening
The flatness layer 220 that portion 234 is exposed.
Then, in forming reflecting layer 260 on pixel electrode 240 in reflector space RF, reflecting layer 260 is opened positioned at contact hole
In mouth 222 and central opening 232, and on several raised designs of flatness layer 220.Reflecting layer 260 can reflect the external world as a result,
Ambient light, and promote the optical uniformity at each visual angle.
Fig. 6 A are the top views of the array substrate 30 of another embodiment of the disclosure.Fig. 6 B are tangentially 6B-6B ' in Fig. 6 A
Sectional view.
The array substrate 30 of Fig. 6 A and Fig. 6 B can have opening portion 334, effect to be similar to the opening portion 134 described in Fig. 4.
As shown in Figure 6 A and 6 B, scan line 111 and grid 110 can be patterned by the first metal material layer M1 forms.Data line 113,
Source electrode 114 can be patterned by the second metal material layer M2 with drain electrode 116 and be formed.
In the present embodiment, the material of flatness layer 320, the first protective layer 330, pixel electrode 342, the second protective layer 350
It can be similar to flatness layer 120, the first protective layer 130, pixel electrode PE, the second protective layer 150 of Fig. 4.
After forming active member T, the second protective layer 350 can be formed on active member T and gate insulation layer GI.Then,
Flatness layer 320 is formed on the second protective layer 350.Flatness layer 320 has contact window 322, and contact window 322 exposes
The local surfaces of second protective layer 350.
Then, the first protective layer 330 is formed on flatness layer 320, is opened wherein the first protective layer 330 is more covered in contact hole
The side wall of mouth 322.Then, the centre using a photomask in contact window 322 forms central opening 332, makes local
Drain electrode 116 is exposed from central opening 332.Meanwhile more forming opening portion 334.Opening portion 334 exposes the office of flatness layer 320
Portion's area, but do not expose remaining film layer.
Here, flatness layer 320 is only exposed to from opening portion 334 in process environments, the aqueous vapor in process environments can be by opening
Oral area 334 enters flatness layer 320.Suitable aqueous vapor can spread to channel layer 112 as a result, thus can help to active member T's
Electrical promotion.
Then, pixel electrode 342 is formed on the first protective layer 330, and pixel electrode 342 passes through contact window 322
And central opening 332 and with drain electrode 116 be electrically connected.Also, pixel electrode 342 is more inserted in opening portion 334, to cover opening
The flatness layer 320 that portion 334 is exposed.
In the present embodiment, pel array PA (being shown in Fig. 1) can further include a common electrode 341, common electrode 341
Between flatness layer 320 and the first protective layer 330.Here, common electrode 341, the first protective layer 330 and pixel electrode 342 can
Together constitute with storage capacitors.
In addition, in the present embodiment, opening portion 334 can be at least partly Chong Die with data line 113, and then avoids each sub-pixel
Aperture opening ratio loss.
The array substrate that the various embodiments described above are provided has another opening portion independently of central opening.Flatness layer is only
It is exposed in process environments from this opening portion, therefore, aqueous vapor can enter flatness layer during technique, to be promoted in array substrate
Semiconductor element it is electrical.
In conclusion although the disclosure is disclosed as above with embodiment, so it is not limited to the disclosure.Disclosure sheet
Field those of ordinary skill is not departing from spirit and scope of the present disclosure, when can be used for a variety of modifications and variations.Therefore, originally
Disclosed protection domain is when subject to appended claims institute defender.
Claims (11)
1. a kind of array substrate, with a viewing area and a circuit region, which includes：
One metal layer；
One flatness layer is located on the metal layer；
One first protective layer is located on the flatness layer, which has an opening portion, which is located at the viewing area
It is interior, and the opening portion exposes the flatness layer and does not expose the metal layer；And
One conductive layer on first protective layer and is inserted in the opening portion, to cover the flatness layer of opening portion exposing.
2. the material of array substrate as described in claim 1, the wherein flatness layer includes organic material, first protective layer
Material includes inorganic material.
3. array substrate as described in claim 1, wherein aqueous vapor penetrance≤10 of the conductive layer-1g/m2-24hr。
4. array substrate as described in claim 1, further includes：
One pel array is located in the viewing area, and wherein the pel array includes：
One data line and scan line；
One active member, is electrically connected the data line and the scan line, which includes a grid, monoxide semiconductor
Layer, a source electrode and a drain electrode, the oxide semiconductor layer are located on the grid, and the source electrode and the drain electrode are electrically connected at the oxygen
Compound semiconductor layer；And
One pixel electrode is located on first protective layer；
Wherein there is the flatness layer contact window, first protective layer to cover the side wall of the contact window, pixel electricity
Pole is electrically connected by the contact window and the drain electrode.
5. array substrate as claimed in claim 4, the wherein conductive layer are the pixel electrode.
6. array substrate as claimed in claim 4, further includes one second protective layer, which covers the oxide half
Conductor layer.
7. array substrate as claimed in claim 4, the wherein pel array include a penetration region and a reflector space, this is opened
Oral area is located in the penetration region, which is located in the reflector space.
8. array substrate as claimed in claim 4, which further includes a common electrode, and the common electrode is flat positioned at this
Between smooth layer and first protective layer.
9. array substrate as claimed in claim 4, the wherein metal layer are formed, the metal by a metal material pattern layers
Layer includes the data line, the source electrode and the drain electrode.
10. array substrate as claimed in claim 9, the wherein opening portion at least partly with the data line overlap.
11. the ratio of array substrate as described in claim 1, the wherein area of the opening portion and the gross area of first protective layer
Example≤10%.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107113866A TWI655768B (en) | 2018-04-24 | 2018-04-24 | Array substrate |
| TW107113866 | 2018-04-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108803176A true CN108803176A (en) | 2018-11-13 |
| CN108803176B CN108803176B (en) | 2021-04-20 |
Family
ID=64076865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810784035.7A Active CN108803176B (en) | 2018-04-24 | 2018-07-17 | Array substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108803176B (en) |
| TW (1) | TWI655768B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110828476A (en) * | 2019-10-16 | 2020-02-21 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI819508B (en) * | 2022-03-04 | 2023-10-21 | 友達光電股份有限公司 | Transflective liquid crystal panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020012083A1 (en) * | 2000-07-28 | 2002-01-31 | Jun Tanaka | Color liquid crystal panel and color liquid crystal display apparatus |
| CN103123911A (en) * | 2012-10-23 | 2013-05-29 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN105470197A (en) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | Production method of low temperature poly silicon array substrate |
| CN106057824A (en) * | 2016-08-03 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN108780617A (en) * | 2016-03-18 | 2018-11-09 | 株式会社半导体能源研究所 | Display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483151B (en) * | 2008-01-10 | 2013-05-22 | 统宝光电股份有限公司 | Organic light emitting apparatus and forming method thereof |
| TWI462635B (en) * | 2011-12-22 | 2014-11-21 | Au Optronics Corp | Organic electroluminescence device |
| DE112013003609B4 (en) * | 2012-07-20 | 2017-04-27 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device that includes the display device |
| CN106531768A (en) * | 2016-12-07 | 2017-03-22 | 厦门天马微电子有限公司 | Organic electroluminescence display panel and preparation method thereof |
-
2018
- 2018-04-24 TW TW107113866A patent/TWI655768B/en active
- 2018-07-17 CN CN201810784035.7A patent/CN108803176B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020012083A1 (en) * | 2000-07-28 | 2002-01-31 | Jun Tanaka | Color liquid crystal panel and color liquid crystal display apparatus |
| CN103123911A (en) * | 2012-10-23 | 2013-05-29 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN105470197A (en) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | Production method of low temperature poly silicon array substrate |
| CN108780617A (en) * | 2016-03-18 | 2018-11-09 | 株式会社半导体能源研究所 | Display device |
| CN106057824A (en) * | 2016-08-03 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110828476A (en) * | 2019-10-16 | 2020-02-21 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display device |
| CN110828476B (en) * | 2019-10-16 | 2022-04-05 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI655768B (en) | 2019-04-01 |
| TW201946266A (en) | 2019-12-01 |
| CN108803176B (en) | 2021-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9543443B2 (en) | Thin film transistor assembly, array substrate method of manufacturing the same, and display device | |
| WO2016173027A1 (en) | Thin film transistor array substrate and manufacturing method therefor | |
| JP2019511831A (en) | TFT array substrate, method of manufacturing the same, display device | |
| KR20170124151A (en) | Transistor array panel and manufacturing method thereof | |
| US9214476B1 (en) | Pixel structure | |
| CN109166889B (en) | Display substrate, manufacturing method thereof and display device | |
| WO2016192446A1 (en) | Thin film transistor and manufacturing method thereof, and array substrate and manufacturing method thereof | |
| CN103794633B (en) | A kind of array base palte and preparation method thereof, display device | |
| TWI555183B (en) | Thin film transistor and pixel structure | |
| US10971525B1 (en) | TFT array substrate and manufacturing method thereof | |
| CN108447822A (en) | The production method of LTPS TFT substrates | |
| CN105870057A (en) | Array substrate and manufacturing method thereof and display device | |
| WO2016173012A1 (en) | Film transistor array substrate and method for fabricating same | |
| US20210408063A1 (en) | Array substrate and method of manufacturing same | |
| WO2022213420A1 (en) | Array substrate and preparation method therefor, and oled display panel | |
| CN108803176A (en) | Array substrate | |
| JP6440228B2 (en) | Method for manufacturing thin film transistor substrate | |
| JP2023531839A (en) | Organic light-emitting display substrate, manufacturing method thereof, and organic light-emitting display device | |
| EP3754637A1 (en) | Pixel unit, manufacturing method thereof, and array substrate | |
| CN106057825A (en) | Array substrate of OLED display device and manufacture method of array substrate | |
| US9437661B2 (en) | Thin film transistor substrate, display device having the same and method of manufacturing the same | |
| CN203707135U (en) | Array substrate and display device | |
| US10516059B1 (en) | Lower temperature polycrystalline silicon thin film transistor and method of manufacture thereof and OLED display device | |
| CN106252277B (en) | Low-temperature polycrystalline silicon thin film transistor array substrate, manufacturing method and display device | |
| CN109920829A (en) | OLED backboard and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |