CN108781060B

CN108781060B - Voltage sampling driver with enhanced high frequency gain

Info

Publication number: CN108781060B
Application number: CN201780007969.3A
Authority: CN
Inventors: 阿明·塔亚丽
Original assignee: Kandou Labs SA
Current assignee: Kandou Labs SA
Priority date: 2016-01-25
Filing date: 2017-01-25
Publication date: 2023-04-14
Anticipated expiration: 2037-01-25
Also published as: EP3408935A1; US20200106412A1; EP3408935B1; EP3408935A4; US11183982B2; WO2017132292A1; US10498305B2; US20180302053A1; US20170214374A1; CN108781060A; US10003315B2

Abstract

Methods and systems are described for: receiving a set of input signals by an input differential branch pair and generating a first differential current in response; receiving an offset voltage control signal at an input of the offset voltage branch pair and responsively generating a second differential current; supplementing a high frequency component of the second differential current by injecting the high pass filtered set of input signals into the input terminals of the offset voltage branch pair with a high pass filter; and generating an output differential current from the first and second differential currents by an amplification stage connected to the input differential leg pair and the offset voltage leg pair.

Description

Voltage sampling driver with enhanced high frequency gain

Cross Reference to Related Applications

This application claims priority from U.S. provisional patent application No. 62/286,717, filed 2016, 25/1, to arnin Tajalli, entitled "voltage sampling driver with enhanced high frequency gain," the contents of which are hereby incorporated by reference in their entirety for all purposes.

The following references are incorporated by reference herein in their entirety for all purposes:

U.S. patent application with publication number 2011/0268225, application number 12/784,414, application date 2010, 20/5, entitled "orthogonal differential vector signaling" entitled Cronie 1, issued to Harm Cronie and Amin Shokrollahi;

U.S. patent application publication No. 2011/0302478, application No. 12/982,777, application date 30/12/2010, to Harm Cronie and Amin Shokrollahi, entitled "inter-chip communication with high pin utilization and high power utilization with common-mode noise and synchronous switch output noise resistance" (hereinafter "Cronie 2");

the invention relates to a communication system, which is applied for 13/030,027, has an application date of 2011, 2, and 17, and is named as Harm Cronie, amin Shokrollahi and Armin Tajalli, and is named as U.S. patent application of a method and a system for carrying out anti-noise interference, high pin utilization rate and low power consumption communication by using sparse signaling codes, and is called as Cronie 3 below;

U.S. patent application Ser. No. 13/463,742, filed 2012, 5/3, entitled "finite State encoder and decoder for vector Signaling codes," U.S. patent application Ser. No. < Cronine 4 >;

U.S. patent application No. 13/842, 740, filed 2013, 3, 15, entitled "bias tolerant method in vector signaling codes for interchip communication and advanced detector for vector signaling codes for interchip communication", entitled "Holden 1", entitled "united states patent application No. Brian Holden, amin Shokrollahi and ant Singh;

U.S. patent application Ser. No. 13/603,107, filed 2012, 9/9, entitled "method and System for selecting vector Signaling code union for high Pin utilization and high Power utilization inter-chip communication," Brian Holden and Amin Shokrollahi, U.S. patent application Ser. No. (hereinafter "Holden 2");

U.S. patent application Ser. No. 13/671,426 filed 2012, 11/7/2012, entitled "Cross-connect decoder for vector signaling codes" by the inventors of Brian Holden and Amin Shokrollahi (hereinafter "Holden 3").

U.S. provisional patent application with application number 61/839,360, application date 2013, 6/23, entitled Amin Shokrollahi, entitled "low receiver complexity vector signaling," hereinafter referred to as Shokrollahi 1;

the U.S. provisional patent application with application number 61/839,360, application date of 2013, 23/6, inventor of Amin Shokrollahi, entitled "low receiver complexity vector signaling", is hereinafter referred to as Shokrollahi 2;

U.S. provisional patent application No. 61/946,574 filed on 2014, 28/2, brian Holden, and Richard Simpson, entitled "vector signaling code with embedded clock", hereinafter "Shokrollahi 3";

U.S. patent application Ser. No. 13/895,206 filed on 2013, 5, 15, and entitled "Circuit for efficiently detecting inter-chip communication vector signaling codes Using Difference" to Roger Ulrich and Peter Hunt, U.S. patent application Ser. No. < Ulrich 1 >;

in addition, the following prior art references are also cited in the present application:

behzad Razavi, "StrongARM latch," journal of IEEE solid-state circuits, journal of autumn and spring 2015, pages 12-17, DOI 10.1109/MSSC2015.2418155, hereinafter called Razavi;

"double-tail current latch type voltage sensitive amplifier with total establishing and maintaining time of 18 picoseconds", simulation technique and phase-locked loop, 2.13.2.2007, pages 314-315 and 605, which are called "Schinkel" below.

Background

In a communication system, information may be transferred from one physical location to another. In general, it is desirable that the transmission of such information be reliable, fast, and consume minimal resources. A serial communication link is a common information transmission medium and may be based on a single wired circuit having a ground or other common reference as the object of comparison, a plurality of such wired circuits having a ground or other common reference as the object of comparison, or a plurality of circuits with each other as the object of comparison. A common example of the latter scenario is Differential Signaling (DS). The operating principle of differential signaling is that one signal is sent in one line and the opposite of the signal is sent in the paired line; the signal information is represented by the difference between the two lines, rather than its absolute value relative to ground or other fixed reference value.

Differential signaling can cancel crosstalk and other common mode noise compared to single-ended signaling (SES), thereby enhancing the recovery of the original signal at the receiving end. Another advantage of this technique is that the Synchronous Switching Noise (SSN) transients generated by both signals are almost zero. As such, when both outputs have the same load, their transmission requirements on the power supply remain unchanged regardless of the data being transmitted. In addition, in this case, any induced currents generated by the differential line termination of the receiving end cancel each other out, thereby minimizing induced noise introduced in the receiving system.

There are a number of signaling methods that can increase pin utilization while maintaining the same beneficial characteristics as compared to differential signaling. Many such methods operate on more than two lines simultaneously, each using a binary signal, but mapping the information in the form of packetized bits.

Vector signaling is a signaling method. By vector signaling, the multiple signals in the multiple lines can be viewed as a whole while maintaining the independence of each signal. Each signal in the ensemble of signals is referred to as a vector component, and the number of lines is referred to as the "dimension" of the vector. In some embodiments, as with the paired lines of differential signaling, the signal in one line is completely dependent on the signal in the other line. Thus, in some cases, the above-described vector dimension may refer to the number of degrees of freedom of the signal in the plurality of lines, rather than the number of the plurality of lines.

In binary vector signaling, each component has a coordinate value (or simply "coordinate") that is one of two possible values. For example, 8 single-ended signaling lines can be considered as a whole, where each component/line takes one of two values in a signal cycle. Then a "codeword" of the binary vector signaling corresponds to one of the possible states of the entire component/line group. For a given vector signaling coding scheme, the set of valid, desirable codewords is referred to as a "vector signaling code" or "vector signaling vector set". A "binary vector signaling code" is a mapping method and/or a set of rules for mapping information bits to binary vectors.

In non-binary vector signaling, each component takes the value of a coordinate value selected from a set of more than two possible coordinate values. A "non-binary vector signaling code" refers to a mapping scheme and/or a set of rules for mapping information bits to non-binary vectors.

Examples of vector signaling codes are found in Cronie 1, cronie 2, cronie 3 and Cronie 4.

While non-binary vector signaling approaches may provide substantial improvements in the tradeoff between pin utilization, power utilization, and noise immunity over traditional signaling approaches, other improvements may still be made in some applications.

Disclosure of Invention

A method and system of an apparatus including a voltage sampling driver to generate an output differential current from at least a first differential current and a second differential current is described herein. The voltage sampling driver includes: an input differential branch pair for receiving a set of input signals, each branch of the input differential branch pair comprising one or more transistors for generating the first differential current; and an offset voltage branch pair for receiving an offset voltage control signal at an input, each branch of the offset voltage branch pair comprising one or more transistors for generating the second differential current. The device further comprises: an amplification stage connected to the voltage sampling driver for generating a differential output voltage from the output differential current; and a high-pass filter for injecting the set of input signals after high-pass filtering into the input ends of the offset voltage branch pairs to supplement the high-frequency component of the second differential current.

In some embodiments, the voltage sampling driver further comprises respective tail current sources for periodically activating the input differential finger pair and offset voltage finger pair. In some embodiments, the respective tail current sources are periodically enabled according to an input clock signal. In some embodiments, the current magnitudes of the respective tail current sources are independently adjustable.

In some embodiments, the amplification stage comprises a pair of load resistors for generating a differential output voltage from the extracted differential current.

In some embodiments, the amplification stage comprises an active device. In some embodiments, the active device is a MOS device. In some embodiments, the MOS devices are periodically enabled to implement a discrete time-domain integrator.

In some embodiments, the set of input signals corresponds to code character numbers of an orthogonal differential vector signaling code (ODVS). In some embodiments, the set of input signals correspond to codeword symbols of a Phase Modulation (PM) code.

In some embodiments, the first branch of the input differential branch pair includes at least two transistors connected in parallel. In some embodiments, the first branch of the offset voltage branch pair includes a plurality of transistors identical to a plurality of transistors within the first branch of the input differential branch pair.

In some embodiments, each branch of the input differential branch pair and each branch of the offset correction branch pair includes a single transistor. In some embodiments, each transistor in the input differential finger pair and the offset voltage finger pair has a weight value associated with a transistor characteristic. In some embodiments, each weight value is determined by a respective value of a row of the orthogonal matrix.

In some embodiments, the input differential branch pair includes a frequency selective impedance connected at a common node connecting a pair of branches within the input differential branch pair. In some embodiments, the frequency selective impedance comprises a resistor-capacitor network.

In some embodiments, the apparatus further comprises a multiple-input comparator (MIC) for providing the set of input signals as differential input signals. In some embodiments, the differential input signal represents a combination of symbols of a codeword.

In some embodiments, the amplification stage comprises an integrator circuit for generating a differential output voltage from the differential current. In some embodiments, the integrator is a discrete time integrator having a periodically activated load device. In some embodiments, the single line of differential output voltage represents a single ended output. In some embodiments, the amplifier is a voltage mode amplifier.

In some embodiments, the apparatus further comprises a comparator for generating a single ended output by dividing the differential output voltage.

In some embodiments, the offset voltage control signal user eliminates offset errors introduced by components of the voltage sampling driver and/or the amplification stage. In some embodiments, the voltage sampling driver comprises an NMOS transistor. In some embodiments, the voltage sampling driver comprises a PMOS transistor.

In some embodiments, the offset voltage control signal represents an arbitrary reference voltage.

In some embodiments, the amplification stage comprises a pair of load resistors for generating the differential output voltage from the output differential current. In some embodiments, the amplification stage further comprises a pair of capacitors, wherein each capacitor is connected between one end of a respective load resistor and ground. In some embodiments, the pair of load resistors is adjustable. In some embodiments, the amplification stage further comprises an adjustable tail current source.

In some embodiments, the product of the current magnitude of the adjustable tail current source and the magnitude of the impedance of one of the pair of load resistors is a constant value, and the pair of load resistors and the pair of adjustable tail current sources have bandwidth control inputs for adjusting bandwidth. In an alternative embodiment, the product of the magnitude of the current of the adjustable tail current source and the magnitude of the impedance of one of the load resistors is a non-constant value, and the pair of load resistors and the tail current source have power control inputs for adjusting power consumption.

In some embodiments, each adjustable load resistor comprises a plurality of resistors forming a parallel network, each resistor of the plurality of resistors having a respective switch connected between the resistor and a common node of the parallel network, each switch connecting or disconnecting the resistor into or from the parallel network in accordance with a respective control signal.

The summary of the invention section is a brief summary of a series of concepts described in detail in the detailed description section below. The summary of the invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Other objects and/or advantages of embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description and the accompanying drawings.

Drawings

Various embodiments consistent with the present invention are described below with reference to the accompanying drawings. In the present invention and the drawings, like numerals denote like parts and components.

Fig. 1 illustrates a communication system according to some embodiments.

Fig. 2A and 2B are schematic diagrams of a multiple-input comparator (MIC) according to some embodiments.

Fig. 3A and 3B illustrate a multiple-input comparator with and without equalization having an input weight value defined in line 3 of the matrix of equation 4, respectively, in accordance with some embodiments.

FIG. 4 is a block diagram of a transfinned receiver according to some embodiments.

Fig. 5 is a block diagram of a multiple-input comparator with adjustable bandwidth and connected to a voltage sampling driver and an amplification stage according to some embodiments.

Fig. 6 is a block diagram of another multiple-input comparator connected to a voltage sampling driver and an amplification stage according to some embodiments.

FIG. 7 is a schematic diagram of the voltage sampling driver according to some embodiments.

FIG. 8 is a schematic diagram of a multiple input voltage sampling driver according to some embodiments.

FIG. 9 is a flow diagram of a method according to some embodiments.

Fig. 10 illustrates a first configuration of a multiple input comparator/offset correction combining circuit according to some embodiments.

Fig. 11 illustrates a second configuration of a multiple input comparator/offset correction combining circuit according to some embodiments.

FIG. 12 illustrates a third configuration of a multiple input comparator/offset correction combining circuit according to some embodiments.

Fig. 13 illustrates an amplifier with adjustable bandwidth according to some embodiments.

FIG. 14 illustrates an adjustable impedance according to some embodiments.

FIG. 15 illustrates a voltage sampling driver connected to a two-tailed current latch, according to some embodiments.

Figure 16 illustrates a voltage sampling driver connected to a StrongARM latch according to some embodiments.

Fig. 17 is a schematic diagram according to some embodiments.

Fig. 18-20 show simulation results for systems with and without high frequency injection for 12mm, 24mm and 70mm channels, respectively.

Detailed Description

Fig. 1 illustrates a communication system that employs vector signaling codes in accordance with some embodiments. The source data (i.e., S shown in the figure) input to the transmitter 110 ₀ ，S ₁ ，S ₂ ，S ₃ ，S ₄ ) In the form of a source data word 100 into an encoder 112. The size of the source data word may vary with the parameters of the vector signalling code. The encoder 112 generates codewords for the vector signaling code for which the system is designed. In operation, the above-described codeword generated by encoder 112 is used to control the PMOS and NMOS transistors within driver 118 to generate two, three, or more different voltages or currents on each of the N communication lines 125 of communication channel 120 to represent the N symbols of the codeword. In the embodiment of fig. 1, the size of the source data word is shown as 5 bits, and the codeword size is 6 symbols. Therefore, the number of the first and second electrodes is increased,the communication channel 110 is shown as being comprised of 6 signal lines 125, each transmitting a codeword symbol. One familiar with the art of coding can also describe this code as: a block length of 6 (i.e. generating an output word of six symbols) and a code size of 32 (i.e. having 32 different code words, sufficient to encode 5 binary bits of data).

Within the communication receiver 130, a detector 132 reads the voltage or current in the line 125, which may involve amplification, frequency compensation, and common mode signal cancellation. In this example, the result 140 (i.e., R as shown in the figure) is received ₀ ，R ₁ ，R ₂ ，R ₃ ，R ₄ ) Provided directly by the detector 132 without the use of the optional decoder 138.

It is readily understood that different codes may have correspondingly different block sizes and codeword sizes. For convenience of description, but not by way of limitation, the system shown in the example of fig. 1 employs an orthogonal differential vector signaling code that encodes 5 binary bit values for transmission over 6 lines, a so-called 5b6w code.

Depending on the kind of the employed vector signaling code, there may be no decoder, no encoder, or neither decoder nor encoder. For example, for the 8b8w code disclosed in Cronie 2, both the encoder 112 and the decoder 138 are provided. On the other hand, for the 5b6w code in this example, since the system can directly generate the reception result 140 by the detector 132, the decoder does not need to be explicitly provided.

In order to ensure proper operation of the communication system, the operation of the communication transmitter 110 and the communication receiver 130 must be fully synchronized. In some embodiments, the synchronization is achieved by an external clock shared by the transmitter and the receiver. In other embodiments, the clock function may be combined with one or more of the data channels described above, as is well known for bi-phase encoding for serial communications or other methods described herein.

Advanced vector signaling detector

Methods of detecting symbols transmitted over a vector signalling link are described in Cronie 1, cronie 2 and Holden 2. The present invention will be described with respect to other detection methods.

As described in Holden 1, in the case of inter-chip communication using Phase Modulation (PM) coding, a detection mechanism called maximum likelihood decoding is employed. The decoder described in Holden 2 generates a result representing a sorting or ordering operation within the decoder by comparing signal values on two communication lines with a comparator.

The following Sign function (Sign (x)) may briefly represent the above-described operation of such a comparator: sign (x) = +1 when x > 0; sign (x) = -1 when x < 0; when x =0, sign (x) is uncertain, that is, when two values entering the comparator are equal or nearly equal, the output value of the comparator can be +1 or-1, and it is not known in advance which value is specifically output. Such a comparator is hereinafter referred to as a "simple comparator".

For some applications, the simple comparator described above may not be sufficient to detect the codewords of the vector signaling code. For example, when a phase modulation code composed of permutations of the vector (1, 0, -1) is combined with a phase modulation code composed of permutations of the vector (1, -1, -1), the combined code itself contains 18 codewords, and each phase modulation code forming the combined code contains a maximum of 12 codewords. In contrast, a four-bit data value requires 16 unique codewords to be represented. Therefore, although 4 bits cannot be transmitted over 4 lines when one phase modulation code is used alone, transmission with high pin utilization can be realized over 4 lines by combining two phase modulation codes. In addition, the implementation of this transmission requires efficient circuitry to detect each codeword. It can be seen that even a complete set of 6 simple comparators between each pair of lines is not sufficient to enable detection of a codeword. This is because the comparison operations performed by these comparators cannot indicate within which of the two phase modulation codes making up the union code the received code word is contained.

When it is desired to rank the transmitted values on n communication lines, the number of simple comparators required is equal to n (n-1)/2, i.e., the number of all integer pairs formed by the integers in the range of 1,2, \8230; \8230, n, before the ranking. In some cases, this number may be too large. For example, when n equals 10, the number of simple comparators needed is 45, and such a large number of needed comparators may be difficult to achieve for a given application.

For these reasons, it is desirable to design a circuit that is more efficient than the above-described circuit requiring the use of an unacceptably large number of simple comparators and that is capable of detecting codewords that are otherwise undetectable. Hereinafter, a description will be given of a circuit using an element called a multiple input comparator.

Coefficient (also called input weighting coefficient) is a ₀ ，a ₁ ，……，a _m-1 The multi-input comparator is a comparator for input vector (x) ₀ ，x ₁ ，……，x _m-1 ) A circuit for outputting the result of the following equation 1:

sign(a ₀ *x ₀ +...+a _m-1 *x _m-1 ) (formula 1)

The symbolic function in equation 1 is defined as described above. In this way, a simple comparator can be seen as a multiple input comparator with a number of inputs of 2 and coefficients of 1 and-1, i.e. a special case of a multiple input comparator.

According to at least one embodiment, each coefficient of the multiple-input comparator is an integer. FIG. 2A shows a circuit implementation of the multi-input comparator in such an embodiment, wherein the input value x ₀ ～x ₄ The coefficients of (a) are 2,4, -1, -2, -3, respectively. In this example, 12 identical input transistors 201 form an extended differential input stage of a shared current source 202, downstream of which is a differential comparison stage 205. Since all transistors 201 are identical, x will be input ₀ And x ₁ The contribution to the positive summing node 203 and the input x ₂ ，x ₃ And x ₄ The contribution to the negative summing node 204 is weighted in proportion to the number of input transistors controlled by each such input. As shown, sumResistor 206 on

nodes

203 and 204 is a passive pull-up resistor. In some embodiments, its functionality is contained within the functionality of the differential comparator 205. If the gain of the differential comparator 205 is high enough to obtain a digital result, its output represents the result of the sign function operation performed on the difference between the positive summing node 203 and the negative summing node 204. Thus, the circuit of FIG. 2A is a specific implementation of equation 1, where a positive coefficient input is applied to the transistor 201 associated with the positive summing node 203, a negative coefficient input is applied to the transistor 201 associated with the negative summing node 204, and each coefficient value is represented by the number of identical input transistors 201 for each input.

Fig. 2B shows another multiple-input comparator with identical coefficients in simplified form, where for each input the number of transistors representing the input is numerically labeled near the corresponding transistor. According to at least one embodiment, the plurality of parallel transistors for the same input may also be implemented as a single transistor having a channel width, a transmission current, or other functional characteristics in equal proportion to the plurality of parallel transistors. In another embodiment, equivalent results are generated in a dynamic manner, where each input controls the amount of charge on each capacitor to be proportional to the input weight value, which is then injected into the summing node.

A multi-input comparator with all coefficients summed to zero is called an anti-common mode multi-input comparator. It is easy to see that when the input values of the anti-common mode multiple input comparator are simultaneously increased by the same amount, no change occurs in the output.

The multiple input comparator is more affected by thermal noise than a simple comparator. When each input of the multi-input comparator is caused by additive white Gaussian noise (the mean value of the noise is 0, and the variance is sigma) ² ) When the variation occurs, the mean value of the interference degree of the additive white gaussian noise to the output of the comparator is 0, and the variance is:

for a given input (x) ₀ ，x ₁ ，x ₂ ，……，x _m-1 ) And (y) ₀ ，y ₁ ，y ₂ ，……，y _t-1 ) If it is determined that

This value is not equal to 0, the error probability of the multi-input comparator is Q _σ (a) Wherein, Q _σ (x) Is mean 0 and variance σ ² The probability that the value of the normal random variable is greater than or equal to x. In the following, we refer to α as the "sensitivity" of the multi-input comparator with respect to its input. It is noted that the sensitivity is defined as not being equal to 0, that is, if the input of the multi-input comparator is such that the α value shown in equation 3 is zero, the sensitivity of the comparator with respect to that particular input is an "indeterminate value".

A set of multiple-input comparators S is considered to "detect" the vector signaling code C when the following conditions hold: for any two codewords c and d, there is always one multi-input comparator in the set of multi-input comparators S such that their sensitivity values with respect to c and d are not both indeterminate and are not equal to each other. This means that when the codeword is used as input to the set of multiple-input comparators S, the respective outputs of all the multiple-input comparators within the set may uniquely determine the respective codeword of the vector signaling code. If the set of multiple-input comparators S can detect the vector signaling code C, the "minimum sensitivity" of the set of multiple-input comparators S with respect to C is defined as the minimum sensitivity of any comparator among the comparators therein to any code word among the code words of the vector signaling code C (as long as the sensitivity is not an indeterminate value). This minimum sensitivity concept represents the maximum amount of thermal noise that each codeword can have given the detection error probability assured. In the following, several examples of this concept will be given.

In some embodiments, rather than using a simple dual-input comparator to divide the output of the multiple-input comparator, a differential output voltage may be employed. Fig. 3A and 3B are schematic diagrams of a multiple-input comparator with and without equalization functionality, respectively, according to such embodiments. Fig. 3A shows a multiple-input comparator with equalization including frequency selective impedances connecting the sources of all transistors. In some embodiments as shown, the frequency selective impedance includes a tunable resistor and a tunable capacitor. In some embodiments, the frequency selective impedance may be used to adjust the bandwidth of the multiple input comparator. The weight values of the multi-input comparators shown in fig. 3A and 3B correspond to row 3 of the matrix shown in equation 4 below.

Receiver using multiple input comparator

On a mathematical level, the set of multi-input comparators comprising a code receiver as described above can be described in a compact way using a matrix representation, where each column of the matrix corresponds to an input vector (x) ₀ ，x ₁ ，……，x _m-1 ) I.e. the plurality of signal conductor inputs or signal line inputs carrying the vector signalling code; each row of the matrix corresponds to a vector defining a particular multi-input comparator and its output values. In this representation, the values of the matrix elements correspond to a vector of weight values or a set of scaling coefficients applied by the multi-input comparators of the respective row to the input values of the respective column.

The matrix of equation 4 represents such a set of multiple-input comparators that includes a code receiver.

In this embodiment, the 6 input lines represented by the 6 matrix columns are processed by 5 multiple input comparators represented by the 2 nd to 6 th rows of the routing matrix. For the purposes described hereinafter, the first row of the matrix is composed entirely of the value "1", thereby generating a 6 × 6 square matrix. Herein, the matrix described by equation 4 is referred to as a through-fin (glassing) receiver matrix.

In this context, when the matrix M conforms to M ^T M = D (as in formula 4)Matrix), referred to as an "orthogonal" matrix. That is, a matrix is an orthogonal matrix when the product of the matrix and its transpose is a diagonal matrix having only non-zero values on the diagonals. This definition is weaker than the usual definition, since the usual definition requires that the multiplication result is an identity matrix, i.e. all values on the diagonal are equal to 1. While the matrix M may also be normalized to meet strong common orthogonality requirements, as described below, this is neither necessary nor beneficial in practical applications.

On the functional level, the requirement of orthogonality is as follows: each row of weight vectors representing a multi-input comparator is orthogonal to all other rows and the sum of each row representing a multi-input comparator is zero (since it is orthogonal to the common mode codeword with all element values 1). This means that the outputs of the comparators are also orthogonal (and therefore independent of each other) and thus represent different communication modes, which are referred to herein as "subchannels" of a vector signaling code communication system.

Based on the above mode explanation, the first row of the above matrix can be considered to represent a common-mode communication channel in the transmission medium. Since a common-mode rejection of the receiver is desired in a practical system, the values in the first row are set to "1" to maximize the common-mode contribution of the output value of each line to the matrix row. Since all matrix rows are defined as being orthogonal to each other, the other matrix rows (i.e., the receiver outputs) may not be affected by common mode signals. An embodiment with this common mode rejection need not employ a physical comparator corresponding to the first row of its description matrix.

To avoid confusion, it is noted that in an orthogonal differential vector signaling system, all data communications, including state transitions representing signals carried in sub-channels, are codeword communications carried out in the entire channel. As described herein, holden 1, and Ulrich 1, in embodiments, input values may be associated with particular mappings of codewords, and these mappings may be associated with particular detector results, but such associations should not be confused with the partitioning, subdivision, or sub-channels of the physical communication medium itself. Likewise, the concept of orthogonal differential vector signaling subchannels is not limited by the illustrative embodiments to a particular orthogonal differential vector signaling code, transmitter embodiment, or receiver embodiment. In addition, encoders and/or decoders for maintaining internal states may also be part of certain embodiments. A subchannel may be represented by individual signals or by the state conveyed by multiple signals.

Generating orthogonal differential vector signaling codes corresponding to a receiver matrix

Orthogonal differential vector signaling codes can be formed by combining (0, a) with a generator matrix as described in Cronie 1 and Cronie 2 ₁ ，a ₂ ，……，a _n ) The input modulation vector of the form is constructed by multiplying with matrix M. In the simplest case, each a of this vector _i Are both positive or negative numbers, e.g., ± 1, representing a single value of 1 bit of transmitted information.

By understanding the matrix M as various communication modes describing the system, it can be readily seen that in multiplying the matrix with such input vectors, the zeroth mode corresponding to the common mode transmission is not affected at all, but the other modes are all affected by a of the vector _i The disturbance of (2). It will be readily appreciated by those skilled in the art that in most embodiments, the energy consumed in common mode transmission is an unnecessary waste. However, in at least one embodiment of the present invention, the non-zero amplitude of the common mode term is used to provide a non-zero bias or baseline value throughout the communication channel.

It can also be seen that each codeword of the code generated using this method represents a linear combination of orthogonal communication modes. Without imposing additional constraints (e.g., for implementation convenience purposes), the method implements a system that can communicate with N-1 different sub-channels over N lines, which is typically implemented as an N-1 bit/N line system. The set of independent codeword values used to represent each encoded value is referred to as a symbol set of the corresponding code, and the number of independent codeword values within the symbol set is referred to as a symbol set size.

As another example, table 1 shows codes generated from the matrix of equation 4 by the above method.

It will be appreciated that the symbol set of this code consists of values +1, +1/3, -1/3, -1, and thus the code is a four-element code (i.e., the symbol set is four in size). This code is hereinafter referred to as the 5b6w code or "turbo-code" and the corresponding receiving matrix shown in equation 4 is referred to as a "turbo-receiver".

FIG. 4 illustrates one embodiment of a transfinned receiver defined by a matrix of equation 4, where w ₀ ～w ₅ Representing 6 input lines, S ₀ ～S ₄ Representing 5 sub-channel outputs. In the drawing rules employed herein, each input of the multiple-input comparators 410-450 is labeled with a weight value that is defined by the rows of the matrices of equation 4 that define the respective multiple-input comparator and that represents the relative contribution of that input to the final result output. Thus,

comparators

410 and 430 can each be considered as conventional dual-input differential comparators with a positive-negative two inputs with equal weight and opposite sign;

comparators

420 and 440 each have two positive inputs and one negative input, each positive input contributing half of the total positive value and all negative values contributing from the negative input; comparator 450 has three positive inputs and three negative inputs, each positive input contributing one-third of the total positive value and each negative input contributing one-third of the total negative value. Furthermore, although the 5 sub-channels output S ₀ ～S ₄ A single line is shown, but it should be noted that in many embodiments, each sub-channel output may be a differential output.

Fig. 5 is a block diagram of an embodiment employing a bandwidth adjustable multiple-input comparator 520 according to some embodiments connected to a voltage sampling driver and amplification stage (also called sampler/equalizer) 530. This design has several advantages. First, conventionally, the required degree of equalization is achieved by adjusting the dc gain of a Continuous Time Linear Equalizer (CTLE). In the apparatus shown in fig. 5, the power consumption of the CTLE remains unchanged even in the case where the channel characteristics are good. The sampler/equalizer circuit provides a degree of freedom such that the apparatus may consume less power with good channel characteristics. In some embodiments, the equalization and power consumption may be calibrated according to channel loss. This is very challenging for conventional architectures. In conventional architectures, it may be difficult to switch to include or exclude additional levels of CTLEs based on a particular channel response. By employing independent bandwidth adjustable multiple-input comparators 520, the architecture described herein may provide adjustable power consumption and equalization directly. In architectures according to some embodiments, a bandwidth adjustable multiple input comparator 520 is employed, downstream of which the equalizer/sampler 530 described above is located. In some embodiments, adjusting the bandwidth of the CTLE or the multiple-input comparator comprises adjusting the frequency selective impedance and the magnitude of the tail current source. In some embodiments, calibrating the above-described equalization includes adjusting a bandwidth of the multiple-input comparator, wherein the equalizer/sampler stage is not involved. When the required degree of equalization is small, the bandwidth (and thus the bias current) can be reduced, thereby reducing power consumption. Furthermore, after the bandwidth of the multi-input comparator is reduced, the effective peak value of the path (multi-input comparator-equalizer/sampler) is reduced correspondingly, thereby realizing adjustable equalization degree.

Fig. 13 is a schematic diagram of an amplifier with adjustable bandwidth. As shown, the amplifier includes an adjustable load impedance 1310 (R) _L ) Load capacitor C _L And an adjustable current source I _SS . As will be readily understood by those skilled in the art, the bandwidth of the amplifier shown in fig. 13 is given by equation 5 below:

when the bandwidth of the amplifier shown in FIG. 13 is adjusted, R can be set _L ·I _SS Is kept unchanged by making R _L And I _SS Reverse change occurs (i.e. increase R) _L When, I is decreased _SS (ii) a And vice versa), bandwidth adjustment is achieved. Thus, the gain can be kept constant during the bandwidth adjustment. In such embodiments, power consumption adjustment may also be implemented. By reducing I _SS While increasing R _L The low power consumption amplifier can be realized at the expense of a certain bandwidth. FIG. 14 shows a possible adjustable R _L An exemplary schematic of (a). As shown, FIG. 14 includes a plurality of parallel resistors R ₁ ，R ₂ ，R ₃ ，……，R _n And each resistor is connected in series with a PMOSFET. In some embodiments, the resistance of each resistor may be equal, however this should not be construed as limiting the invention. In FIG. 14, the gate of each PMOS receives a signal that connects a respective resistor to a common node V _DD To the corresponding gate input. It will be readily appreciated by those skilled in the art that increasing the parallel resistance will result in a decrease in the overall resistance of the circuit. In increasing the resistance value, the corresponding control signal may be set (e.g., via a register) such that one or more resistors are connected to the common node V _DD And (5) disconnecting. In some embodiments, the resistance value of a given combination of control signals may be a known resistance value, and the control signals may be provided to the PMOS devices according to the desired load resistance and using firmware or a look-up table (LUT). In some embodiments (constant power embodiments), the same control signal may be used to reverse control the adjustable current source. It should be noted that the differential amplifier configuration described above does not set any limit to the invention, and such a configuration may also be used with a multiple input comparator (such as the multiple input comparator shown in fig. 3A and 3B, or the multiple input comparator 520 with adjustable bandwidth shown in fig. 5). Furthermore, in alternative embodiments, the adjustable load impedance 1310 does not necessarily have the structure shown in fig. 14, but may include a potentiometer or any other adjustable impedance element known to those skilled in the art. In other alternative embodiments, the load capacitor C _L May be adjusted to provide additional bandwidth adjustment functions while keeping power consumption constant. It should be noted that although in fig. 13, the described system is adjustableThe amplifier of bandwidth is a differential amplifier, but in some embodiments, the same principles can also be applied to a multiple-input comparator (such as the multiple-input comparator shown in fig. 3A and 3B) to form the bandwidth adjustable multiple-input comparator 520.

The block diagram shown in fig. 6 includes a sampler 620 comprising an amplification stage 630 and a voltage sampling driver 640. As shown, the multi-input comparator 420 receives a set of input signals w ₀ ～w ₂ . The multi-input comparator 420 provides a differential voltage +/-VIN to the voltage sampling driver 640. In some embodiments, the voltage sampling driver also enables its periodic start by receiving a clock signal. In some embodiments, voltage sampling driver 640 is used to draw a differential current through amplification stage 630. In some embodiments, amplification stage 630 includes an integrator with positive feedback. In some embodiments, the amplification stage 630 may include a two-tail current latch as shown in fig. 15. In some embodiments, amplification stage 630 may include a StrongARM latch as shown in fig. 16. The operation of the StrongARM latch is divided into three phases, as described in Razavi. In the first phase, the clock signal (CLK) is low, and the capacitances CL of the nodes Outn, outp and the capacitances of M1 and M2 are charged to VDD. In the second phase, CLK goes high and current starts to flow through transistors M1 and M2, i.e. M1 and M2 start to discharge the capacitance. The current through each transistor is proportional to the inputs INN and INP, and therefore the rate of discharge of the capacitors of M1 and M2 is also proportional to these two inputs. In the third phase, as the capacitances of M1 and M2 discharge, the cross-coupled transistors M3 and M4 turn on, and the CL of nodes Outn and Outp begin to discharge with current flowing through M3 and M4. Since one of the above CL discharges faster, either PMOS transistors M7 and M5 are made conductive (when Outp discharges faster) or PMOS transistors M6 and M8 are made to discharge (when Outn discharges faster), recharging the respective node to VDD. This further increases the rate of discharge current flow through the respective cross-coupled NMOS transistors M4/M3. Under this action, a cascaded latch effect is created that drives Outn and Outp in opposite directions, and the process occurs at a rate proportional to the inputs INN and INP. Thus, for the inputs INN and INN in this textThe above process occurs more rapidly for embodiments where the INP is injected with a high pass filter component. Fig. 16 also includes an offset corrected differential pair 645 having a high frequency injection in parallel with the input differential pair. A similar arrangement is shown in figure 15. In some embodiments, voltage sampling driver 640 is used to provide a differential output voltage +/-VOUT by drawing a differential current through the integrator. In some embodiments, the amplification stage 630 includes a load resistor for providing the differential output voltage.

Fig. 7 illustrates an apparatus according to some embodiments. As shown, the apparatus includes a voltage sampling driver 640 for generating an output differential current based on at least a first differential current and a second differential current, the voltage sampling driver including an input differential branch pair for receiving a set of input signals +/-VIN, and each branch of the differential branch pair including one or more transistors for generating the first differential current. Voltage sampling driver 640 further comprises a pair of offset voltage branches for receiving an offset voltage control signal +/-VOC, and each branch of the pair of offset differential branches includes one or more transistors for generating the second differential current. The apparatus shown in fig. 7 further includes an amplification stage 630 coupled to the voltage sampling driver 640, the amplification stage 630 for generating a differential output voltage +/-VOUT based on the output differential current drawn by periodically activating the input differential finger pair and the offset differential finger pair. The apparatus also includes a high pass filter for supplementing high frequency components of the second differential current by injecting a high pass filtered set of input signals through the offset differential branch pair. In some embodiments, the periodic activation of the input differential finger pair and the offset differential finger pair is accomplished by respective tail current sources (illustrated as transistors). In some embodiments, the tail current sources are enabled by an input clock signal CK. In some embodiments, the magnitude of the current drawn by the respective tail current sources is independently adjustable (by adjusting transistor characteristics, etc.) to enable adjustment of the sampler frequency peak characteristics. By employing such offset differential finger pairs, input offset compensation can be achieved more easily than, for example, the capacitive trimming function in Razavi for providing offset correction within a latch. The advantages of the above embodiment over the other embodiment are further increased by providing additional high frequency gain with the offset differential branch pair. In addition, the current ratio between the input differential pair and the offset correction pair can be adjusted, thereby realizing that the direct current gain is changed while the high frequency gain is kept unchanged.

In some embodiments, the offset differential branch pair may be provided within a multi-input comparator, as shown in fig. 8. In one embodiment, the set of input signals received by the input differential branch pair within the multiple-input comparator corresponds to respective symbols of a vector signaling code codeword. As shown, the first branch receiving line w of the input differential branch pair ₀ And w ₁ And the second branch of the input differential branch pair receives the line w ₂ The symbol above. In some embodiments, as shown, the offset differential branch pair contains the same transistor structure as the input differential branch pair. In some embodiments, the input differential finger pair and the offset differential finger pair each include a pair of transistors. In some embodiments, the input differential branch pair and the offset differential branch pair each include one or more transistors. In some embodiments, each input signal in the input differential finger pair and the offset differential finger pair has a weight value applied thereto (as shown in fig. 2A and 2B). In some embodiments, the weight value is selected according to a certain row of the orthogonal matrix (e.g., in fig. 8, the weight value corresponds to row 3 of equation 4). In some embodiments, the weight value for a given input signal is determined by several identical transistors receiving the same input signal (e.g., a weight value equal to 2 in FIG. 8 represents two identical transistors, each receiving w ₂ As its input). In some embodiments, the weight values applied to a given input signal are determined by a weighting factor having an input weighting coefficient associated therewithIndividual transistors. In some embodiments, the input weighting factor is determined by transistor characteristics.

Fig. 9 illustrates a method 900 according to some embodiments. As shown, the method 900 includes: in step 902, receiving a set of input signals by an input differential branch pair; and in step 904, a first differential current is generated accordingly. In step 906, the offset voltage branch pair receives the offset voltage control signal at the input terminal and generates a second differential current in step 908, respectively. In step 910, a high pass filter supplements high frequency components of the second differential current by injecting a high pass filtered set of input signals at the input of the offset voltage branch pair. In step 912, an amplification stage connected to the input differential leg pair and the offset voltage leg pair generates an output differential current from the first and second differential currents. It should be noted that the steps in fig. 9 are not in any order, and certain steps may be performed simultaneously. For example, the first and second currents may be generated simultaneously by receiving the offset voltage control signal and the input signal in high frequency form at the inputs of the offset voltage branch pair while the set of input signals is received by the input differential branch pair. The output differential current is then formed by effectively superimposing the first and second differential currents on each other.

In some embodiments, generating the first and second differential currents comprises: enabling corresponding tail current sources of the input differential branch pair and the offset differential branch pair. In certain embodiments, the method further comprises: the respective tail current sources are periodically enabled by an input clock signal.

In certain embodiments, the method further comprises: generating a differential output voltage by extracting the output differential current through a pair of load resistors. In some embodiments, each load resistor has a respective capacitor connected between one end of the load resistor and ground. In some embodiments, the load resistor is adjustable. In some embodiments, the amplification stage further comprises an adjustable tail current source.

In some embodiments, the product of the current magnitude of the adjustable tail current source and the impedance magnitude of one of the load resistors is a constant value, wherein the method further comprises implementing bandwidth adjustment by adjusting the pair of load resistors and the adjustable current source. Alternatively, a product of a current magnitude of the adjustable tail current source and a magnitude of an impedance of one of the load resistors is not a constant value, wherein the method further comprises enabling power consumption adjustment by adjusting the pair of load resistors and the current source.

In some embodiments, each adjustable load resistor comprises a plurality of resistors in a parallel network, and the method further comprises selectively activating each of the plurality of resistors based on a respective switch receiving a respective control signal.

FIG. 10 illustrates an exemplary configuration of a multiple input comparator/offset voltage correction combination (similar to FIG. 8). As shown, fig. 10 includes a multiple input comparator/input stage and an offset voltage stage. The multiple input comparator/input stage includes a transistor (shown with input weighting coefficients for simplicity; however, this is not limiting), a load impedance, and a current source with a Clock (CK) input. Fig. 10 also includes an offset voltage stage similar to that on the right side of fig. 7, but with more than two inputs into the offset voltage stage. The offset voltage stage shown in fig. 10 employs similar advantageous features shown in the multiple-input comparator/input stage with a single transistor on the right with a 2-fold input weighting factor/coefficient. In some embodiments, the input weighting coefficients for the transistors are implemented by adjusting physical characteristics (e.g., channel width) of the transistors. In an alternative embodiment, the input weighting coefficients are implemented using several identical transistors, which are connected in parallel with each other and each receiving the same input in parallel.

FIG. 11 shows an embodiment similar to the embodiment of FIG. 10, but wherein the left side of the offset voltage stage shares a transistor with a 2 input weighting factor and which receives the signal w ₀ And w ₁ The high frequency component of (1). In some embodiments, the embodiments shown in fig. 10 and 11 may be selected according to design parameters such as device matching performance (e.g., parasitic input capacitance and physical capacitance).

Fig. 12 shows a combination of the embodiments shown in fig. 10 and 11, which achieves the advantage of reducing the number of transistors. Although the multiple-input comparator in the embodiments of fig. 10, 11, and 12 is illustrated without any equalization or bandwidth adjustment functionality, it should be noted that the equalization technique shown in fig. 3A and the bandwidth adjustment technique shown in fig. 13 and 14 may be used in any of the embodiments shown in fig. 10, 11, and 12.

FIG. 17 is a circuit schematic according to some embodiments. As shown, the circuit includes a multiple input comparator 1705, a digital to analog converter (for providing an offset correction voltage) 1710, an rc network, an offset correction pair 1715, an input differential pair 1720, and a summing node 1725. The multiple input comparator 1705 may take the form of a multiple input comparator as described above. In some embodiments, the RC network corresponds to the RC network shown in fig. 7 for injecting the high pass filtered multiple input comparator output into the differential current. The input differential pair 1720 (also called a sampler differential pair) is used to receive the differential output of the multiple input comparator 1705. In some embodiments, the summing node corresponds to a line node for summing currents from the input differential pair 1720 and the offset correction differential pair 1715.

Fig. 18, 19 and 20 show simulation results for a given subchannel (subchannel 4) for 12mm, 24mm and 80mm channels, respectively. Wherein, the cut-off frequency of the high-pass filter is shown as the following formula 6:

where Cin is an input capacitance of the offset corrected differential pair. Typical values for this equation may include: cin =2fF, C =9fF, R =2k to 200k.

Fig. 18 shows the simulation results for a 12mm channel, where R =200k. As shown, the eye opening increases from 166mV to 226mV after injecting the high pass filtered multiple input comparator output signal.

Fig. 19 shows the simulation result for a 24mm channel, where R =200k. As shown, the eye opening increases from 136mV to 172mV after injecting the high pass filtered multiple input comparator output signal.

Fig. 20 shows the simulation result for a 70mm channel, where R =2k. As shown, the eye opening increases from 33mV to 92mV after injecting the high pass filtered multiple input comparator output signal.

Although the above examples describe the application of vector signaling codes in point-to-point wired communications, this should not be construed as limiting the above embodiments in any way. The methods disclosed in the present application are equally applicable to other communication media including optical and wireless communications. Thus, descriptive words such as "voltage" or "signal level" etc. should be taken to include their equivalent concepts in other metrology systems, such as "light intensity", "radio frequency modulation", etc. The term "physical signal" as used herein includes all applicable forms and attributes of physical phenomena capable of conveying information. Further, the physical signal may be a tangible, non-transitory signal.

When a set of signals is understood as a selection of an object (e.g. a data object), it may include: the object is selected based at least in part on the set of signals and/or one or more attributes of the set of signals. When a set of signals is understood to be a representation of an object (e.g., a data object), it may include: the object is determined and/or selected based at least in part on a representation corresponding to the set of signals. Furthermore, the same set of signals may be used to select and/or determine a plurality of different objects (e.g., data objects).

Claims

1. An apparatus for detecting and equalizing a set of input signals, the apparatus comprising:

a voltage sampling driver to generate an output differential current from at least a sum of a first differential current and a second differential current, the voltage sampling driver comprising:

an input differential branch pair for receiving a set of input signals, each branch of the input differential branch pair comprising one or more transistors for generating the first differential current in response to the set of input signals;

an offset differential branch pair for facilitating input offset compensation and receiving an offset voltage control signal at an input, each branch of the offset differential branch pair comprising one or more transistors for generating the second differential current in response to receipt of the offset voltage control signal, wherein the offset voltage control signal is for canceling offset errors introduced by components of the voltage sampling driver;

an amplification stage connected to the voltage sampling driver, the amplification stage to generate a differential output voltage from the output differential current; and

a high pass filter for injecting the set of input signals after high pass filtering into the input terminals of the offset differential branch pair to supplement high frequency components of the second differential current;

wherein the voltage sampling driver further comprises respective tail current sources connected to each of the input differential finger pair and the offset differential finger pair, each tail current source having an independently adjustable magnitude to control the respective first differential current and the second differential current, the tail current sources for receiving an input clock signal to periodically enable the respective input differential finger pair and the offset differential finger pair to generate the output differential current.

2. The apparatus of claim 1, the amplification stage comprising:

a pair of load resistors for generating the differential output voltage from the output differential current, wherein each load resistor is adjustable;

a pair of capacitors, each capacitor connected between one end of a respective load resistor and ground; and

an adjustable tail current source.

3. The apparatus of claim 2, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the pair of load resistors is a constant value, wherein the pair of load resistors and the adjustable tail current source have bandwidth control inputs for adjusting a bandwidth.

4. The apparatus of claim 2, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the pair of load resistors is a non-constant value, wherein the pair of load resistors and the adjustable tail current source have power control inputs for adjusting power consumption.

5. The apparatus of claim 2, each adjustable load resistor comprising a plurality of resistors forming a parallel network, each resistor of the plurality of resistors having a respective switch connected between the resistor and a common node of the parallel network, wherein each switch is to switch the respective resistor into or out of the parallel network according to a respective control signal.

6. A method for detecting and equalizing a set of input signals, the method comprising:

receiving, by an input differential branch pair connected to a summing node, a set of input signals and generating a first differential current in response to the set of input signals;

receiving, by an offset differential branch pair connected to the summing node, an offset voltage control signal at an input to facilitate input offset compensation and generating a second differential current in response to the offset voltage control signal, wherein the offset voltage control signal is used to cancel offset errors introduced by components of a voltage sampling driver;

injecting the set of input signals after high-pass filtering processing into the input ends of the offset differential branch pair by using a high-pass filter so as to supplement high-frequency components of the second differential current; and

periodically activating respective tail current sources of the input differential branch pair and the offset differential branch pair using an input clock signal to generate an output differential current from a sum of the first differential current and the second differential current through an amplification stage connected to the summing node, wherein magnitudes of the first differential current and the second differential current are independently adjustable by the respective tail current sources.

7. The method of claim 6, further comprising generating a differential output voltage by drawing the output differential current through an adjustable pair of load resistors.

8. The method of claim 7, wherein each load resistor has a respective capacitor connected between one end of the load resistor and ground.

9. The method of claim 8, wherein the amplification stage further comprises an adjustable tail current source.

10. The method of claim 9, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the pair of load resistors is a constant value, wherein the method further comprises: bandwidth adjustment is performed by adjusting the pair of load resistors and the adjustable tail current source.

11. The method of claim 9, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the pair of load resistors is a non-constant value, wherein the method further comprises: power consumption adjustment is performed by adjusting the pair of load resistors and the adjustable tail current source.

12. The method of claim 7, wherein each adjustable load resistor comprises a plurality of resistors forming a parallel network, wherein the method further comprises: selectively activating a respective resistor of the plurality of resistors in accordance with a switch receiving a control signal.