CN108768573B - Clock synchronization method and device - Google Patents
Clock synchronization method and device Download PDFInfo
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- CN108768573B CN108768573B CN201810333472.7A CN201810333472A CN108768573B CN 108768573 B CN108768573 B CN 108768573B CN 201810333472 A CN201810333472 A CN 201810333472A CN 108768573 B CN108768573 B CN 108768573B
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Abstract
The clock synchronization method and device provided by the embodiment of the application are applied to a clock synchronization system, the system comprises a system master station clock and a plurality of slave station clocks which are connected to a bus, the plurality of slave station clocks belong to different clock synchronization subsystems, and the method comprises the following steps: a first slave station clock serving as a subsystem master station clock in each clock synchronization subsystem receives a first clock synchronization frame which is sent by the system master station clock and used for carrying out clock synchronization; performing clock synchronization with a system master station clock according to the first clock synchronization frame; and sending a second clock synchronization frame for clock synchronization to other slave station clocks in the clock synchronization subsystem to enable the other slave station clocks to perform clock synchronization with the first slave station clock, so that the system master station clock only performs clock synchronization with the first slave station clock serving as the subsystem master station clock in each clock synchronization subsystem, the software and hardware resources of the system master station clock can be saved, and the running performance of the clock synchronization system is improved.
Description
Technical Field
The application relates to the technical field of industrial internet, in particular to a clock synchronization method and device.
Background
At present, a large number of clock devices exist in the industrial field, the clock types of the clock devices are not necessarily the same, but the clock devices are used as slave station clocks and need to be synchronized with the system master station clock.
In the prior art, based on a real-time bus or a real-time ethernet, a slave station clock and a system master station clock can complete clock synchronization, so as to ensure transmission and processing of real-time data, but with the increasing number of slave station clocks, the real-time performance of clock synchronization between the slave station clock and the system master station clock is limited, which causes the poor real-time performance of data transmitted on the real-time bus or the real-time ethernet.
Therefore, the problem that the real-time performance of clock synchronization between the slave station clock and the system master station clock is poor exists in the prior art.
Disclosure of Invention
The embodiment of the application provides a clock synchronization method and a clock synchronization device, which are used for solving the problem that in the prior art, the real-time performance of clock synchronization between a slave station clock and a system master station clock is poor.
In a first aspect, a clock synchronization method provided in an embodiment of the present application is applied to a clock synchronization system, where the clock synchronization system includes a system master clock and multiple slave clocks connected to a bus, and the multiple slave clocks belong to different clock synchronization subsystems in the clock synchronization system, and the method includes:
and then, sending second clock synchronization frames for clock synchronization to other slave station clocks in the clock synchronization subsystem to enable the other slave station clocks to carry out clock synchronization with the first slave station clock.
By adopting the scheme, the clock synchronization system is divided into a plurality of clock synchronization subsystems, the system master clock only needs to be in clock synchronization with the first slave clock serving as the subsystem master clock in each clock synchronization subsystem, and subsequently, the first slave clock in each clock synchronization subsystem and the rest of the slave clocks in the subsystems are in clock synchronization, so that the number of the slave clocks in clock synchronization with the system master clock is greatly reduced, the clock synchronization between the slave clocks and the system master clock is better in real-time performance, the software and hardware resources such as a CPU (Central processing Unit) and a bandwidth of the system master clock can be saved, and the running performance of the whole clock synchronization system is further improved.
Under one possible implementation, the method further includes:
and any slave station clock in the receiving clock synchronization subsystem sends a third clock synchronization frame for clock synchronization, and performs clock synchronization with any slave station clock according to the third clock synchronization frame, wherein the third clock synchronization frame is sent after the any slave station clock takes over the first slave station clock as the subsystem master station clock.
By adopting the scheme, the clock of the first slave station serving as the clock of the master station of the subsystem in the clock synchronization subsystem is not fixed but adjustable, so that if the clock of the first slave station fails, the clock synchronization of the clock of the first slave station and the clock of the master station of the system can be carried out by taking over the clock of the first slave station by other slave station clocks, the clock synchronization of the clocks of the slave stations in the clock synchronization subsystem is maintained, and the robustness of the clock synchronization subsystem is good.
Under one possible implementation, the method further includes:
and receiving a fourth clock synchronization frame sent by the clock of the system master station, and performing clock synchronization with the clock of the system master station according to the fourth clock synchronization frame, wherein the fourth clock synchronization frame is sent by the clock of the system master station after the number of times that the clock synchronization subsystem and the master station clock of the replacement subsystem are determined exceeds the preset number, and the fourth clock synchronization frame is used for performing clock synchronization on all slave station clocks in the clock synchronization subsystem.
By adopting the scheme, after the system master station clock determines that the number of times of replacing the master station clock of the subsystem by a certain clock synchronization subsystem exceeds the preset number of times, the clock synchronization frame for carrying out clock synchronization on all the slave station clocks in the clock synchronization subsystem can be sent, so that the clock disorder problem caused by frequent replacement of the first slave station clock in one clock synchronization subsystem can be avoided.
In a second aspect, a clock synchronization apparatus provided in an embodiment of the present application is applied to a clock synchronization system, where the clock synchronization system includes a system master clock and multiple slave clocks connected to a bus, and the multiple slave clocks belong to different clock synchronization subsystems in the clock synchronization system, and the clock synchronization apparatus includes:
the receiving module is used for receiving a first clock synchronization frame which is sent by a system master station clock and used for clock synchronization;
the synchronization module is used for carrying out clock synchronization with the system master station clock according to the first clock synchronization frame;
and a sending module, configured to send a second clock synchronization frame for clock synchronization to another slave station clock in the clock synchronization subsystem, so that the other slave station clock performs clock synchronization with the first slave station clock.
The beneficial effects brought by any design manner in the second aspect of the present application can be referred to the technical effects brought by different implementation manners in the first aspect, and are not described herein again.
In a third aspect, a clock synchronization method provided in an embodiment of the present application is applied to a clock synchronization system, where the clock synchronization system includes a system master clock and multiple slave clocks connected to a bus, and the multiple slave clocks belong to different clock synchronization subsystems in the clock synchronization system, and the method includes:
each second slave station clock except for the clock of the master station of the subsystem in each clock synchronization subsystem receives a first slave station clock which is used as the clock of the master station of the subsystem in the clock synchronization subsystem and transmits a second clock synchronization frame used for clock synchronization, and the clock synchronization is carried out with the first slave station clock according to the second clock synchronization frame, wherein the second clock synchronization frame is transmitted after the first slave station clock receives a first clock synchronization frame transmitted by the clock of the master station of the system and carries out clock synchronization with the clock of the master station of the system according to the first clock synchronization frame.
By adopting the scheme, the clock synchronization is carried out on the first slave station clock serving as the subsystem master station clock in each clock synchronization subsystem and the system master station clock, and then the first slave station clock is used for time service to each second slave station clock in the subsystem, so that the number of the slave station clocks which are in clock synchronization with the system master station clock can be effectively reduced, and the clock synchronization between the slave station clocks and the system master station clock has better real-time performance.
Under one possible implementation, clock synchronization with the first slave station clock according to the second clock synchronization frame includes:
the clock information of the second slave station clock, the clock precision information and the clock information of the first slave station clock carried in the second clock synchronization frame are obtained, the time deviation between the second slave station clock and the first slave station clock is determined according to the clock information of the second slave station clock, the clock precision information and the clock information of the first slave station clock, and if the time deviation is determined to be smaller than a first threshold value, the clock information of the second slave station clock is adjusted according to the time deviation, so that clock synchronization with the first slave station clock is completed.
By adopting the mode, when any second slave station clock in each clock synchronization subsystem receives the clock synchronization frame sent by the first slave station clock in the subsystem, the precision of the first slave station clock is checked firstly, and only when the precision of the first slave station clock is determined to be higher than that of the first slave station clock, the clock synchronization with the first slave station clock is carried out, so that the clock synchronization mechanism is more reasonable.
In a possible implementation, if it is determined that the time offset between the second slave station clock and the first slave station clock is greater than the first threshold, the method further includes:
and adding one to a counter corresponding to the second slave station clock, applying for the system master station clock as the subsystem master station clock if the numerical value of the counter reaches a second threshold value, taking over the original first slave station clock to perform clock synchronization with the system master station clock after receiving a confirmation message sent by the system master station clock, and sending a third clock synchronization frame for performing clock synchronization to other slave station clocks in the clock synchronization subsystem.
By adopting the mode, each clock synchronization subsystem is used as the first slave station clock of the subsystem master station clock, when other slave station clocks in the subsystem are granted, each granted slave station clock can calibrate the precision of the first slave station clock, and when any slave station clock determines that the precision of the first slave station clock is not accurate for a plurality of continuous time-giving periods, the clock can be used as a new subsystem master station clock in the subsystem.
Under one possible implementation, the method further includes:
and receiving a fourth clock synchronization frame sent by the clock of the system master station, and performing clock synchronization with the clock of the system master station according to the fourth clock synchronization frame, wherein the fourth clock synchronization frame is sent by the clock of the system master station after the number of times that the clock synchronization subsystem and the master station clock of the replacement subsystem are determined exceeds the preset number, and the fourth clock synchronization frame is used for performing clock synchronization on all slave station clocks in the clock synchronization subsystem.
By adopting the scheme, when the system master station clock determines that the number of times of replacing the master station clock of the subsystem by a certain clock synchronization subsystem exceeds the preset number of times, the clock synchronization frame for carrying out clock synchronization on all the slave station clocks in the clock synchronization subsystem can be sent, so that the clock disorder problem caused by frequent replacement of the first clock in one clock synchronization subsystem can be avoided.
In a fourth aspect, an embodiment of the present invention provides a clock synchronization apparatus applied to a clock synchronization system, where the clock synchronization system includes a system master clock and multiple slave clocks connected to a bus, and the multiple slave clocks belong to different clock synchronization subsystems in the clock synchronization system, and the clock synchronization apparatus includes:
the receiving module is used for receiving a first slave station clock serving as a subsystem master station clock in the clock synchronization subsystem and a second clock synchronization frame which is sent by the clock synchronization subsystem and used for clock synchronization, wherein the second clock synchronization frame is sent by the first slave station clock after receiving the first clock synchronization frame sent by the system master station clock and is sent after clock synchronization is carried out on the first clock synchronization frame and the system master station clock;
and the synchronization module is used for carrying out clock synchronization with the first slave station clock according to the second clock synchronization frame.
The beneficial effects brought by any design manner in the fourth aspect of the present application can be referred to the technical effects brought by different implementation manners in the third aspect, and are not described herein again.
In a fifth aspect, the present application provides a clock synchronisation system comprising a system master clock and a plurality of slave clocks coupled to a bus, the plurality of slave clocks being respectively of different clock synchronisation subsystems in the clock synchronisation system, wherein each slave clock comprises first means, such as the clock synchronisation means of the second aspect, and second means, such as the clock synchronisation means of the fourth aspect.
In a possible implementation manner, a clock synchronization frame sent by any clock in the clock synchronization system is encapsulated at a designated position in a real-time data frame, where the real-time data frame refers to a data frame for transmitting data on a bus in real time, so that channel resources do not need to be occupied separately, and thus the channel resources can be saved.
In a sixth aspect, an embodiment of the present application provides a computer, including at least one processing unit and at least one storage unit, where the storage unit stores program code, and when the program code is executed by the processing unit, the computer is caused to perform the steps of any one of the clock synchronization methods described above.
In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, which includes program code, and when the program code runs on a computer, the computer is caused to execute the steps of any one of the clock synchronization methods described above.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
Drawings
Fig. 1 is a schematic diagram of a clock synchronization system applied to a clock synchronization method according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a frame structure of a clock synchronization frame according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a generation process of a subsystem master station clock in a clock synchronization subsystem a according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a clock synchronization method according to an embodiment of the present application;
fig. 5 is a structural diagram of a clock synchronization apparatus according to an embodiment of the present disclosure;
fig. 6 is a flowchart of another clock synchronization method provided in the embodiment of the present application;
fig. 7 is a structural diagram of another clock synchronization apparatus provided in an embodiment of the present application;
fig. 8 is a schematic hardware structure diagram of a computer for implementing any one of the clock synchronization methods according to the embodiment of the present application.
Detailed Description
In order to improve the real-time performance of clock synchronization between a slave station clock and a system master station clock, embodiments of the present application provide a clock synchronization method and apparatus.
First, some terms referred to in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.
The system master station clock has the functions of timing, time service and the like, generally has higher clock precision, is arranged at the front end of the bus and can be used for carrying out time service on a slave station clock connected with the bus.
The slave station clock has the functions of timing, time service, time synchronization and the like, has lower clock precision compared with the system master station clock, can be connected with the bus, receives a clock synchronization frame which is sent by the system master station clock and used for clock synchronization through the bus, and performs clock synchronization with the system master station clock according to the clock information of the system master station clock carried in the clock synchronization frame.
In the embodiment of the present application, the slave clocks divided into one clock synchronization subsystem have two roles, one is used as a subsystem master clock and performs clock synchronization with a system master clock on a bus, and the other is used as a general slave clock in the subsystem and performs clock synchronization with the subsystem master clock.
Referring to fig. 1, fig. 1 shows a schematic diagram of a clock synchronization system applied to the clock synchronization method in the present application, where the clock synchronization system includes a system master clock 0 and 9 slave clocks 1 to 9, the system master clock 0 and the slave clocks 1 to 9 are both connected to a bus, and then the slave clocks in the clock synchronization system may be divided according to the requirement of each slave clock to clock precision, assuming that three clock synchronization subsystems a to C are obtained, the slave clocks 1 to 3 belong to the clock synchronization subsystem a, the slave clocks 4 to 6 belong to the clock synchronization subsystem B, and the slave clocks 7 to 9 belong to the clock synchronization subsystem C.
It should be noted that fig. 1 is only an example, and in practice, the number of slave clocks included in the clock synchronization system is far more than 9, the number of divided clock synchronization subsystems is also far more than 3, and the slave clocks in the clock synchronization system may be divided according to the geographical position of the slave clocks, which is also only an example and is not limited to the basis of the divided clock synchronization subsystems.
Furthermore, each clock synchronization subsystem may have a subsystem master clock, as shown in fig. 1, the slave clock 1 is the subsystem master clock of the clock synchronization subsystem a, the slave clock 5 is the subsystem master clock of the clock synchronization subsystem B, and the slave clock 7 is the subsystem master clock of the clock synchronization subsystem C.
In specific implementation, a system master clock on a bus sends a first clock synchronization frame for clock synchronization to a subsystem master clock in each clock synchronization subsystem, the subsystem master clock in each clock synchronization subsystem adjusts its own clock information according to clock information of the system master clock carried in the first clock synchronization frame to complete clock synchronization with the system master clock, and then sends a second clock synchronization frame for clock synchronization to other slave clocks in its own clock synchronization subsystem to time service the other slave clocks.
Taking the clock synchronization subsystem a as an example, the slave station clock 1 in the clock synchronization subsystem a receives the system master station clock 0 to send a first clock synchronization frame, performs clock synchronization with the system master station clock 0 according to the clock information of the system master station clock 0 in the first clock synchronization frame, and then sends a second clock synchronization frame for performing clock synchronization to the slave station clocks 2 and 3, so that the slave station clocks 2 and 3 can perform clock synchronization with the slave station clock 1 according to the clock information of the slave station clock 1 in the second clock synchronization frame when receiving the second clock synchronization frame, and do not need to perform clock synchronization with the system master station clock 0 any more, and the clock synchronization subsystems B and C are similar and are not described herein again.
In the embodiment of the application, the system master clock is used for time transfer to the first slave clock which is used as the subsystem master clock in each clock synchronization subsystem, and the first slave station clock of the master station clock of each subsystem is used for time service to other slave station clocks in the clock synchronization subsystem, so that, in each clock synchronization subsystem, only one slave clock is clock synchronized with the system master clock, the other slave clocks need only be clock synchronized with the slave clock and need not be time synchronized with the system master clock, and therefore, the number of slave clocks that are directly clocked with the system master clock on the bus can be reduced, further, the real-time performance of clock synchronization between the slave station clock and the system master station clock is improved, and, the system can save software and hardware resources such as a CPU (central processing unit) and bandwidth of a system master station clock, and improve the running performance of the whole clock synchronization system.
In specific implementation, all slave station clocks in the clock synchronization subsystem are equal, so that when a first slave station clock serving as a subsystem master station clock in the clock synchronization subsystem fails or is reduced in precision, other slave station clocks in the clock synchronization subsystem can take over the clock synchronization work of the first slave station clock, and further the stability of the clock synchronization subsystem is improved.
For each clock synchronization subsystem, when any second slave station clock except the first slave station clock in the subsystem receives a second clock synchronization frame transmitted by the first slave station clock, the clock accuracy of the first slave station clock can be checked, and if the clock accuracy of the second slave station clock is lower than that of the first slave station clock, the clock synchronization with the first slave station clock is carried out; if the clock precision of the slave station clock is higher than that of the first slave station clock, the slave station clock with the highest precision in the clock synchronization subsystem can be used as the subsystem master station clock after a plurality of time service periods, and therefore the time precision of each slave station clock in the clock synchronization subsystem is improved.
For example, in fig. 1, when the slave clock 2 receives the second clock synchronization frame sent by the slave clock 1, the slave clock 2 may call its own base function to obtain its own clock information, and obtain the clock accuracy information and the clock information of the slave clock 1 from the second clock synchronization frame, and then input its own clock information, the clock accuracy information and the clock information of the slave clock 1 to the check function to obtain a value of the check function, and if the value of the check function is less than zero, the slave clock 2 may maintain its own clock role of the non-subsystem master; if the values of the check function are continuously more than zero for a plurality of time service periods, the slave station clock 2 can determine that the clock precision of the slave station clock is higher than that of the slave station clock 1, and can apply for a system master station clock 0 to serve as a new subsystem master station clock in the clock synchronization subsystem A.
Further, when receiving the request from the slave clock 2 and confirming that the clock accuracy of the slave clock 2 is higher than that of the slave clock 1, the system master clock 0 may transmit an acknowledgement message to the slave clock 2, and then the slave clock 2 takes over the clock synchronization of the slave clock 1 with the system master clock 0 and gives time to the slave clocks 1 and 3 in the clock synchronization subsystem a.
The encapsulation and the parsing of the clock synchronization frame mentioned in the embodiment of the present application are all completed in the data link layer, so that the real-time performance and the flexibility of the clock can be improved.
In the embodiment of the application, the length of the clock synchronization frame is 8 bytes, and the clock synchronization frame can be positioned in any frame header of a data frame for transmitting real-time data on a bus.
As shown in fig. 2, which is a schematic diagram of a frame structure of a clock synchronization frame provided in the embodiment of the present application, the clock synchronization frame includes 4 parts: the identifier, the type, the precision parameter 1 and the clock correction parameter 2 account for 64bits, wherein the identifier accounts for 5bits, the type accounts for 3bits, the precision parameter 1 accounts for 4bits, and the clock correction parameter 2 accounts for 52 bits.
The function of each part in the clock synchronization frame in fig. 2 is described below with reference to fig. 1.
Marking: fixed to 0xE8, for identifying clock synchronization frames;
type (2): the clock synchronization frame type (SyncType) is used for identifying the type of the clock synchronization frame, and for each slave station clock, the clock synchronization frame type can be processed only when the clock synchronization frame sent by the subsystem master station clock of the system master station or the subsystem slave station clock of the clock synchronization subsystem is received; otherwise, directly discarding, where whether to discard or not is determined according to the type of the clock synchronization frame, and the value range of the type of the clock synchronization frame is 0x0-0x8, where:
0x7 denotes a clock synchronization frame transmitted from the system master clock to all slave clocks, for example, the system master clock 0 needs to give time to all slave clocks 1 to 9, and the system master clock 0 can transmit a clock synchronization frame with SyncType of 0x 7.
0x1, a request frame sent by a slave clock as a subsystem master clock, for example, when the slave clock 1 wants to apply for a subsystem master clock in the clock synchronization subsystem a, the slave clock 1 may send a clock synchronization frame with SyncType of 0x1, and the clock synchronization frame is received by both the system master clock 0 and the slave clocks 2 to 9.
0x2 clock synchronization frame transmitted by the subsystem master clock, for example, the slave clock 1 in the clock synchronization subsystem a can transmit a clock synchronization frame with SyncType of 0x2 when the slave clock 2 and 3 are clocked by the slave clock 1.
0x3, for example, when the slave clock 3 wants to request for a new subsystem master clock in the clock synchronization subsystem a, the slave clock 3 may transmit a clock synchronization frame with SyncType of 0x3, the clock synchronization frame is received by the system master clock 0, and the clock synchronization frames are received by the other slave clocks 0, 1, 2, 4, 5, 6, 7, 8, 9.
0x0, the system master clock sends a clock synchronization frame to the master clocks of the subsystems, for example, if the system master clock 0 provides time for the slave clocks 1, 5, and 7, the system master clock 0 can send a clock synchronization frame with SyncType equal to 0x 0.
0x4, the clock synchronization frame that the system master clock sends to the designated clock synchronization subsystem, for example, if the system master clock 0 wants to give time to the slave clocks 1-3 in the clock synchronization subsystem a alone, the system master clock 0 can send the clock synchronization frame with SyncType of 0x 4.
Precision parameter 1: clock precision information of the sender clock carried in the clock synchronization frame.
Clock correction parameter 2: and clock information of the clock of the sender, namely the clock counter value of the clock of the master station or the clock of the slave station of the system, carried in the clock synchronization frame.
Base function base (x): the method is used for reading the clock information of the slave station clock as a receiving party of the clock synchronization frame, and the actual output value is within 32 bits by adopting a compression mode in consideration of the overflow condition.
Check function (x, y, z): where x is an output value of base (x) (i.e., clock information of the receiver clock); y is a function of 'precision parameter 1', the precision parameters 1 of the slave station clock and the system master station clock are determined by the clock crystal oscillator, and the absolute value of the difference value of the precision parameters 1 of the slave station clock and the system master station clock is represented. For example: the precision parameter 1 of the system master station clock is 10ns, the precision parameter 1 of the slave station clock is 20ns, and then the slave station clock y is: 20-10 ns; z is the value of the clock correction parameter 2 in the clock-synchronized data frame, and a simple check function can be of the form: function (x, y, z) ═ x + y-z.
Taking the slave station clock 2 as an example, when the slave station clock 2 receives a clock synchronization frame sent by the slave station clock 1, the slave station clock 2 can call a base function of itself to obtain clock counting information of itself, and obtain clock precision information and clock counting information of the slave station clock 1 in the clock synchronization frame, then, the information is input to a check function to further obtain a value of the check function, and if the value of the check function is greater than zero, a counter of the slave station clock 2 is added with 1; and if the value of the check function is smaller than zero, the slave station clock 2 adjusts the clock information of the slave station clock based on the value of the check function, and the time synchronization with the slave station clock 1 is completed.
In specific implementation, when the value of the slave clock 2 counter is 3, the slave clock 2 can set the sub-system master clock flag bit, and fill its clock information in the clock synchronization frame in the next time tick period, broadcast to the system master clock 0 and other slave clocks, and apply for the system master clock 0 as a new sub-system master clock.
When any other slave station clock receives the subsystem master station clock application sent by the slave station clock 2, the clock accuracy of the slave station clock 2 can be checked according to the self-checking function, and if the self-checking function is determined to be not higher than the slave station clock 2, the slave station clock 2 does not compete with the other slave station clocks; otherwise, it may compete with slave clock 2 as the new subsystem master clock.
Initially, the first slave clock serving as the master clock of each subsystem in each clock synchronization subsystem may be a clock of a first clock synchronization frame sent by the clock synchronization subsystem in response to the master clock of the system fastest, and subsequently, the first slave clock is generated by the slave clocks in the clock synchronization subsystem according to clock accuracy, so that the master clock of each subsystem mostly needs to be generated through two processes.
Taking the clock synchronization subsystem a as an example, the generation process of the subsystem master clock in the clock synchronization subsystem a can be performed according to fig. 3, which includes:
s301: the system master clock 0 sends clock sync frames to the slave clocks in all subsystems.
At this time, the system master clock 0 sends a clock synchronization frame with SyncType 0X7, which means that all slave clocks are required for processing, and fig. 3 only shows slave clocks 1 to 3 due to space limitation.
S302: the response is first broadcast from the station clock 2.
Assuming that the slave clock 2 firstly broadcasts and responds to the clock synchronization frame with SyncType of 0X7 sent by the system master clock 0, the slave clock 2 broadcasts and sends the clock synchronization frame with SyncType of 0X1 to the bus master 0 and all the slaves, and declares that the slave clock is the subsystem master clock in the clock synchronization subsystem a, at this time, the slave clocks in other subsystems do not process the clock synchronization frame, and after receiving the synchronization frame, other slave clocks in the clock synchronization subsystem can know that the slave clock 2 is the subsystem master clock in the clock synchronization subsystem a, and can record the clock identifier of the slave clock 2, so that for the clock synchronization subsystem a, an initial clock synchronization flow is established, and further, clock synchronization with the system master clock 0 can be performed according to the flow.
In the above process, if there is a case where a plurality of slave clocks claim to be applied as the subsystem master clock at the same time in the clock synchronization subsystem a, the slave clock processed first by the system master clock 0 is used as the subsystem master clock.
S303: the system master clock 0 clocks the slave clock 2.
In a specific implementation, the system master clock 0 first receives the response frame transmitted by the slave clock 2, determines the slave clock 2 as the subsystem master clock in the clock synchronization subsystem a, and further transmits a clock synchronization frame with SyncType of 0X0 to the slave clock 2 (and the subsystem master clock in the clock synchronization subsystem B, C) to time the slave clock 2.
S304: the slave clock 2 gives time to the slave clocks 1 and 3.
The slave clock 2 transmits a clock synchronization frame with SyncType of 0X2 to the slave clocks 1 and 3, and is used to time the slave clocks 1 and 3, so that the slave clocks 1 and 3 complete the clock information check and clock synchronization processing based on the clock synchronization frame.
S305: and the slave station clock 3 is verified and determined to apply for being the subsystem master station clock.
If a clock synchronization abnormality occurs in the clock synchronization subsystem a, when the slave station clock 3 receives the clock synchronization frame sent by the slave station clock 2 and checks the clock synchronization frame to determine that the clock accuracy of the slave station clock is high, the clock synchronization frame with SyncType of 0X3 can be sent for application as a new subsystem master station clock in the clock synchronization subsystem a.
S306: the system master clock 0 gives time to the slave clock 3.
After confirming that the slave clock 3 is the new subsystem master clock in the clock synchronization subsystem a, the system master clock 0 transmits a clock synchronization frame with SyncType of 0X0, and gives time to the slave clock 3.
S307: the slave clock 3 gives time to the slave clocks 1 and 2.
The slave clock 3 transmits a clock synchronization frame with SyncType 0X2 to the slave clocks 1 and 2, and is used for timing the slave clocks 1 and 2.
S308: the system master clock 0 sends a clock sync frame to all slave clocks in the subsystem a.
For the clock synchronization subsystem a, if the number of times of replacing the subsystem master clock exceeds 3 times, it indicates that the clock synchronization subsystem a may have relatively serious clock disorder, and the clock synchronization subsystem a may not be able to adjust the time of the clock back, at this time, the system master clock 0 may send a clock synchronization frame with SyncType of 0X4 to all slave clocks in the subsystem a, so as to time slave clocks 0 to 3 in the clock synchronization subsystem a.
Corresponding to the clock synchronization system, when the execution subject is the clock of the first slave station serving as the subsystem master in the clock synchronization system, the clock synchronization method provided in the embodiment of the present application may be executed according to the flow shown in fig. 4, and includes the following steps:
s401: and a first slave station clock serving as a subsystem master station clock in each clock synchronization subsystem receives a first clock synchronization frame which is sent by the system master station clock and used for clock synchronization.
At this time, SyncType of the first clock synchronization frame is 0x 0.
S402: and performing clock synchronization with a system master station clock according to the first clock synchronization frame.
Generally, the default is that the clock information of the system master clock on the bus is absolutely accurate, and the clocks of other slave stations are consistent with the system master clock, so that at this time, the first slave station clock only needs to acquire the clock information of the system master clock in the first clock synchronization frame, and then adjusts the clock information of the first slave station clock.
S403: and sending a second clock synchronization frame for clock synchronization to other slave station clocks in the clock synchronization subsystem, so that the other slave station clocks are in clock synchronization with the first slave station clock.
At this time, SyncType of the second clock synchronization frame is 0x 2.
For each clock synchronization subsystem, when the clock of the subsystem master station changes, the first slave station clock also receives a third clock synchronization frame which is transmitted by any slave station clock in the clock synchronization subsystem and used for clock synchronization, and performs clock synchronization with any slave station clock according to the third clock synchronization frame, wherein the third clock synchronization frame is transmitted by any slave station clock after taking over the first slave station clock as the clock of the subsystem master station, and SyncType of the third clock synchronization frame is 0x 2.
In a possible implementation, when the system master clock determines that the number of times that the clock synchronization subsystem changes the subsystem master clock exceeds the preset number, the system master clock further transmits a fourth clock synchronization frame to all slave clocks in the clock synchronization subsystem for clock synchronization of all slave clocks in the clock synchronization subsystem, so that the first slave clock further receives the fourth clock synchronization frame and performs clock synchronization with the system master clock according to the fourth clock synchronization frame, and SyncType of the fourth clock synchronization frame is 0x 4.
Based on the same inventive concept, the embodiment of the present application further provides a clock synchronization apparatus corresponding to the clock synchronization method, and as the principle of the apparatus for solving the problem is similar to the clock synchronization method in the embodiment of the present application, the implementation of the apparatus can refer to the implementation of the method, and repeated parts are not described again.
As shown in fig. 5, a structure diagram of a clock synchronization apparatus provided in an embodiment of the present application includes:
a receiving module 501, configured to receive a first clock synchronization frame sent by a system master station clock and used for clock synchronization;
a synchronization module 502, configured to perform clock synchronization with a system master clock according to the first clock synchronization frame;
a sending module 503, configured to send a second clock synchronization frame for performing clock synchronization to the other slave station clocks in the clock synchronization subsystem, so that the other slave station clocks perform clock synchronization with the first slave station clock.
In a possible implementation manner, the receiving module 501 is further configured to receive a third clock synchronization frame sent by any slave station clock in the clock synchronization subsystem for clock synchronization, where the third clock synchronization frame is sent by the any slave station clock after taking over the first slave station clock as the subsystem master station clock;
the synchronization module 502 is further configured to perform clock synchronization with the any slave station clock according to the third clock synchronization frame.
In a possible implementation manner, the receiving module 501 is further configured to receive a fourth clock synchronization frame sent by the system master clock, where the fourth clock synchronization frame is sent by the system master clock after determining that the number of times of the clock synchronization subsystem and the subsystem master clock is replaced exceeds a preset number, and the fourth clock synchronization frame is used to perform clock synchronization on all slave clocks in the clock synchronization subsystem;
the synchronization module 502 is further configured to perform clock synchronization with the system master clock according to the fourth clock synchronization frame.
Corresponding to the clock synchronization system, when the execution subject is the clock of the second slave station that is not the subsystem master station in the clock synchronization system, the clock synchronization method provided in the embodiment of the present application may be executed according to the flow shown in fig. 6, and includes the following steps:
s601: and each second slave station clock except the clock serving as the subsystem master station clock in each clock synchronization subsystem receives the first slave station clock serving as the subsystem master station clock in the clock synchronization subsystem and a second clock synchronization frame transmitted for clock synchronization.
And the second clock synchronization frame is sent after the first slave station clock receives the first clock synchronization frame sent by the system master station clock and carries out clock synchronization with the system master station clock according to the first clock synchronization frame.
S602: and performing clock synchronization with the first slave station clock according to the second clock synchronization frame.
Specifically, clock information of a second slave station clock, and clock precision information and clock information of a first slave station clock carried in a second clock synchronization frame are obtained, and further, according to the clock information of the second slave station clock, the clock precision information and the clock information of the first slave station clock, a time deviation between the second slave station clock and the first slave station clock is determined; and if the time deviation is determined to be smaller than the first threshold, adjusting the clock information of the second slave station clock according to the time deviation to finish clock synchronization with the first slave station clock.
In specific implementation, if it is determined that the time deviation between the second slave station clock and the first slave station clock is greater than the first threshold, a counter corresponding to the second slave station clock may be further incremented, and if it is determined that the value of the counter reaches the second threshold, the counter may apply for the system master station clock as the subsystem master station clock, and after receiving a confirmation message sent by the system master station clock, take over the original first slave station clock to perform clock synchronization with the system master station clock, and send a third clock synchronization frame for performing clock synchronization to other slave station clocks in the clock synchronization subsystem.
In a possible implementation manner, when the system master clock determines that the number of times that the clock synchronization subsystem changes the subsystem master clock exceeds the preset number, the system master clock further sends a fourth clock synchronization frame to all slave clocks in the clock synchronization subsystem for clock synchronization of all slave clocks in the clock synchronization subsystem, and at this time, the second slave clock further receives the fourth clock synchronization frame and performs clock synchronization with the system master clock according to the fourth clock synchronization frame.
Based on the same inventive concept, the embodiment of the present application further provides a clock synchronization apparatus corresponding to the clock synchronization method, and as the principle of the apparatus for solving the problem is similar to the clock synchronization method in the embodiment of the present application, the implementation of the apparatus can refer to the implementation of the method, and repeated parts are not described again.
As shown in fig. 7, a structure diagram of a clock synchronization apparatus provided in an embodiment of the present application includes:
a receiving module 701, configured to receive a first slave station clock serving as a subsystem master station clock in the clock synchronization subsystem, and a second clock synchronization frame sent for clock synchronization.
And the second clock synchronization frame is sent after the first slave station clock receives the first clock synchronization frame sent by the system master station clock and carries out clock synchronization with the system master station clock according to the first clock synchronization frame.
A synchronization module 702, configured to perform clock synchronization with the first slave station clock according to the second clock synchronization frame.
In a possible implementation, the synchronization module 702 is specifically configured to:
acquiring clock information of a second slave station clock, and clock precision information and clock information of a first slave station clock carried in a second clock synchronization frame;
determining the time deviation between the clock of the second slave station and the clock of the first slave station according to the clock information of the clock of the second slave station, the clock precision information of the clock of the first slave station and the clock information;
and if the time deviation is determined to be smaller than the first threshold value, adjusting the clock information of the second slave station clock according to the time deviation to finish clock synchronization with the first slave station clock.
In a possible implementation manner, the method further includes the verification module 703:
a checking module 703, configured to add one to a counter corresponding to the second slave station clock if it is determined that the time deviation between the second slave station clock and the first slave station clock is greater than the first threshold, apply for the system master station clock as the subsystem master station clock if it is determined that the value of the counter reaches the second threshold, and after receiving a confirmation message sent by the system master station clock, take over the original first slave station clock to perform clock synchronization with the system master station clock, and send a third clock synchronization frame for performing clock synchronization to other slave station clocks in the clock synchronization subsystem.
In a possible implementation manner, the receiving module 701 is further configured to receive a fourth clock synchronization frame sent by the system master clock, where the fourth clock synchronization frame is sent by the system master clock after determining that the number of times of the clock synchronization subsystem and the subsystem master clock is replaced exceeds a preset number, and the fourth clock synchronization frame is used to perform clock synchronization on all slave clocks in the clock synchronization subsystem;
the synchronization module 702 is further configured to perform clock synchronization with the system master clock according to the fourth clock synchronization frame.
The present invention also provides a clock synchronization system comprising a system master clock and a plurality of slave clocks connected to a bus, the plurality of slave clocks being respectively associated with different clock synchronization subsystems in the clock synchronization system, and each slave clock comprising first means and second means, wherein the first means is a first clock synchronization means as described above, and the second means is a second clock synchronization means as described above.
As shown in fig. 8, a hardware structure diagram of a computer for implementing a clock synchronization method provided in the embodiment of the present application includes a processor 801, a communication interface 802, a memory 803, and a communication bus 804, where the processor 801, the communication interface 802, and the memory 803 complete communication with each other through the communication bus 804.
A memory 803 for storing a computer program;
the processor 801 is configured to cause the computer to execute the steps of the first or second clock synchronization method when executing the program stored in the memory 803.
A computer-readable storage medium provided in an embodiment of the present application includes program code, and when the program code runs on a computer, the computer is caused to execute the steps of the first or second clock synchronization method.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (14)
1. A clock synchronization method for use in a clock synchronization system including a system master clock and a plurality of slave clocks coupled to a bus, the plurality of slave clocks being respectively associated with different clock synchronization subsystems in the clock synchronization system, the method comprising:
a first slave station clock serving as a subsystem master station clock in each clock synchronization subsystem receives a first clock synchronization frame which is sent by the system master station clock and used for clock synchronization;
the first slave station clock carries out clock synchronization with the system master station clock according to the first clock synchronization frame;
the first slave station clock transmits a second clock synchronization frame for clock synchronization to the other slave station clocks in the clock synchronization subsystem in which the first slave station clock is located, so that the other slave station clocks are in clock synchronization with the first slave station clock;
further comprising:
the first slave station clock receives a fourth clock synchronization frame sent by the system master station clock, the fourth clock synchronization frame is sent after the system master station clock determines that the number of times of replacing the subsystem master station clock by the clock synchronization subsystem where the first slave station clock is located exceeds a preset number, and the fourth clock synchronization frame is used for carrying out clock synchronization on all slave station clocks in the clock synchronization subsystem where the first slave station clock is located;
and the first slave station clock carries out clock synchronization with the system master station clock according to the fourth clock synchronization frame.
2. The method of claim 1, further comprising:
the first slave station clock receives a third clock synchronization frame which is sent by any slave station clock in a clock synchronization subsystem where the first slave station clock is located and is used for clock synchronization, and the third clock synchronization frame is sent by any slave station clock after the first slave station clock replaces the first slave station clock to serve as a subsystem master station clock;
and the first slave station clock is in clock synchronization with any slave station clock according to the third clock synchronization frame.
3. A clock synchronization method for use in a clock synchronization system including a system master clock and a plurality of slave clocks coupled to a bus, the plurality of slave clocks being respectively associated with different clock synchronization subsystems in the clock synchronization system, the method comprising:
each second slave station clock of each clock synchronization subsystem except for being used as a subsystem master station clock receives a second clock synchronization frame which is used for clock synchronization and is sent by a first slave station clock which is used as a subsystem master station clock in the clock synchronization subsystem where the second slave station clock is located, wherein the second clock synchronization frame is sent by the first slave station clock after receiving a first clock synchronization frame sent by the system master station clock and carrying out clock synchronization with the system master station clock according to the first clock synchronization frame;
the second slave station clock performs clock synchronization with the first slave station clock according to the second clock synchronization frame;
further comprising:
the second slave station clock receives a fourth clock synchronization frame sent by the system master station clock, the fourth clock synchronization frame is sent after the system master station clock determines that the number of times of replacing the subsystem master station clock by the clock synchronization subsystem where the second slave station clock is located exceeds a preset number, and the fourth clock synchronization frame is used for carrying out clock synchronization on all slave station clocks in the clock synchronization subsystem where the second slave station clock is located;
and the second slave station clock carries out clock synchronization with the system master station clock according to the fourth clock synchronization frame.
4. The method of claim 3, wherein the second slave station clock is clock synchronized to the first slave station clock in accordance with the second clock synchronization frame, comprising:
acquiring clock information of the second slave station clock, and clock precision information and clock information of the first slave station clock carried in the second clock synchronization frame;
determining a time deviation between the second slave station clock and the first slave station clock according to the clock information of the second slave station clock, the clock precision information of the first slave station clock and the clock information;
and if the time deviation is determined to be smaller than the first threshold, adjusting the clock information of the second slave station clock according to the time deviation to finish clock synchronization with the first slave station clock.
5. The method of claim 4, wherein if it is determined that the time offset is greater than the first threshold, further comprising:
adding one to a counter corresponding to the second slave station clock;
if the numerical value of the counter reaches a second threshold value, applying for the system master station clock as the subsystem master station clock;
and after receiving the confirmation message sent by the system master clock, taking over the clock synchronization between the original first slave clock and the system master clock, and sending a third clock synchronization frame for clock synchronization to other slave clocks in the clock synchronization subsystem where the second slave clock is located.
6. A clock synchronization apparatus for use in a clock synchronization system including a system master clock and a plurality of slave clocks coupled to a bus, the plurality of slave clocks being respectively associated with different clock synchronization subsystems in the clock synchronization system, the apparatus being located in a first slave clock of each clock synchronization subsystem as a subsystem master clock, comprising:
the receiving module is used for receiving a first clock synchronization frame which is sent by the system master station clock and used for clock synchronization;
the synchronization module is used for carrying out clock synchronization with the system master station clock according to the first clock synchronization frame;
a sending module, configured to send a second clock synchronization frame for clock synchronization to another slave station clock in the clock synchronization subsystem where the first slave station clock is located, so that the other slave station clock and the first slave station clock perform clock synchronization;
the receiving module is further configured to receive a fourth clock synchronization frame sent by the system master clock, where the fourth clock synchronization frame is sent by the system master clock after it is determined that the number of times that the subsystem master clock is replaced by the clock synchronization subsystem where the first slave clock is located exceeds a preset number, and the fourth clock synchronization frame is used to perform clock synchronization on all slave clocks in the clock synchronization subsystem where the first slave clock is located;
and the synchronization module is further used for performing clock synchronization with the system master station clock according to the fourth clock synchronization frame.
7. The apparatus of claim 6,
the receiving module is further configured to receive a third clock synchronization frame sent by any slave station clock in a clock synchronization subsystem where the first slave station clock is located, where the third clock synchronization frame is sent by the any slave station clock after taking over the first slave station clock as a subsystem master station clock;
and the synchronization module is further configured to perform clock synchronization with any slave station clock according to the third clock synchronization frame.
8. A clock synchronization apparatus for use in a clock synchronization system including a system master clock and a plurality of slave clocks coupled to a bus, the plurality of slave clocks being respectively associated with different clock synchronization subsystems in the clock synchronization system, the apparatus being located in each clock synchronization subsystem except for each second slave clock which is a subsystem master clock, comprising:
a receiving module, configured to receive a second clock synchronization frame for clock synchronization, sent by a first slave station clock serving as a subsystem master station clock in a clock synchronization subsystem in which the second slave station clock is located, where the second clock synchronization frame is sent after the first slave station clock receives a first clock synchronization frame sent by the system master station clock and performs clock synchronization with the system master station clock according to the first clock synchronization frame;
a synchronization module, configured to perform clock synchronization with the first slave station clock according to the second clock synchronization frame;
the receiving module is further configured to receive a fourth clock synchronization frame sent by the system master clock, where the fourth clock synchronization frame is sent by the system master clock after determining that the number of times that the clock synchronization subsystem where the second slave clock is located replaces the subsystem master clock exceeds a preset number, and the fourth clock synchronization frame is used to perform clock synchronization on all slave clocks in the clock synchronization subsystem where the second slave clock is located;
and the synchronization module is further used for performing clock synchronization with the system master station clock according to the fourth clock synchronization frame.
9. The apparatus of claim 8, wherein the synchronization module is specifically configured to:
acquiring clock information of the device, and clock precision information and clock information of the first slave station clock carried in the second clock synchronization frame;
determining a time offset between the apparatus and the first slave clock based on the clock information of the apparatus, the clock accuracy information of the first slave clock and the clock information;
and if the time deviation is determined to be smaller than a first threshold value, adjusting the clock information of the device according to the time deviation to finish clock synchronization with the clock of the first slave station.
10. The apparatus of claim 9, further comprising the verification module:
the checking module is configured to add one to a counter corresponding to the device if it is determined that the time deviation is greater than the first threshold; if the numerical value of the counter reaches a second threshold value, applying for the system master station clock as the subsystem master station clock; and after receiving the confirmation message sent by the system master clock, taking over the clock synchronization between the original first slave clock and the system master clock, and sending a third clock synchronization frame for clock synchronization to other slave clocks in the clock synchronization subsystem where the second slave clock is located.
11. A clock synchronisation system comprising a system master clock and a plurality of slave clocks coupled to a bus, the plurality of slave clocks being respectively associated with different clock synchronisation subsystems in the clock synchronisation system, wherein each slave clock comprises first means and second means, wherein the first means is a clock synchronisation means as claimed in claim 6 or claim 7 and the second means is a clock synchronisation means as claimed in any one of claims 8 to 10.
12. The system of claim 11, wherein a clock synchronization frame sent by any clock in the system is encapsulated at a specified location in a real-time data frame, the real-time data frame being a data frame for transmitting data in real-time over the bus.
13. A computer, comprising at least one processing unit and at least one memory unit, wherein the memory unit stores program code which, when executed by the processing unit, causes the computer to perform the steps of the method of any of claims 1 to 5.
14. A computer-readable storage medium, comprising program code means for causing a computer to carry out the steps of the method as claimed in any one of claims 1 to 5 when said program code means is run on the computer.
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