CN114731205A

CN114731205A - Clock synchronization method and device

Info

Publication number: CN114731205A
Application number: CN201980102220.6A
Authority: CN
Inventors: 黄天强; 刘威; 邱贤文
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2022-07-08
Also published as: WO2021097769A1

Abstract

A clock synchronization method and device are used for solving the problem of inaccurate time synchronization. The method comprises the following steps: the method comprises the steps that first equipment sends first data, time stamps are printed in the first data, the position of the data corresponding to the time stamps in the first data is determined, and first time of sending the data corresponding to the time stamps is determined; determining the transmission delay of the data of the position in the format conversion process; sending a first message to the second device, the first message indicating a time compensated for the first time; receiving a second message sent by the second device at a third time; and sending a third message containing the third time to the second equipment so as to enable the second equipment to carry out clock synchronization. The method compensates in advance through the determined transmission delay, effectively solves the problem that the clock synchronization is influenced by the data format conversion of the transmission data, and improves the accuracy of time synchronization.

Description

Clock synchronization method and device

Technical Field

The present invention relates to the field of wireless communications technologies, and in particular, to a clock synchronization method and apparatus.

Background

In order to improve the transmission efficiency of data, data clock synchronization is required between a transmitting side and a receiving side of the data. At present, the clock synchronization between the devices is mainly performed based on the precision clock synchronization protocol standard (IEEE1588 protocol) of the network measurement and control system.

As shown in fig. 1, the specific clock synchronization process between the data sender and the data receiver is as follows:

when the data sender transmits data to the data receiver, the data sender sends a synchronization (sync) message carrying data to the data receiver, and the data receiver records the receiving time T2 when receiving the sync message. Then, the data sender sends a following (follow _ up) message carrying a real time T1 of data sending to the data receiver, and the data receiver obtains the T1 in the follow _ up message. After receiving the Sync message, the data receiving side sends a Delay request (Delay _ req) message to the data sending side, and records a sending time T3 for sending the Delay _ req message. After receiving the Delay _ Req message, the data sender records the accurate receiving time T4 of the Delay _ Req message, and then sends a Delay response (Delay _ Resp) message carrying the T4 to the data receiver, and the data receiver obtains the T4 in the Delay _ Resp message. Therefore, the data receiver determines the time difference between the data sender and the data receiver and the path delay of the data transmission process according to four time points T1, T2, T3 and T4 based on the IEEE1588 protocol. And the data receiver realizes the clock synchronization between the data sender and the data receiver according to the determined time difference and the path delay.

However, in the communication service, when the data sender transmits data, it is often necessary to process the data format of the transmitted data. For example, when the data sending side and the data receiving side adopt a Clock Data Recovery (CDR) system to perform data transmission, a Forward error correction coding (FEC) technology is generally adopted to perform data format processing on transmission data. And the change of the data format of the transmission data can generate large delay jitter.

At present, in the prior art, when a data format cannot be changed for data, accurate clock synchronization between the data sender and the data receiver is realized, and thus, the data transmission efficiency between the data sender and the data receiver is reduced.

Disclosure of Invention

The embodiment of the application provides a clock synchronization method and a clock synchronization device, which are used for solving the problem that in the prior art, clock synchronization is not accurate enough when data formats are processed.

In a first aspect, an embodiment of the present application provides a clock synchronization method, used in a network environment formed by a first device, a conversion device, and a second device, where the conversion device is configured to perform format conversion on first data of the first device to obtain second data, and send the second data to the second device, and the method includes:

the first device sends the first data, stamps a time stamp in the first data, determines a data position of the data corresponding to the time stamp in the first data, and sends a first time of the data corresponding to the time stamp; the first equipment determines the transmission delay generated in the format conversion process of the data at the data position according to the data position; the first device sends a first message to the second device, wherein the first message is used for indicating a second time, and the second time is the time after the first time is compensated according to the transmission delay; the first equipment receives a second message sent by the second equipment at a third time; and the first equipment sends a third message to the second equipment, wherein the third message comprises the third time, so that the second equipment performs clock synchronization with the first equipment according to the second time, the third time and a fourth time for sending the second message.

Based on the scheme, in the communication transmission process, the first device determines the transmission delay generated in the data format conversion process of the transmission data and the first time for sending the data with the timestamp recorded in the first data, and then indicates the second time for clock synchronization of the second device according to the transmission delay and the first time, wherein the second time is the time after the first time is compensated according to the transmission delay, so that the second device performs clock synchronization according to the compensated sending time, the influence of delay jitter generated in the data format conversion process of the transmission data on clock synchronization is effectively solved, and the accuracy of time synchronization is improved.

In a possible implementation manner, the first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time; or the first message includes the second time.

In a possible implementation manner, the first message is a follow _ up message; the second message is a Delay request Delay _ req message; the third message is a Delay response Delay _ Resp message.

In a possible implementation manner, during transmission of the second data, a relative position of an alignment mark in the second data and data in the second data is unchanged.

In a second aspect, an embodiment of the present application provides a clock synchronization method, used in a network environment formed by a first device, a conversion device and a second device, where the conversion device is configured to perform format conversion on first data of the first device to obtain second data, and send the second data to the second device, and the method includes:

the second equipment receives second data sent by the conversion equipment; the second equipment receives a first message sent by the first equipment, wherein the first message is used for indicating a second time; the second time is the time after compensating the first time according to the transmission delay, the transmission delay is generated in the format conversion process of the data with the timestamp in the first data, and the first time is the sending time of the first equipment for sending the data corresponding to the timestamp; the second device sends a second message to the first device at a fourth time; the second device receives a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and the second equipment performs clock synchronization with the first equipment according to the second time, the third time and the fourth time.

Based on the scheme, in the communication transmission process, the second device receives a first message which is sent by the first device and indicates a second time, wherein the second time is the time after the first time is compensated according to the transmission delay, so that the second device carries out clock synchronization according to the compensated sending time, the delay jitter generated in the data format conversion process of the transmission data is effectively solved, the influence on the clock synchronization is avoided, and the accuracy of the time synchronization is improved.

In a possible implementation manner, before the second device performs clock synchronization with the first device according to the second time, the third time, and the fourth time, the method further includes: and the second equipment determines the second time according to the transmission delay and the first time contained in the first message.

In a possible implementation manner, during transmission of the second data, the relative position of the alignment mark in the second data and the data in the second data is unchanged.

In a third aspect, an embodiment of the present application provides a clock synchronization method, used in a network environment formed by a first device, a conversion device and a second device, where the conversion device is configured to perform format conversion on first data of the first device to obtain second data, and send the second data to the second device, and the method includes:

the second equipment receives second data sent by the conversion equipment; the second equipment determines the transmission delay of the time-stamped data in the second data in the format conversion process; the second equipment receives a first message sent by the first equipment, wherein the first message comprises the first time; the second device sends a second message to the first device at a fourth time; the second device receives a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and the second equipment performs clock synchronization with the first equipment according to the first time, the transmission delay, the third time and the fourth time.

Based on the scheme, in the communication transmission process, the second device determines the transmission delay generated in the data format conversion process of the data, and then compensates the received first time from the first device according to the transmission delay to obtain the second time, so that the clock synchronization is performed according to the second time, the influence of the data format processing of the transmission data on the clock synchronization is effectively solved, and the accuracy of the time synchronization is improved.

In a possible implementation manner, the second device compensates the first time according to the transmission delay to obtain a second time; and the second equipment performs clock synchronization with the first equipment according to the second time, the third time and the fourth time.

In a fourth aspect, an embodiment of the present application provides a communication apparatus having a function of implementing the devices in the first to third aspects in the foregoing embodiments. The function can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more units or modules corresponding to the above functions.

In a possible implementation manner, the communication apparatus may be the first device in the first aspect, or a component, such as a chip or a chip system or a circuit, which may be used in the first device, and the communication apparatus may include: a transceiver and a processor. The processor may be configured to enable the communication apparatus to perform the respective functions of the first device described above, and the transceiver is configured to enable communication between the communication apparatus and other devices (e.g., a second device), and so on. Optionally, the communication device may also include a memory, which may be coupled to the processor, that retains program instructions and data necessary for the communication device. The transceiver may be a separate receiver, a separate transmitter, a transceiver with integrated transceiving function, or an interface circuit.

In another possible implementation manner, the communication apparatus may be the second device in the second aspect or the third aspect, or a component, such as a chip or a chip system or a circuit, which may be used in the second device, and the communication apparatus may include: a transceiver and a processor. The processor may be configured to enable the communication apparatus to perform the respective functions of the second device described above, and the transceiver is configured to enable communication between the communication apparatus and other devices (e.g., the first device), and so on. Optionally, the communication device may also include a memory, which may be coupled to the processor, that retains program instructions and data necessary for the communication device. The transceiver may be a separate receiver, a separate transmitter, a transceiver with integrated transceiving function, or an interface circuit.

In a fifth aspect, an embodiment of the present application provides a communication apparatus, configured to implement any one of the foregoing first aspect or the first aspect.

In a possible implementation, when the communication apparatus is a first device, the method may include: processing unit and communication unit:

the communication unit is used for transmitting the first data;

the processing unit is used for stamping a time stamp in the first data, determining a data position of the data corresponding to the time stamp in the first data, and sending a first time of the data corresponding to the time stamp; determining transmission delay generated in the format conversion process of the data at the data position according to the data position;

the communication unit is configured to send a first message to the second device, where the first message is used to indicate a second time, and the second time is a time obtained by compensating the first time according to the transmission delay; receiving a second message sent by the second device at a third time; and sending a third message to the second device, wherein the third message comprises the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time and a fourth time for sending the second message.

In a sixth aspect, an embodiment of the present application provides a communication apparatus, configured to implement any one of the methods in the second aspect or the second aspect.

In a possible implementation, when the communication apparatus is a second device, the method may include: processing unit and communication unit:

the communication unit is used for receiving second data sent by the conversion equipment; receiving a first message sent by the first device, wherein the first message is used for indicating a second time; the second time is the time after compensating the first time according to the transmission delay, the transmission delay is generated in the format conversion process of the data with the timestamp in the first data, and the first time is the sending time of the first equipment for sending the data corresponding to the timestamp; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message;

and the processing unit is used for performing clock synchronization with the first equipment according to the second time, the third time and the fourth time.

In a seventh aspect, an embodiment of the present application provides a communication apparatus, configured to implement any one of the third aspect and the third aspect.

the communication unit is used for receiving second data sent by the conversion equipment;

the processing unit is used for determining transmission delay generated in the format conversion process of the data with the timestamp in the second data;

the communication unit is configured to receive a first message sent by the first device, where the first message includes the first time; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and performing clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time.

In an eighth aspect, an embodiment of the present application provides a communication system, which includes a first device and a second device. Wherein the first device may be configured to perform any of the first aspects above; or performing any one of the methods of the first aspect above;

the second device is configured to perform any of the second or third aspects above; or for performing any of the methods of the first or third aspects above.

In a ninth aspect, the present application provides a chip system comprising a processor. Optionally, the communication device may further include a memory, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the communication device with the chip system installed therein executes any one of the first to third surfaces; or performing any one of the methods of the first to third aspects described above.

In a tenth aspect, an embodiment of the present application provides a computer storage medium having instructions stored therein, which when run on a communication apparatus, cause the communication apparatus to perform any of the first to third aspects described above; or performing any one of the methods of the first to third aspects above.

In an eleventh aspect, embodiments of the present application provide a computer program product comprising instructions that, when run on a communication apparatus, cause the communication apparatus to perform any one of the first to third aspects described above; or performing any one of the methods of the first to third aspects above.

Drawings

Fig. 1 is a schematic diagram illustrating a message transmission between a sending device and a receiving device based on IEEE1588 in the prior art;

FIG. 2 is a schematic diagram illustrating a timestamp marking method in a conventional data transmission process;

FIG. 3 is a system architecture diagram according to an embodiment of the present application;

fig. 4 is a schematic flowchart corresponding to a time synchronization method according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating determining transmission delay by performing FEC coding according to an embodiment of the present application;

fig. 6 is a schematic diagram of compensation for the transmission time T1 according to an embodiment of the present application;

fig. 7 is a schematic flowchart corresponding to another clock synchronization method according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a first apparatus according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a second apparatus according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a first second apparatus according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a second apparatus according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a third second apparatus provided in an embodiment of the present application;

fig. 13 is a schematic structural diagram of a fourth second apparatus provided in the embodiment of the present application.

Detailed Description

The present application will now be described in detail with reference to the drawings attached hereto.

In communication services, when the data sender performs data transmission, it is often necessary to convert the data format of the transmission data in order to improve the data transmission efficiency and reduce the error rate. For example, when the data sender and the data receiver use the CDR/Retimer system for data transmission, FEC coding technology is generally used to perform data format conversion on the transmission data. The data format conversion of the transmission data may generate a large delay jitter, where the delay jitter generated by the data format conversion is referred to as a transmission delay in the embodiment of the present application.

For example, as shown in fig. 2, it is assumed that data at position a in the transmission data is used as a reference of a time stamp during data transmission, that is, the sending device uses the sending time of the data at position a as the sending time of the transmission data.

Case 1: data format conversion is not required for data transmitted from the first device to the second device.

For example, if the first device directly sends the data to be transmitted to the second device, the first device sends a sync message carrying the transmitted data to the second device, stamps a timestamp on the transmitted data, and determines a data position of the data corresponding to the timestamp in the transmitted data and a first time for sending the data corresponding to the timestamp. And the second equipment records that the time of receiving the sync message is 1:10 (namely time T2).

If the first device determines that the sending time of the position a data is 1:00, the first device determines that a timestamp driven into a follow _ up message is 1:00 according to the sending time 1:00, that is, after the first device determines the sending time of the position a data, a timestamp is generated according to the sending time, and the timestamp is carried in the follow _ up message. And the first equipment sends the follow _ up message to the second equipment. And the second device receives the follow _ up message and acquires the timestamp 1:00 (namely, the time T1) in the follow _ up message.

Thus, the second device can obtain the sum of the time difference Offset and the network transmission Delay of the first device and the second device according to the following formula 1 and the known T1 and T2.

T2-T1 ═ offset + Delay equation 1

When T1 is 1:00 and T2 is 1:10, the sum of Offset and Delay can be determined to be 10 by substituting the value into the formula 1.

In this embodiment, the term "timestamp the transmission data" refers to that the first device generates a credential document (i.e., a timestamp) after determining the sending time of the data at the location a, and the sending time of the data at the location a can be known through the timestamp. Further, the first device may record the credential document (i.e., the timestamp) in the follow _ up packet, and send the follow _ up packet to the second device, so that the second device obtains the sending time of the data at the location a.

It should be noted that the above explanation of "time stamping the transmission data" is not intended to limit the embodiments of the present application. Since the generation time of some events is often determined or proved by means of time stamping during the communication transmission, those skilled in the art can understand the meaning of "the first device time stamps in the transmission data" in the embodiment of the present application.

Case 2: data format conversion is required for data transmitted from the first device to the second device.

For example, the first device sends a sync message carrying the transmission data to the second device through a conversion device (for example, the conversion device is a CDR/timer), where the transmission data is subjected to data format conversion in the conversion device.

The first device determines the transmission time of the transmission data (i.e., the data at the position a), and if the transmission time of the transmission data is 1:00, the first device determines that the timestamp in the follow _ up message is 1:00 according to the transmission time 1: 00. Then, the first device sends the follow _ up message to the second device. And the second device receives the follow _ up message and acquires the timestamp 1:00 (namely, the time T1) in the follow _ up message.

However, the data format conversion of the transmission data in the conversion device may generate transmission delay, and it is assumed that the transmission delay generated by the data format conversion of the transmission data in the conversion device is 5 minutes. Therefore, the second device records that the time of receiving the sync message is 1:15 (i.e., time T2).

Thus, the second device can obtain the sum of the time difference Offset and the network transmission Delay of the first device and the second device according to the above equation 1 and the known T1 and T2.

The sum of Offset and Delay can be determined to be 15 by substituting T1 of 1:00 and T2 of 1:15 into the above formula 1.

Obviously, through the descriptions of the above cases 1 and 2, it can be known that the sum of Offset and Delay determined in the case 2 is not the real sum of Offset and Delay in the data transmission process between the first device and the second device, and therefore, the second device performs clock synchronization with the first device based on the Offset and Delay obtained in the case 2, which may generate a large error, and cannot achieve accurate clock synchronization.

Therefore, in the prior art, when data format processing is required for transmitted data, clock synchronization between the first device and the second device cannot be accurately realized, and thus data transmission efficiency between the first device and the second device is reduced.

On the other hand, when data format conversion is performed by the encoding technique, the delay jitter generated by the FEC encoding can be compensated according to the table 1 like below. However, the delay time generated by the FEC coding provided in the prior art is the maximum delay time that can be generated. Assuming the FEC (528, 541) in table 1 is taken as an example, it can be known that the maximum transmission delay that can be generated is 5.6ns when the port is 25. In each data transmission process, the timestamp is determined by taking the data at a certain position in the transmission data as a reference, and the transmission delay generated by data format conversion of the data at the position is not necessarily 5.6ns, and the prior art cannot compensate the data at the specific position in the clock synchronization process, and still has the problems of large clock synchronization error and incapability of realizing accurate clock synchronization.

FEC algorithm	Port(s)	Check bit	Uncertainty transmission delay (ns)
(528，514)	25	140	5.6
(528，514)	100	140	1.4
(544，514)	50	300	6
(544，514)	100	300	3
(544，514)	200	300	1.5
(544，514)	400	300	0.75

Table 1 transmission delay of uncertainty generated by FEC coding

In order to solve the above problem, an embodiment of the present application provides a method for clock synchronization, and a technical solution of the embodiment of the present application may be applied to various communication systems, for example: long Term Evolution (LTE) systems, Worldwide Interoperability for Microwave Access (WiMAX) communication systems, future fifth Generation (5th Generation, 5G) systems, such as new radio access technology (NR), and future communication systems, such as 6G systems, etc.

Taking a 5G system (may also be referred to as a New Radio system) as an example, specifically, in order to accurately solve the problem of transmission delay generated in a data format conversion process, in the embodiment of the present application, a transmission delay generated by performing data format conversion on transmission data is determined, and the transmission delay is compensated to a sending time, such as a sending time T1, when a first device sends data to a second device. By the method, when the second device performs clock synchronization with the first device, the sending time T1 for performing clock synchronization is compensated time, which eliminates transmission delay generated by data format conversion of the transmission data, thereby effectively solving the influence of the data format conversion process of the transmission data on clock synchronization and improving the accuracy of time synchronization.

It should be noted that the time synchronization in the embodiment of the present application may also be referred to as clock synchronization.

Fig. 3 is a schematic diagram of a system architecture applicable to the embodiment of the present application. As shown in fig. 3, the system architecture includes one or more first devices 301, such as a gNB, eNodeB, or WLAN access point, one or more second devices 302, one or more translation devices 303 (e.g., CDR/timer), and a core network 304.

In this embodiment, the first device 301 may include: a Base Transceiver Station (Base Transceiver Station), a wireless Transceiver, a Basic Service Set (BSS), an Extended Service Set (ESS), NodeB, eNodeB, gNB, and so on.

The system architecture may include several different types of first devices 301, such as a macro base station (macro base station), a micro base station (micro base station), and the like. The first device 301 may apply a different radio technology, e.g. a cell radio access technology, or a WLAN radio access technology.

The second device 302 may be a device with wireless transceiving function, which may be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on the water surface (such as a ship and the like); and may also be deployed in the air (e.g., airplanes, balloons, satellites, etc.). The terminal device may be a mobile phone (mobile phone), a tablet computer (Pad), a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal device in industrial control (industrial control), a wireless terminal device in self driving (self driving), a wireless terminal device in remote medical treatment (remote medical), a wireless terminal device in smart grid (smart grid), a wireless terminal device in transportation safety (transportation safety), a wireless terminal device in smart city (smart city), a wireless terminal device in smart home (smart home), and the like.

The core network device 304 may be a Mobility Management Entity (MME) in the LTE system, or an access and mobility management function (AMF) network element and a Session Management Function (SMF) network element in the 5G communication system, which is not limited specifically.

In the embodiment of the present application, the system architecture illustrated in fig. 3 is mainly used as an example for description, but is not limited thereto.

The communication system to which the above system architecture is applicable includes but is not limited to: wideband Code Division Multiple Access (WCDMA) mobile communication systems, evolved universal terrestrial radio access network (E-UTRAN) systems, Long Term Evolution (LTE) systems, future fifth Generation (5th Generation, 5G) systems, such as new radio access technology (NR), and future communication systems, such as 6G systems.

In the following, some terms referred to in the embodiments of the present application are explained for convenience of understanding.

1) FEC is a coding technique, and is a method for increasing the reliability of data communication by using an error control method. The method mainly refers to a technology that signals are encoded according to a certain algorithm in advance before being sent into a transmission channel, redundant codes with the characteristics of the signals are added, and the received signals are decoded at a receiving end according to the corresponding algorithm, so that error codes generated in the transmission process are found out and corrected.

2) The main principle of the Precision Clock Synchronization Protocol standard (IEEE1588 Precision Clock Synchronization Protocol) of the network measurement and control system is to periodically correct and synchronize clocks of all nodes in the network through a Synchronization signal, so that the ethernet-based distributed system can achieve Precision Synchronization, and the Precision Clock Synchronization Protocol standard has the characteristics of easiness in configuration, quick convergence, low network bandwidth and resource consumption and the like. The IEEE1588 clock synchronization technology described in the embodiments of the present application may be applied to any multicast network.

3) The message is a data unit exchanged and transmitted in the network, that is, a data block to be sent by the station at one time. The message contains complete data information to be sent, and the message is very inconsistent in length, unlimited in length and variable.

In an IEEE1588 time synchronization system, messages mainly include a sync synchronization message, a follow-up message, a delay _ req delay request message, and a delay _ resp delay response message. The sync message is periodically sent from a master clock and contains a timestamp that accurately describes the expected time of sending out a data packet by the master clock, where the expected time of sending out is not the actual time of sending out.

The follow message is sent from the master clock after the real sending time of the sync message is determined, and includes a time T1 for accurately describing the real sending time of the sync message sent by the master clock. The slave clock may determine a time difference (T2-T1) between the master clock and the slave clock according to a reception time T2 of the sync message and the real emission time T1 in the follow message.

However, the time difference calculated at this time includes the Delay caused by network transmission, so the Delay _ Req message is used to define the transmission Delay of the network.

The Delay _ Req message is sent by a slave clock after the slave clock receives the Sync message, and as with the Sync message, the slave clock of the sender records the accurate sending time T3 of the Delay _ Req message, and the master clock of the receiver records the accurate receiving time T4 of the Delay _ Req message. After receiving the Delay _ Req message, the master clock records the accurate receiving time T4 of the Delay _ Req message, then carries the T4 in a Delay _ Resp message sent to a slave clock, and informs the slave clock of the T4 through the Delay _ Resp message, so that the slave clock can calculate network Delay and clock error.

4) Reed-solomon codes (RS), which are a type of forward error correction channel code, are effective for the polynomial generated by correcting the oversampled data. When the receiver correctly receives enough points, it can recover the original polynomial, even if many points on the received polynomial are distorted by noise interference.

5) The retiming (Retimer) chip is mainly used for reconstructing a signal through an internal clock when the signal passes through the Retimer, so that the signal transmission energy is increased, and then the signal is continuously transmitted, so that the jitter of the signal can be reduced.

6) The time stamp is a complete and verifiable data that can represent that a piece of data already exists at a specific time point, and mainly provides an electronic evidence for a user to prove the generation time of some data of the user.

In general, the timestamp is an encrypted document of the certificate, which includes three parts: a summary of the file to be time stamped; the date and time the authentication unit received the file; a digital signature of the authentication unit.

In addition, the term "at least one" in the embodiments of the present application means one or more, and "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone, wherein, A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. Any combination of these items, including any combination of the singular or plural items, is meant by at least one of the following items or the like. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

Unless stated to the contrary, the embodiments of the present application refer to the ordinal numbers "first", "second", etc., for distinguishing between a plurality of objects, and do not limit the sequence, timing, priority, or importance of the plurality of objects.

Furthermore, the terms "comprising" and "having" in the description of the embodiments and claims of the present application and the drawings are not intended to be exclusive. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or modules listed, but may include other steps or modules not listed.

By introducing the application scenario in the embodiment of the present application, a process of performing clock synchronization based on the IEEE1588 protocol is specifically introduced below for a case where data format conversion is required for data transmission.

When the clock synchronization is performed according to the embodiment of the present application, a main mode is to compensate transmission delay generated in a data format conversion process of the data into transmission time, and then perform clock synchronization according to the compensated transmission time. However, depending on the implementation of the compensation, there are various situations, which will be described separately below.

In this embodiment, it is assumed that data at position a in the transmission data is used as a reference, and for convenience of subsequent description, a sending time when the first device sends data to the second device is denoted as T1, a receiving time when the second device receives the data is denoted as T2, a transmission delay generated by performing data format conversion on the data is Δ T, data that is not subjected to data format processing is simply referred to as first data, and data obtained by performing data format processing on the first data is simply referred to as second data.

The execution apparatus 1 that performs compensation: the first device compensates the sending time T1 according to the transmission delay Δ T generated by the data format conversion process of the transmission data.

As shown in fig. 4, when the executing device for performing compensation is a first device, the clock synchronization of the present application includes:

s400, the first device sends the first data to the conversion device, and records the sending time T1 of the first data.

In this embodiment, since the data of the position a in the transmission data is used as a reference in the present application, it can be understood that the sending time T1 is specifically a time when the first device sends the data of the position a in the first data.

Optionally, the first device may carry the first data through a sync message, that is, the first device sends the sync message carrying the first data to the conversion device.

S401, the conversion equipment performs data format conversion on the first data to generate second data.

S402, the conversion equipment sends the second data to second equipment.

S403, the second device receives the second data and records the time T2 when the second data is received.

In this embodiment, since the data of the position a in the transmission data is used as a reference in the present application, it can be understood that the receiving time T2 is specifically the time of the data of the position a in the second data received by the second device.

S404, the first device determines the time delay jitter delta t generated in the data format conversion process according to the first data and the second data.

Further, the first device may determine the Δ t according to a data transmission rate of the first data and a data transmission rate of the second data.

The first device may determine a data transmission rate of the first data according to the first data to be transmitted, and the first device may determine a transmission rate of the second data according to a rule for data conversion by the conversion device.

Optionally, in this embodiment of the application, the first device may determine the transmission delay Δ t according to the transmission rate of the first data and the transmission rate of the second data.

In this embodiment, since the data of the position a in the transmission data is used as a reference in the present application, the Δ t determined by the first device is a difference between a transmission time of the position a data in the first data and a transmission time of the position a data in the second data.

For example, in the embodiment of the present application, a detailed description is given by selecting to implement data format conversion on the first data through an FEC technology, and it should be noted that other manners that may change a data format may be applied to the embodiment of the present application.

As shown in fig. 5, it is assumed that, during data transmission, when the first device and the second device perform data transmission, clock synchronization is performed with reference to the 3000 th bit of transmission data. The first data format is RS (528,514), and the data transmission rate based on 100GE port is 4 x 25.78125 Gbps; the second data format is RS (544,514), and the data transmission rate based on 100GE port is 4 x 26.5625 Gbps; and the sending start bit of the first data is the same as the sending start bit of the second data, for example, the first data start bit and the second data start bit are both bit0, and the delay jitter of the first data start bit and the second data start bit is 0.

Wherein, the delay jitter generated by data format conversion of the 3000 th bit of the transmission data can be determined according to the following formula 2.

Δ t (bitx) ═ a/y (gbps) - (a)/z (gbps) formula 2

In the above formula 2, y (gbps) represents the data transmission rate of the first data, z (gbps) represents the data transmission rate of the second data, X represents a bit used as a reference of the time stamp, and a represents the number of bits corresponding to 0 to X bits, for example, when the bit is bit0, a represents data having a length of 1 bit; when the bit is bit1, a represents data of 2 bits length; when the bit number is bit3000, A represents data of 3001 bit length; Δ t represents delay jitter generated by data format conversion of the first data.

Therefore, based on the above equation 2, Δ t (bit3000) ═ 0.855ps can be obtained in (3001)/4/25.78125Gbps- (3001)/4/26.5625 Gbps.

It should be noted that, in addition to the above method for determining the transmission delay generated in the data format conversion process of the transmission data, any method for determining the transmission delay generated by the format conversion of the transmission data, which is applicable to the embodiments of the present application, belongs to the protection scope of the present application.

Further, the first device determines the direction of Δ t, i.e., the positive and negative of Δ t, so as to determine whether to increase or decrease the delay after the data format processing according to the direction of Δ t.

S405, the first device compensates the T1 according to the delta T to obtain the second time T1'.

If the Δ T direction is right, that is, if the Δ T is a positive value, it indicates that the Δ T is a transmission delay added on the basis of the first data transmission, and then the T1' is T1 +/Δ T; if the Δ T direction is left, that is, if the Δ T is a negative value, it indicates that the Δ T is a transmission delay decreased based on the first data transmission, and then the T1' is T1- Δ T.

For example, as shown in fig. 6, when data format conversion is required to be performed on transmission data sent by the first device to the second device, assuming that the transmission delay Δ T determined by the first device is increased by 5ns, the first device sends a sync message to the second device through the conversion device at 1:00 (i.e., T1). The second device receives the sync message at 1:15 (i.e., the T2).

Wherein the first device compensates the T1 according to the Δ T to obtain the T1', that is, the T1' is 1:00+0:05 is 1: 05.

Similarly, when the transmission data sent by the first device to the second device needs to be subjected to data format conversion, assuming that the transmission delay Δ T determined by the first device is reduced by 2ns, the first device sends a sync message to the second device through the conversion device at 1:02 (i.e., T1). The second device receives the sync message at 1:00 (i.e., the T2).

Wherein the first device compensates the T1 according to the Δ T to obtain the T1', that is, the T1 ═ 1:02 to 0:02 ═ 1: 00.

S406, the first device sends a first message (e.g., a follow _ up packet) to the second device, where the first message is used to indicate the second time T1'.

Optionally, in this embodiment of the application, the step S404 may be omitted, that is, the first device does not need to compensate the T1 according to the Δ T, so as to obtain the second time T1'. The first device may directly carry the T1 and the Δ T in the first message and send the first message to the second device, so that after the second device acquires the first message, the second device determines the T1' according to the T1 and the Δ T in the first message.

S407, the second device receives the first message, and obtains the T1' in the first message.

Optionally, if the information carried in the first message is the T1 and the Δ T, after the second device acquires the first message, it determines T1' by itself according to the T1 and the Δ T in the first message.

S408, the second device sends a second message (e.g., a Delay _ Req packet) to the first device, and records a sending time T3 of the second message.

S409, the first device receives the second message and records the time T4 when the second message is received.

S410, the first device sends a third message (for example, a delay _ resp packet) to the second device, where the third message includes the T4.

S411, the second device receives the third message, and acquires the T4 in the third message.

S412, the second device performs clock synchronization with the first device according to the T1', the T2, the T3 and the T4.

For example, in this embodiment of the application, when the first device and the second device implement time synchronization through the IEEE1588 protocol, it is necessary to determine a time difference Offset and a path transmission Delay between the first device and the second device, so that the second device implements time synchronization with the first device according to the calculated time difference Offset and path transmission Delay.

Wherein the second device performs a calculation according to the following equations 3 and 4:

T2-T1 ═ offset + delays equation 3

T4-T3 ═ offset + Delaysm equation 4

T2 in the formula 3 represents the time when the second device receives the transmission data sent by the first device, T1 represents the time when the first device actually sends the transmission data, offset represents the time difference between the devices during the communication between the first device and the second device, and Delayms represents the network path transmission delay when the first device transmits data to the second device.

T3 in the formula 4 represents the time when the second device sends the delay request message to the first device, T4 represents the time when the first device receives the delay request message, -offset represents the time difference between the second device and the first device during the communication transmission process, and Delaysm represents the network path transmission delay when the second device transmits data to the first device.

Since the transmitted transmission data is converted into a data format, and thus Δ T exists, the transmission time of the transmission data calculated by the second device substituting into equation 3 should be a compensated time, i.e., T1'.

The second device substitutes the T1', T2, T3, and T4 into the formula 3 and the formula 4 to obtain the formula 5.

Offset [ (T2-T1') - (T4-T3) - (delays-Delaysm) ]/2 formula 5

In the embodiment of the present invention, since the T1 is compensated in advance according to the Δ T, interference of the Δ T on the clock synchronization can be reduced when the clock synchronization is performed subsequently.

For example, Δ t is included in Offset when output transmission is performed, see the following equation 6:

offset ═ [ (T2-T1) - (T4-T3) - (Delayms +. DELTA.t-Delaysm) ]/2 equation 6

The Offset obtained in the present application is shown in the following formula 7:

offset [ (T2-T1') - (T4-T3) - (Delayms +. DELTA.t-Delaysm) ]/2 equation 7

Further, since T1 ═ T1 +. Δ T, the Offset obtained in the present application is as follows from equation 7:

Offset＝[(T2-T1+△t)-(T4-T3)-(Delayms+△t-Delaysm)]/2

＝[(T2-T1)-(T4-T3)-(Delayms-Delaysm)]/2

therefore, in the embodiment of the application, the sending time T1 is compensated, so that accurate clock synchronization of the second device can be performed on the premise of no other precision loss.

Further, in this embodiment of the application, when the first device transmits data to the second device, the relative position of an Alignment Mark (AM) in the data and data in the second data is not changed in the transmission process, that is, the first device passes through the data to be transmitted to the second device.

When the first device transmits the transmission data to the second device, the relative position of the data in the FEC codeword is fixed, and thus the path delay d is also fixed. Therefore, in the data transmission process, the accuracy of the clock synchronization of the first device by the second device can be effectively ensured only by determining the fixed path delay d of the path transmission.

It should be noted that, in the interaction flow shown in fig. 4 in this embodiment of the application, the order of some steps is not limited, for example, S404 may be executed before S402.

The execution device 2 that performs compensation: the second device compensates the sending time T1 for the transmission delay Δ T generated by the data format conversion process according to the data.

As shown in fig. 7, when the executing device performing compensation is a second device, the clock synchronization of the present application includes:

s700, the first device sends the first data to the conversion device, and records the time T1 for sending the first data.

S701, the conversion equipment performs data format processing on the first data to generate second data.

S702, the conversion equipment sends the second data to second equipment.

S703, the second device receives the second data, and records a time T2 when the second data is received.

S704, the second device determines the transmission delay generated in the format conversion process of the data of the second data recording timestamp.

Optionally, in this embodiment of the application, after the second device acquires the second data, the second device may determine the first data according to a data format conversion rule of the conversion device and the second data, and then determine the transmission delay Δ t according to the first data and the second data.

For a specific way of determining the transmission delay Δ t, refer to the above S404, which is not described herein again.

S705, the first device sends a first message (e.g., a follow _ up packet) to the second device, where the first message is used to indicate the T1.

S706, the second device receives the first message, and acquires the T1 in the first message.

S707, the second device compensates the T1 according to the delta T and determines a compensated T1'.

S708, the second device sends a second message (e.g., a Delay _ Req packet) to the first device, and records a sending time T3 of the second message.

S709, the first device receives the second message, and records a time T4 when the second message is received.

S710, the first device sends a third message (e.g., a delay _ resp packet) to the second device, where the third message includes the T4.

S711, the second device receives the third message, and obtains the T4 in the third message.

S712, the second device performs clock synchronization with the first device according to the T1', T2, T3 and T4.

The specific clock synchronization method is described in detail in step S412, and is not described herein again.

It should be noted that, in the interaction flow shown in fig. 7 in this embodiment of the application, the order of some steps is not limited, for example, S704 may be executed before S702.

Through the above description of the present application, it can be understood that, in order to implement the above functions, the above-described devices include hardware structures and/or software modules for performing the respective functions. Those of skill in the art will readily appreciate that the present invention can be implemented in hardware or a combination of hardware and computer software, with the exemplary elements and algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

Based on the above embodiment, as shown in fig. 8, a first device for clock synchronization provided by the present application includes a processor 800, a memory 801, and a communication interface 802.

The processor 800 is responsible for managing the bus architecture and general processing, and the memory 801 may store data used by the processor 800 in performing operations. The transceiver communication interface 802 is used for receiving and transmitting data under the control of the processor 800 in data communication with the memory 801.

The processor 800 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP. The processor 800 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. The memory 701 may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The processor 800, the memory 801 and the communication interface 802 are connected to each other. Optionally, the processor 800, the memory 801 and the communication interface 802 may be connected to each other through a bus 803; the bus 803 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 8, but this is not intended to represent only one bus or type of bus.

Specifically, the processor 800 is configured to read a program in the memory 801 and execute:

sending the first data, stamping a time stamp in the first data, determining the data position of the data corresponding to the time stamp in the first data, and sending the first time of the data corresponding to the time stamp; determining transmission delay generated in the format conversion process of the data at the data position according to the data position; sending a first message to the second device, wherein the first message is used for indicating a second time, and the second time is the time after the first time is compensated according to the transmission delay; receiving a second message sent by the second device at a third time; and sending a third message to the second device, wherein the third message comprises the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time and a fourth time for sending the second message.

In a possible implementation method, the first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time; or the first message includes the second time.

In a possible implementation method, during transmission of the second data, the relative position of the alignment mark in the second data and the data in the second data is unchanged.

As shown in fig. 9, the present invention provides a clock synchronization first apparatus, including: processing unit 900 and communication unit 901:

the communication unit 901 is configured to send the first data;

the processing unit 900 is configured to stamp a timestamp in the first data, determine a data position of the data corresponding to the timestamp in the first data, and send a first time of the data corresponding to the timestamp; determining transmission delay generated in the format conversion process of the data at the data position according to the data position;

the communication unit 901 is configured to send a first message to the second device, where the first message is used to indicate a second time, and the second time is a time obtained by compensating the first time according to the transmission delay; receiving a second message sent by the second device at a third time; and sending a third message to the second device, wherein the third message comprises the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time and a fourth time for sending the second message.

As shown in fig. 10, the embodiment of the present application further provides a clock synchronization second device, which includes a processor 1000, a memory 1001 and a communication interface 1002.

The processor 1000 is responsible for managing the bus architecture and general processing, and the memory 1001 may store data used by the processor 1000 in performing operations. The transceiver communication interface 1002 is used for receiving and transmitting data under the control of the processor 1000 in data communication with the memory 1001.

The processor 1000 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP. The processor 1000 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. The memory 1001 may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The processor 1000, the memory 1001 and the communication interface 1002 are connected to each other. Optionally, the processor 1000, the memory 1001 and the communication interface 1002 may be connected to each other through a bus 1003; the bus 1003 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 10, but this is not intended to represent only one bus or type of bus.

Specifically, the processor 1000 is configured to read a program in the memory 1001 and execute:

receiving second data sent by the conversion equipment; receiving a first message sent by the first device, wherein the first message is used for indicating a second time; the second time is the time after compensating the first time according to the transmission delay, the transmission delay is generated in the format conversion process of the data with the timestamp in the first data, and the first time is the sending time of the first equipment for sending the data corresponding to the timestamp; sending a second message to the first device at a fourth time; the second device receives a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and performing clock synchronization with the first equipment according to the second time, the third time and the fourth time.

In one possible implementation, the processor 1000 is further configured to:

and the second equipment determines the second time according to the transmission delay and the first time contained in the first message.

As shown in fig. 11, the present invention provides a clock synchronization second device, including: processing unit 1100 and communication unit 1101:

the communication unit 1101 is configured to receive second data sent by the conversion device; receiving a first message sent by the first device, wherein the first message is used for indicating a second time; the second time is the time after compensating the first time according to the transmission delay, the transmission delay is generated in the format conversion process of the data with the timestamp in the first data, and the first time is the sending time of the first equipment for sending the data corresponding to the timestamp; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message;

the processing unit 1100 is configured to perform clock synchronization with the first device according to the second time, the third time, and the fourth time.

As shown in fig. 12, the embodiment of the present application further provides another clock synchronization second device, which includes a processor 1200, a memory 1201 and a communication interface 1202.

The processor 1200 is responsible for managing the bus architecture and general processing, and the memory 1201 may store data used by the processor 1200 in performing operations. The transceiver communication interface 1202 is used to receive and transmit data under the control of the processor 1200 for data communication with the memory 1201.

The processor 1200 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP. The processor 1200 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. The memory 1201 may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The processor 1200, the memory 1201 and the communication interface 1202 are connected to each other. Optionally, the processor 1200, the memory 1201 and the communication interface 1202 may be connected to each other through a bus 1203; the bus 1203 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 12, but this is not intended to represent only one bus or type of bus.

Specifically, the processor 1200 is configured to read a program in the memory 1201 and execute:

receiving second data sent by the conversion equipment; determining transmission delay generated in the format conversion process of the data with the timestamp in the second data; receiving a first message sent by the first device, wherein the first message comprises the first time; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and performing clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time.

In one possible implementation, the processor 1200 is further configured to:

the second equipment compensates the first time according to the transmission delay to obtain a second time; and the second equipment performs clock synchronization with the first equipment according to the second time, the third time and the fourth time.

As shown in fig. 13, another clock synchronization first device provided by the present invention includes: processing unit 1300 and communication unit 1301:

the communication unit 1301 is configured to receive second data sent by the conversion apparatus;

the processing unit 1300 is configured to determine a transmission delay generated in a format conversion process of the time-stamped data in the second data;

the communication unit 1301 is configured to receive a first message sent by the first device, where the first message includes the first time; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and performing clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time.

In some possible implementations, various aspects of the clock synchronization method provided by the embodiments of the present invention can also be implemented in the form of a program product including program code for causing a computer device to perform the steps in the clock synchronization method according to various exemplary embodiments of the present invention described in this specification when the program code runs on the computer device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. Examples (a non-exhaustive list) of further embodiments of the readable storage medium in one implementation include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A program product for clock synchronization according to an embodiment of the present invention may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a server device. However, the program product of the present invention is not limited thereto, and in this document, the readable storage medium may be any tangible medium containing or storing the program, which can be used by or in connection with an information transmission, apparatus, or device.

A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the periodic network action system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device.

The embodiment of the application also provides a storage medium readable by the computing equipment aiming at the clock synchronization method, namely, the content is not lost after the power is cut off. The storage medium stores a software program comprising program code, which when executed on a computing device, when read and executed by one or more processors, implements any of the above aspects of the embodiments of the present application.

The present application is described above with reference to block diagrams and/or flowchart illustrations of methods, apparatus (systems) and/or computer program products according to embodiments of the application. It will be understood that one block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.

Accordingly, the subject application may also be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Furthermore, the application may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and figures are merely exemplary of the present application as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include such modifications and variations.

Claims

A method for clock synchronization, which is used in a network environment composed of a first device, a conversion device and a second device, wherein the conversion device is used for converting a format of first data of the first device to obtain second data, and sending the second data to the second device, the method comprising:

the first device sends the first data, stamps a time stamp in the first data, determines a data position of the data corresponding to the time stamp in the first data and a first time for sending the data corresponding to the time stamp;

the first equipment determines the transmission delay generated in the format conversion process of the data at the data position according to the data position;

the first device sends a first message to the second device, wherein the first message is used for indicating a second time, and the second time is the time after the first time is compensated according to the transmission delay;

the first equipment receives a second message sent by the second equipment at a third time;

and the first equipment sends a third message to the second equipment, wherein the third message comprises the third time, so that the second equipment performs clock synchronization with the first equipment according to the second time, the third time and a fourth time for sending the second message.
The method of claim 1, wherein the first message is used to indicate a second time, and comprises:

the first message comprises the first time and the transmission delay, so that the second equipment compensates the first time according to the transmission delay to obtain a second time; or

The first message includes the second time.
The method according to claim 1 or 2, wherein the first message is a follow _ up message; the second message is a Delay request Delay _ req message; the third message is a Delay response Delay _ Resp message.
The method according to any one of claims 1 to 3, wherein the alignment mark in the second data is unchanged from the data in the second data during transmission of the second data.
A method for clock synchronization, which is used in a network environment composed of a first device, a conversion device and a second device, wherein the conversion device is used for converting a format of first data of the first device to obtain second data, and sending the second data to the second device, the method comprising:

the second equipment receives second data sent by the conversion equipment;

the second equipment receives a first message sent by the first equipment, wherein the first message is used for indicating a second time; the second time is the time after compensating the first time according to the transmission delay, the transmission delay is generated in the format conversion process of the data with the timestamp in the first data, and the first time is the sending time of the first equipment for sending the data corresponding to the timestamp;

the second device sends a second message to the first device at a fourth time;

the second device receives a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message;

and the second equipment performs clock synchronization with the first equipment according to the second time, the third time and the fourth time.
The method of claim 5, wherein before the second device performs clock synchronization with the first device according to the second time, the third time, and the fourth time, further comprising:

and the second equipment determines the second time according to the transmission delay and the first time contained in the first message.
The method according to claim 5 or 6, wherein the first message is a follow _ up message; the second message is a Delay request Delay _ req message; the third message is a Delay response Delay _ Resp message.
The method according to any one of claims 5 to 7, wherein the alignment mark in the second data is unchanged from the data in the second data during transmission of the second data.
A method for clock synchronization, which is used in a network environment composed of a first device, a conversion device and a second device, wherein the conversion device is used for converting a format of first data of the first device to obtain second data, and sending the second data to the second device, the method comprising:

the second equipment receives second data sent by the conversion equipment;

the second device determines the transmission delay of the time-stamped data in the second data in the format conversion process;

the second equipment receives a first message sent by the first equipment, wherein the first message comprises the first time;

the second device sends a second message to the first device at a fourth time;

the second device receives a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message;

and the second equipment performs clock synchronization with the first equipment according to the first time, the transmission delay, the third time and the fourth time.
The method of claim 9, wherein the second device performs clock synchronization with the first device according to the first time, the transmission delay, the third time, and the fourth time, and comprises:

the second equipment compensates the first time according to the transmission delay to obtain a second time;

and the second equipment performs clock synchronization with the first equipment according to the second time, the third time and the fourth time.
The method according to claim 9 or 10, wherein the first message is a follow _ up message; the second message is a Delay request Delay _ req message; the third message is a Delay response Delay _ Resp message.
The method according to any one of claims 9 to 11, wherein the alignment mark in the second data is unchanged from the data in the second data during transmission of the second data.
A communications apparatus, comprising: a processing unit and a communication unit;

the communication unit is used for transmitting the first data;

the processing unit is used for stamping a time stamp in the first data, determining the position of the data corresponding to the time stamp in the first data, and sending the first time of the data corresponding to the time stamp; determining transmission delay generated in the format conversion process of the data at the data position according to the data position;

the communication unit is configured to send a first message to the second device, where the first message is used to indicate a second time, and the second time is a time obtained by compensating the first time according to the transmission delay; receiving a second message sent by the second device at a third time; and sending a third message to the second device, wherein the third message comprises the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time and a fourth time for sending the second message.
A communications apparatus, comprising: a processing unit and a communication unit;

the communication unit is used for receiving second data sent by the conversion equipment; receiving a first message sent by the first device, wherein the first message is used for indicating a second time; the second time is a time after compensating a first time according to a transmission delay, the transmission delay is generated in a format conversion process of data with a timestamp in the first data, and the first time is a sending time of the first device for sending the data corresponding to the timestamp; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message;

and the processing unit is used for performing clock synchronization with the first equipment according to the second time, the third time and the fourth time.
A communications apparatus, comprising: a processing unit and a communication unit;

the communication unit is used for receiving second data sent by the conversion equipment;

the processing unit is used for determining transmission delay generated in the format conversion process of the data with the timestamp in the second data;

the communication unit is configured to receive a first message sent by the first device, where the first message includes the first time; sending a second message to the first device at a fourth time; receiving a third message sent by the first device, wherein the third message comprises a third time when the first device receives the second message; and performing clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time.
A communications apparatus, comprising: one or more processors; a memory; one or more programs; wherein the one or more programs are stored in the memory, the one or more programs comprising instructions which, when executed by the processor, cause the communication device to perform the method steps of any of claims 1-4.
A communications apparatus, comprising: one or more processors; a memory; one or more programs; wherein the one or more programs are stored in the memory, the one or more programs comprising instructions which, when executed by the processor, cause the communication device to perform the method steps of any of claims 5-12.
A system for clock synchronization, comprising: a first device, a second device and a conversion device;

the first device for performing the method steps of any of claims 1 to 4;

the second device for performing the method steps of any one of claims 5 to 12;

the conversion device is configured to perform format conversion on the first data of the first device to obtain second data, and send the second data to the second device.
A computer-readable storage medium comprising computer instructions which, when executed on a first device, cause the first device to perform the method steps of any one of claims 1 to 4.
A computer-readable storage medium comprising computer instructions which, when executed on a second device, cause the second device to perform the method steps of any of claims 5 to 12.