CN112947678A - SoC dual-core system clock synchronization method and device - Google Patents
SoC dual-core system clock synchronization method and device Download PDFInfo
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- CN112947678A CN112947678A CN202110176147.6A CN202110176147A CN112947678A CN 112947678 A CN112947678 A CN 112947678A CN 202110176147 A CN202110176147 A CN 202110176147A CN 112947678 A CN112947678 A CN 112947678A
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Abstract
The application discloses a clock synchronization method and a device of an SoC dual-core system, wherein the method comprises the following steps: when the real-time core starts interruption, a first system clock and verification information are sent to a shared memory through the real-time core, and a first clock synchronization mark is set; when the management core regularly detects that a first clock synchronization mark exists in the shared memory, a first system clock and check information in the shared memory are obtained through the management core; and after the first system clock passes the anti-verification according to the verification information, updating the clock data of the management core by adopting the first system clock, thereby realizing clock synchronization. The method and the device can solve the technical problem that in the prior art, the management core cannot store the system clock after the clock is restarted, so that the product time keeping precision is influenced.
Description
Technical Field
The present application relates to the field of clock synchronization technologies, and in particular, to a clock synchronization method and apparatus for an SoC dual-core system.
Background
Along with the rapid development of a power distribution network, stricter requirements are made on the real-time detection capability of operating equipment and the operation reliability of protection automation equipment, two ARM processors and an FPGA are integrated in a System on Chip (System on Chip) dual-core System, data exchange is completed inside a Chip, and the Chip and the System on Chip cooperate with each other to efficiently work, so that the reliability of data exchange can be effectively improved, the complexity of a single board is reduced, and the power consumption is reduced.
At present, most of distribution automation terminals adopt a clock chip to clock, and a dual-core I is a management core, runs on an operating system and is responsible for data interaction with a master station and high-level application; and the second core is a real-time core and is responsible for processing high real-time tasks. When the standardized time-keeping precision test is carried out in the system, a management core clock needs to be acquired, but an RTC clock chip runs in a real-time core, the management core only has a soft clock, and the system clock of the management core cannot be saved in a power failure mode after the power failure restart, so that the time-keeping precision requirement of a power distribution terminal product cannot be met.
Disclosure of Invention
The application provides a clock synchronization method and device for an SoC dual-core system, which are used for solving the technical problem that in the prior art, the clock of the system cannot be stored by a management core after the clock is restarted, so that the time keeping precision of a product is influenced.
In view of this, a first aspect of the present application provides a clock synchronization method for an SoC dual-core system, including:
when the real-time core starts interruption, a first system clock and verification information are sent to a shared memory through the real-time core, and a first clock synchronization mark is set at the same time;
when the management core detects that the first clock synchronization mark exists in the shared memory at regular time, the first system clock and the check information in the shared memory are obtained through the management core;
and after the first system clock passes the anti-verification according to the verification information, updating the clock data of the management core by adopting the first system clock to realize clock synchronization.
Optionally, when the real-time core starts the interrupt, the real-time core sends the first system clock and the check information to the shared memory, and sets the first clock synchronization flag, which further includes:
after the format of the master station clock received by the master station is checked through the management check, the master station clock is stored in the shared memory, and a second clock synchronization mark is set;
when the real-time core detects that a second clock synchronization mark exists in the shared memory at regular time, acquiring a master station clock in the shared memory through the real-time core;
and updating the clock data of the real-time core by adopting the master station clock to realize the synchronization of the issued clock.
Optionally, when the real-time core starts the interrupt, the real-time core sends the first system clock and the check information to the shared memory, and sets the first clock synchronization flag, which further includes:
and after the SoC dual-core system is powered on, respectively carrying out initial system clock setting on the management core and the real-time core.
Optionally, after the SoC dual-core system is powered on, initial system clock setting is performed on the management core and the real-time core respectively, where the initial system clock setting includes:
and sending the RTC clock acquired from the RTC chip to the shared memory through the real-time core, so that the management core performs initial system clock setting according to the RTC clock acquired from the shared memory to obtain a first initial system clock, and the real-time core takes the RTC clock as a second initial system clock.
Optionally, the sending, by the real-time core, the RTC clock acquired on the RTC chip to the shared memory further includes:
if the real-time core fails to acquire the RTC clock from the RTC chip, the management core takes the Linux system clock maintained by the real-time core in the shared memory as the first initial system clock, and the real-time core takes the Linux system clock in the shared memory as the second initial system clock.
A second aspect of the present application provides a clock synchronization apparatus for SoC dual-core system, including:
the shared memory module is used for sending a first system clock and check information to a shared memory through a real-time core when the real-time core starts interruption, and setting a first clock synchronization mark;
a first clock obtaining module, configured to obtain, by a management core, the first system clock and the check information in the shared memory when the management core regularly detects that the first clock synchronization flag exists in the shared memory;
and the verification updating module is used for updating the clock data of the management core by adopting the first system clock after the first system clock passes the anti-verification according to the verification information, so as to realize clock synchronization.
Optionally, the method further includes:
the master station clock synchronization module is used for storing the master station clock in the shared memory and simultaneously setting a second clock synchronization mark after the format of the master station clock received by the master station is checked through the management check;
the second clock acquisition module is used for acquiring a master station clock in the shared memory through the real-time core when the real-time core regularly detects that a second clock synchronization mark exists in the shared memory;
and the clock updating module is used for updating the clock data of the real-time core by adopting the master station clock and realizing the synchronization of the issued clocks.
Optionally, the method further includes:
and the initialization module is used for respectively carrying out initial system clock setting on the management core and the real-time core after the SoC dual-core system is powered on.
Optionally, the initialization module is specifically configured to:
and sending the RTC clock acquired from the RTC chip to the shared memory through the real-time core, so that the management core performs initial system clock setting according to the RTC clock acquired from the shared memory to obtain a first initial system clock, and the real-time core takes the RTC clock as a second initial system clock.
Optionally, the method further includes:
and the acquisition failure module is used for taking the Linux system clock maintained by the real-time core in the shared memory as the first initial system clock and taking the Linux system clock in the shared memory as the second initial system clock if the real-time core fails to acquire the RTC clock on the RTC chip.
According to the technical scheme, the embodiment of the application has the following advantages:
in the present application, a clock synchronization method for an SoC dual-core system is provided, which includes: when the real-time core starts interruption, a first system clock and verification information are sent to a shared memory through the real-time core, and a first clock synchronization mark is set; when the management core regularly detects that a first clock synchronization mark exists in the shared memory, a first system clock and check information in the shared memory are obtained through the management core; and after the first system clock passes the anti-verification according to the verification information, updating the clock data of the management core by adopting the first system clock, thereby realizing clock synchronization.
According to the clock synchronization method for the SoC dual-core system, the shared memory is configured between the management core and the real-time core, the system clock in the real-time core is stored through the shared memory, the system clock is acquired by the management core, and the clock data updating of the management core is completed, so that the condition that the clocks of the management core are not synchronized due to power failure restarting is avoided, the clocks of the SoC dual-core system are ensured to be from the real-time core through the clock synchronization mode of the real-time core and the management core, and the time keeping precision of the SoC dual-core system is ensured through the verification mode. Therefore, the method and the device can solve the technical problem that the product time keeping precision is influenced because the management core cannot store the system clock after the clock is restarted in the prior art.
Drawings
Fig. 1 is a schematic flowchart of a clock synchronization method for an SoC dual-core system according to an embodiment of the present disclosure;
fig. 2 is another schematic flow chart of a SoC dual-core system clock synchronization method according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a SoC dual-core system clock synchronization apparatus according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For convenience of understanding, referring to fig. 1, a first embodiment of a clock synchronization method for an SoC dual-core system provided in the present application includes:
The shared memory is a memory which can be accessed by both the real-time core and the management core, can be set in advance according to needs, and is mainly used for storing information such as clocks, related marks and the like in the clock synchronization process. The verification information not only comprises information obtained by verifying the first system clock in real time, but also comprises verification mode information, so that the management of verification and verification is facilitated. The clock synchronization flag provides different states depending on whether synchronization is completed, thereby confirming whether the clock has been acquired by the management core and completing the clock synchronization operation.
When the real-time core starts interruption, the soft clock in the management core cannot be stored, the real-time core sends the first system clock to the shared memory at the moment, and a first clock synchronization mark is set for prompting the management core to perform clock synchronization operation.
And 102, when the management core regularly detects that the first clock synchronization mark exists in the shared memory, acquiring a first system clock and check information in the shared memory through the management core.
When the management checks that the first clock synchronization mark in the shared memory is in an unsynchronized state, the first system clock and the check information in the shared memory are acquired, and necessary information is acquired for the clock synchronization process of the management core.
And 103, after the first system clock passes the anti-verification according to the verification information, updating the clock data of the management core by using the first system clock, and realizing clock synchronization.
And when the first system clock is subjected to reverse verification timing according to the verification information, if the reverse verification is successful, the synchronous operation of the management core clock can be carried out, and the clock data of the management core is updated by the first system clock, so that the synchronous task can be completed.
The clock synchronization has the meaning of time-keeping testing, when a master station needs to perform the time-keeping testing on the dual-core system, the real-time core stores the clock of the time service equipment on an independent storage point, the management core updates clock data through the acquired clock to realize clock synchronization, and the master station can perform relatively accurate time-keeping testing operation on the dual-core system. The anti-verification can further ensure the accuracy of the clock.
According to the clock synchronization method for the SoC dual-core system, the shared memory is configured between the management core and the real-time core, the system clock in the real-time core is stored through the shared memory, the system clock is acquired by the management core, and the clock data updating of the management core is completed, so that the condition that the clocks of the management core are not synchronized due to power failure restarting is avoided, the clocks of the SoC dual-core system are ensured to be from the real-time core through the clock synchronization mode of the real-time core and the management core, and the time keeping precision of the SoC dual-core system is ensured through the verification mode. Therefore, the technical problem that in the prior art, the clock of the system cannot be saved by the management core after the clock is restarted, and the product time keeping precision is affected can be solved.
The above is an embodiment of a clock synchronization method for a SoC dual-core system provided by the present application, and the following is another embodiment of a clock synchronization method for a SoC dual-core system provided by the present application.
For convenience of understanding, please refer to fig. 2, the present application provides a second embodiment of a SoC dual-core system clock synchronization method, including:
The clock of the management core is mainly provided by the real-time core, the initial system clock setting process is not exceptional, the clock of the real-time core is provided by the RTC chip, the real-time core can acquire clock data from the RCT chip, and if the acquisition fails, the system clock in the Linux management core is adopted to update the clocks of the real-time core and the RTC chip simultaneously.
Further, step 201 includes:
the real-time clock acquired on the RTC chip is sent to the shared memory through the real-time core, so that the management core performs initial system clock setting according to the RTC clock acquired in the shared memory to obtain a first initial system clock, and the real-time core takes the RTC clock as a second initial system clock.
RTC clock TrtcIs a clock derived from a hardware chip. The real-time core acquires an RTC clock to provide the management core with the process of completing initial system clock setting, and the initial clock setting at the moment is recorded as a first initial system clock Tsys1And the real-time core acquires the RCT clock and completes the setting of the clock data thereof as a second initial system clock Tsys2。
Further, still include:
if the real-time core fails to acquire the RTC clock from the RTC chip, the management core takes the Linux system clock maintained by the real-time core in the shared memory as the first initial system clock, and the real-time core takes the Linux system clock in the shared memory as the second initial system clock.
Under the condition that the real-time core fails to acquire the RCT clock, the management core can manage the system clock T in the Linux kernelsysAnd storing the clock into a shared memory, wherein the clock is used for the real-time core to acquire and update the system clock of the real-time core to obtain a second initial system clock, performing time-keeping management on the acquired Linux system clock, namely maintaining the clock, then sending the maintained Linux system clock to the shared memory, and allowing the management core to acquire and update the system clock in the management core, so that the clock of the management core is always synchronous with the real-time core, namely the first initial system clock is always the synchronous clock maintained by the real-time core.
When receiving the clock time tick signal of the master station, firstly, the clock time tick message frame needs to be processed and analyzed, and the master station clock T issued by the master station is obtainedmstAnd after the verification is finished, the master station clock can be sent to the shared memory for storage through the management core, and meanwhile, a corresponding second clock synchronization mark is set.
The real-time core can also detect the shared memory at regular time, judge whether the second clock synchronization mark is in the state of incomplete synchronization, and if so, acquire the master clock in the shared memory.
And step 204, updating the clock data of the real-time core by adopting the master station clock, and realizing the synchronization of the issued clock.
The real-time core adopts the master station clock to update the clock data of the real-time core, and meanwhile, the master station clock is required to be updated into an RTC chip.
It can be understood that, in the above time service process from the master station to the management core and the real-time core, before clock synchronization from the real-time core to the management core is performed, clocks of the management core and the real-time core are issued by the master station once, and then the real-time core maintains the clocks, so as to achieve the purpose of keeping time. However, in the actual process, the time service of the master station does not only occur before the time-keeping process, but also occurs in the time-keeping process, that is, in the process of maintaining the management core clock by the real-time core, the master station may issue the system clock to the management core and the real-time core at irregular time, and update the clocks in the management core, the real-time core and the RTC chip.
And step 207, after the first system clock passes the anti-verification according to the verification information, updating the clock data of the management core by using the first system clock, so as to realize clock synchronization.
Please refer to steps 101 to 103 for the detailed process of steps 205 to 207, where it should be noted that the real-time core is a timer-enabled interrupt, and when the interrupt is enabled, the real-time core needs the current system clock, that is, the first system clock, so that the real-time core writes the first system clock into the shared memory and sets the corresponding synchronization flag. The management core firstly detects the synchronous mark and judges whether the synchronous operation is needed, if so, the first system clock and the verification information are read, and the local clock synchronous operation is executed after the verification, namely, the clock data of the management core is updated.
The clock synchronization operation is to perform timekeeping test, and the time service equipment is used as a reference, so that the time service equipment and the tested equipment simultaneously trigger an external hard contact to obtain clocks of the two equipment, and the clocks are compared to obtain a clock error; the specific operation process can be realized by the prior art, and is not described herein again.
The above is an embodiment of a clock synchronization method for a SoC dual-core system provided by the present application, and the following is an embodiment of a clock synchronization device for a SoC dual-core system provided by the present application.
For easy understanding, please refer to fig. 3, the present application provides an embodiment of a clock synchronization apparatus for an SoC dual-core system, including:
the shared memory module 301 is configured to send a first system clock and check information to a shared memory through a real-time core when the real-time core starts an interrupt, and set a first clock synchronization flag at the same time;
a first clock obtaining module 302, configured to obtain, by a management core, a first system clock and check information in a shared memory when the management core regularly detects that a first clock synchronization flag exists in the shared memory;
and the verification updating module 303 is configured to update the clock data of the management core by using the first system clock after the first system clock passes the inverse verification according to the verification information, so as to implement clock synchronization.
Further, still include:
the master station clock synchronization module 304 is configured to store the master station clock in the shared memory after the format of the master station clock received by the master station clock is checked by the management check, and set a second clock synchronization flag;
a second clock obtaining module 305, configured to obtain, by the real-time core, a master clock in the shared memory when the real-time core regularly detects that the second clock synchronization flag exists in the shared memory;
and the update clock module 306 is configured to update the clock data of the real-time core by using the master station clock, so as to implement synchronization of the issued clock.
Further, still include:
the initialization module 307 is configured to perform initial system clock setting on the management core and the real-time core, respectively, after the SoC dual-core system is powered on.
Further, the initialization module 307 is specifically configured to:
the real-time clock acquired on the RTC chip is sent to the shared memory through the real-time core, so that the management core performs initial system clock setting according to the RTC clock acquired in the shared memory to obtain a first initial system clock, and the real-time core takes the RTC clock as a second initial system clock.
Further, still include:
the acquisition failure module 308 is configured to, if the real-time core fails to acquire the RTC clock on the RTC chip, use the Linux system clock maintained by the real-time core in the shared memory as the first initial system clock, and use the Linux system clock in the shared memory as the second initial system clock by the real-time core.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for executing all or part of the steps of the method described in the embodiments of the present application through a computer device (which may be a personal computer, a server, or a network device). And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A clock synchronization method for an SoC dual-core system is characterized by comprising the following steps:
when the real-time core starts interruption, a first system clock and verification information are sent to a shared memory through the real-time core, and a first clock synchronization mark is set at the same time;
when the management core detects that the first clock synchronization mark exists in the shared memory at regular time, the first system clock and the check information in the shared memory are obtained through the management core;
and after the first system clock passes the anti-verification according to the verification information, updating the clock data of the management core by adopting the first system clock to realize clock synchronization.
2. The SoC dual-core system clock synchronization method according to claim 1, wherein when the real-time core starts an interrupt, the real-time core sends the first system clock and the verification information to the shared memory, and sets a first clock synchronization flag, and the method further comprises:
after the format of the master station clock received by the master station is checked through the management check, the master station clock is stored in the shared memory, and a second clock synchronization mark is set;
when the real-time core detects that a second clock synchronization mark exists in the shared memory at regular time, acquiring a master station clock in the shared memory through the real-time core;
and updating the clock data of the real-time core by adopting the master station clock to realize the synchronization of the issued clock.
3. The SoC dual-core system clock synchronization method according to claim 1, wherein when the real-time core starts an interrupt, the real-time core sends the first system clock and the verification information to the shared memory, and sets a first clock synchronization flag, and the method further comprises:
and after the SoC dual-core system is powered on, respectively carrying out initial system clock setting on the management core and the real-time core.
4. The SoC dual-core system clock synchronization method according to claim 3, wherein the performing initial system clock setting on the management core and the real-time core respectively after the SoC dual-core system is powered on comprises:
and sending the RTC clock acquired from the RTC chip to the shared memory through the real-time core, so that the management core performs initial system clock setting according to the RTC clock acquired from the shared memory to obtain a first initial system clock, and the real-time core takes the RTC clock as a second initial system clock.
5. The SoC dual-core system clock synchronization method according to claim 4, wherein the sending, by the real-time core, the RTC clock acquired on the RTC chip to the shared memory further comprises:
if the real-time core fails to acquire the RTC clock from the RTC chip, the management core takes the Linux system clock maintained by the real-time core in the shared memory as the first initial system clock, and the real-time core takes the Linux system clock in the shared memory as the second initial system clock.
6. A clock synchronization device for an SoC dual-core system, comprising:
the shared memory module is used for sending a first system clock and check information to a shared memory through a real-time core when the real-time core starts interruption, and setting a first clock synchronization mark;
a first clock obtaining module, configured to obtain, by a management core, the first system clock and the check information in the shared memory when the management core regularly detects that the first clock synchronization flag exists in the shared memory;
and the verification updating module is used for updating the clock data of the management core by adopting the first system clock after the first system clock passes the anti-verification according to the verification information, so as to realize clock synchronization.
7. The SoC dual-core system clock synchronization device according to claim 6, further comprising:
the master station clock synchronization module is used for storing the master station clock in the shared memory and simultaneously setting a second clock synchronization mark after the format of the master station clock received by the master station is checked through the management check;
the second clock acquisition module is used for acquiring a master station clock in the shared memory through the real-time core when the real-time core regularly detects that a second clock synchronization mark exists in the shared memory;
and the clock updating module is used for updating the clock data of the real-time core by adopting the master station clock and realizing the synchronization of the issued clocks.
8. The SoC dual-core system clock synchronization device according to claim 6, further comprising:
and the initialization module is used for respectively carrying out initial system clock setting on the management core and the real-time core after the SoC dual-core system is powered on.
9. The SoC dual-core system clock synchronization device according to claim 8, wherein the initialization module is specifically configured to:
and sending the RTC clock acquired from the RTC chip to the shared memory through the real-time core, so that the management core performs initial system clock setting according to the RTC clock acquired from the shared memory to obtain a first initial system clock, and the real-time core takes the RTC clock as a second initial system clock.
10. The SoC dual-core system clock synchronization device according to claim 9, further comprising:
and the acquisition failure module is used for taking the Linux system clock maintained by the real-time core in the shared memory as the first initial system clock and taking the Linux system clock in the shared memory as the second initial system clock if the real-time core fails to acquire the RTC clock on the RTC chip.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113589006A (en) * | 2021-07-30 | 2021-11-02 | 宁波三星医疗电气股份有限公司 | Electric energy meter operation clock control method |
| CN114115446A (en) * | 2021-11-30 | 2022-03-01 | 杭州迪普信息技术有限公司 | Method for sharing real-time clock and data processing equipment |
| CN116938379A (en) * | 2023-09-18 | 2023-10-24 | 湖北芯擎科技有限公司 | Method, device, electronic equipment and computer readable storage medium for time synchronization |
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2021
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113589006A (en) * | 2021-07-30 | 2021-11-02 | 宁波三星医疗电气股份有限公司 | Electric energy meter operation clock control method |
| CN114115446A (en) * | 2021-11-30 | 2022-03-01 | 杭州迪普信息技术有限公司 | Method for sharing real-time clock and data processing equipment |
| CN116938379A (en) * | 2023-09-18 | 2023-10-24 | 湖北芯擎科技有限公司 | Method, device, electronic equipment and computer readable storage medium for time synchronization |
| CN116938379B (en) * | 2023-09-18 | 2023-12-15 | 湖北芯擎科技有限公司 | Method, device, electronic equipment and computer readable storage medium for time synchronization |
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