CN108768410A - A kind of check-node update method suitable for Non-Binary LDPC Coded - Google Patents

A kind of check-node update method suitable for Non-Binary LDPC Coded Download PDF

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Publication number
CN108768410A
CN108768410A CN201810586671.9A CN201810586671A CN108768410A CN 108768410 A CN108768410 A CN 108768410A CN 201810586671 A CN201810586671 A CN 201810586671A CN 108768410 A CN108768410 A CN 108768410A
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minimum
values
value
sub
check
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胡鹏
周昱
张�荣
魏敬和
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1111Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1117Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

The present invention provides a kind of check-node update methods suitable for Non-Binary LDPC Coded, belong to channel coding/decoding technical field.V2C flexible messages are transformed into Δ domain, therefrom select the minimum value and sub-minimum of every a line, and in the first iteration preserve their position;The minimum value selected and sub-minimum are constituted into two kinds of configurations, produce the first additional row and the second additional row respectively;First value additionally arranged is used for updating the C2V values of the other positions in addition to minimum V2C values present position, and the second value additionally arranged is used for updating the C2V values on minimum V2C values position;Obtained C2V values are converted back into common domain;In successive iterations, compares in first time iteration two two V2C values in save location, select smaller value use.Fixed position select minimum value and it is double additionally arrange by way of, under the premise of not losing performance substantially, reduce comparison operation number, be greatly reduced computation complexity, reduce hardware spending, reduce cost.

Description

A kind of check-node update method suitable for Non-Binary LDPC Coded
Technical field
The present invention relates to channel coding/decoding technical fields, more particularly to a kind of check-node suitable for Non-Binary LDPC Coded Update method.
Background technology
Channel coding is to ensure the key technology of communication system and storage system reliably working.LDPC (binary low densities Parity check code) be a kind of performance programmable single-chip system shannon limit linear error correction code.In past more than ten year, binary system LDPC code It is rapidly progressed and is widely used in communication and data transmission system.Non-Binary LDPC Coded can show to compare binary system The better error correcting capability of LDPC code, lower error floor are simultaneously highly applicable to high order modulation.
The decoding algorithm of Non-Binary LDPC Coded has very much, and hard decision and soft-decision two major classes can be divided by being summed up.Wherein, Although hard decision algorithm realizes that simply performance is unsatisfactory, so being rarely employed in practical applications.Soft decision decoding is calculated In method, two kinds of factors of decoding complexity and performance are considered, minimum-sum algorithm more generally uses in hardware realization A kind of algorithm.It only has add operation, check-node there was only comparison operation when updating, obtain one when carrying out variable node update Capable minimum value and sub-minimum.And it is mainly to compare the fortune for finding minimum value to the present worth of decoder handling capacity in both operations It calculates.
Traditional comparing unit finds the structure of minimum value and sub-minimum as shown in Figure 1, D1, D2, D3, D4, D5, D6, D7, D8 represents the data of input comparing unit, and CP is comparing unit, and solid line represents minimum value, and dotted line represents sub-minimum.Some decodings Compare to shorten compares cycle to improve handling capacity and be carried out at the same time using three values or more value in device.Traditional comparison algorithm It is realized completely using comparator, according to m value comparators, finds minimum value and the minimum log of periodicity that sub-minimum usesmdc A compares cycle, wherein m indicate that a comparing unit simultaneously can be compared m value, dcThe degree for indicating check-node, that is, join The data amount check of the module is inputted when being updated with check-node.As the degree d of check-nodecWhen larger, compares cycle significantly increases. If the comparator inputted using four or more to reduce compares cycle, the Resources on Chip consumed obviously increases, to power consumption It is all very unfavorable with cost control.
Invention content
The purpose of the present invention is to provide a kind of check-node update methods suitable for Non-Binary LDPC Coded, existing to solve With the presence of check-node update method operation times it is more, calculate complicated, the big and of high cost problem of resource consumption.
In order to solve the above technical problems, the present invention provides a kind of check-node update side suitable for Non-Binary LDPC Coded Method includes the following steps:
V2C flexible messages are transformed into Δ domain by step 1;
Step 2, the minimum value and sub-minimum for therefrom selecting every a line, and in the first iteration protect their position It deposits;
The minimum value selected and sub-minimum are constituted two kinds of configurations by step 3, and production first additionally arranges respectively and second is additional Row;Described first value additionally arranged is used for updating the C2V values of the other positions in addition to minimum V2C values present position, and described second The value additionally arranged is used for updating the C2V values on minimum V2C values position;
Obtained C2V values are converted back common domain by step 4;
Step 5, in successive iterations, compare in first time iteration two two V2C values in save location, selection is more Small value uses, and repeats step 3~step 4.
Optionally, the minimum value selected and sub-minimum are constituted into two kinds of configurations in the step 3, it is additional produces first respectively Row and the second additional row are specially:Per a line minimum value and configuration, generates first and additionally arrange;Each row sub-minimum and configuration, it is raw At the second additional row.
Optionally, the minimum value that minimum value and configuration are as often gone.
Optionally, sub-minimum and it is configured to the sub-minimum of every row or the sum of two minimum values of not going together, the two take wherein Smaller value.
Optionally, in successive iterations, the comparison operation that each row carries out is primary.
Optionally, in the step 5, after reaching maximum iteration, stop iteration, export C2V values.
A kind of check-node update method suitable for Non-Binary LDPC Coded is provided in the present invention, by V2C flexible messages It is transformed into Δ domain, therefrom selects the minimum value and sub-minimum of every a line, and in the first iteration preserve their position;It will The minimum value and sub-minimum selected constitute two kinds of configurations, produce the first additional row and the second additional row respectively;Described first is additional The value of row is used for updating the C2V values of the other positions in addition to minimum V2C values present position, and the described second value additionally arranged is used for more C2V values on new minimum V2C values position;Obtained C2V values are converted back into common domain;In successive iterations, change more for the first time Two two V2C values in save location, select smaller value use in generation.The present invention selects minimum value by fixed position And double modes additionally arranged reduce comparison operation number under the premise of not losing performance substantially, and it is complicated that calculating is greatly reduced Degree reduces hardware spending, reduces cost.
Description of the drawings
Fig. 1 is traditional check-node updating unit comparison module schematic diagram;
Fig. 2 is the flow diagram of the check-node update method suitable for Non-Binary LDPC Coded;
Fig. 3 is schematic diagram of the V2C flexible messages under Δ domain.
Specific implementation mode
Below in conjunction with the drawings and specific embodiments to a kind of verification section suitable for Non-Binary LDPC Coded proposed by the present invention Point update method is described in further detail.According to following explanation and claims, advantages and features of the invention will be more clear Chu.It should be noted that attached drawing is all made of very simplified form and uses non-accurate ratio, only to conveniently, lucidly Aid in illustrating the purpose of the embodiment of the present invention.
Embodiment one
The present invention provides a kind of check-node update method suitable for Non-Binary LDPC Coded, flow diagram such as Fig. 2 It is shown.The check-node update method suitable for Non-Binary LDPC Coded includes the following steps:
Step S21, V2C flexible messages are transformed into Δ domain;
Step S22, the minimum value and sub-minimum of every a line are therefrom selected, and in the first iteration protects their position It deposits;
Step S23, the minimum value selected and sub-minimum are constituted into two kinds of configurations, produces the first additional row and the second volume respectively Outer row;Described first value additionally arranged is used for updating the C2V values of the other positions in addition to minimum V2C values present position, and described the Two values additionally arranged are used for updating the C2V values on minimum V2C values position;
Step S24, obtained C2V values are converted back into common domain;
Step S25, in successive iterations, compare in first time iteration two two V2C values in save location, selection Smaller value uses, and repeats step S23~step S24.
Specifically, V2C flexible messages are first transformed into Δ domain, as shown in figure 3, illustrating equally in finite field gf (4) lieutenant colonel Test node number of degrees dcIntertexture Δ message in the case of=5.Wherein, C1, C2, C3, C4, C5Non-zero in representing matrix H in certain a line The row of element composition, η indicate Δ index, and range is from 0 to 3;
Minimum value and sub-minimum of the V2C flexible messages per a line are selected, and in the first iteration preserves their position; In Fig. 3, the rows of η=0 minimum value and sub-minimum are that the row minimum values of 0, η=1 are 5, and sub-minimum 10, the row minimum values of η=2 are 10, Sub-minimum is that the minimum values of 15, η=3 are 9, sub-minimum 10.Preserve their position simultaneously;
The minimum value selected and sub-minimum are constituted into two kinds of configurations, produce the first additional row and the second additional row respectively;Tool Body, per a line minimum value and configuration, generates first and additionally arrange;Each row sub-minimum and configuration generate second and additionally arrange.It is minimum Value and the as often capable minimum value of configuration, sub-minimum and are configured to the sub-minimum of every row or the sum of two minimum values of not going together, The two takes smaller value therein.In the present embodiment one, minimum value is followed successively by 0,5,10,9 with element in configuration Δ W1;Sub-minimum It is followed successively by 0,10,14,10 with element in configuration Δ W2.It is worth noting that, from η=1 and η=3 (η=0 quilt in other row Select) minimum value can make up and configurations minimum and for 14.Here and 14 just than the sub-minimum 15 of the rows of η before=2 Smaller.First value additionally arranged is used for updating the C2V values of the other positions in addition to minimum V2C values present position, the second additional row Value be used for updating C2V values on minimum V2C values position;
Obtained C2V values are converted back into common domain;
In successive iterations, compares in first time iteration two two V2C values in save location, select smaller value It uses, repeats step 3~step 4.Therefore, in successive iterations, the comparison operation that each row carries out is only 1 time.It is maximum when reaching After iterations, stop iteration, exports C2V values.
The check-node update method suitable for Non-Binary LDPC Coded that the present embodiment one provides, is selected by fixed position Minimum value and double modes additionally arranged reduce comparison operation number, meter are greatly reduced under the premise of not losing performance substantially Complexity is calculated, reduces hardware spending, reduces cost.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.

Claims (6)

1. a kind of check-node update method suitable for Non-Binary LDPC Coded, which is characterized in that include the following steps:
V2C flexible messages are transformed into Δ domain by step 1;
Step 2, the minimum value and sub-minimum for therefrom selecting every a line, and in the first iteration preserve their position;
The minimum value selected and sub-minimum are constituted two kinds of configurations by step 3, produce the first additional row and the second additional row respectively; Described first value additionally arranged is used for updating the C2V values of the other positions in addition to minimum V2C values present position, and described second is additional The value of row is used for updating the C2V values on minimum V2C values position;
Obtained C2V values are converted back common domain by step 4;
Step 5, in successive iterations, compare in first time iteration two two V2C values in save location, select smaller Value uses, and repeats step 3 ~ step 4.
2. being suitable for the check-node update method of Non-Binary LDPC Coded as described in claim 1, which is characterized in that the step The minimum value selected and sub-minimum are constituted into two kinds of configurations in rapid 3, producing first respectively, additionally row and the second additional row are specially: Per a line minimum value and configuration, generates first and additionally arrange;Each row sub-minimum and configuration generate second and additionally arrange.
3. being suitable for the check-node update method of Non-Binary LDPC Coded as claimed in claim 2, which is characterized in that minimum value The as often capable minimum value with configuration.
4. being suitable for the check-node update method of Non-Binary LDPC Coded as claimed in claim 2, which is characterized in that sub-minimum The sum for minimum value of not going together with the sub-minimum for being configured to every row or two, the two take smaller value therein.
5. being suitable for the check-node update method of Non-Binary LDPC Coded as described in claim 1, which is characterized in that follow-up In iteration, the comparison operation that each row carries out is primary.
6. being suitable for the check-node update method of Non-Binary LDPC Coded as described in claim 1, which is characterized in that the step In rapid 5, after reaching maximum iteration, stops iteration, export C2V values.
CN201810586671.9A 2018-06-08 2018-06-08 A kind of check-node update method suitable for Non-Binary LDPC Coded Pending CN108768410A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104052501A (en) * 2014-06-26 2014-09-17 北京航空航天大学 Multi-system LDPC decoding method low in complexity
CN105024704A (en) * 2015-07-17 2015-11-04 西安空间无线电技术研究所 Low-complexity column layered LDPC decoder realizing method
CN105846832A (en) * 2016-03-21 2016-08-10 联想(北京)有限公司 Check node operation unit, check node, storage device and information processing method
CN106330203A (en) * 2016-08-26 2017-01-11 晶晨半导体(上海)有限公司 Decoding method for LDPC (Low Density Parity Check Code)
CN106374940A (en) * 2016-11-14 2017-02-01 中国电子科技集团公司第五十四研究所 Multi-system LDPC decoding method and decoder
CN107005251A (en) * 2014-11-19 2017-08-01 领特投资两合有限公司 The LDPC decodings of dynamic adjustment with finite accuracy and iterations
CN107707334A (en) * 2017-09-29 2018-02-16 桂林电子科技大学 It is a kind of based on the grid EC T MM interpretation methods additionally arranged

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104052501A (en) * 2014-06-26 2014-09-17 北京航空航天大学 Multi-system LDPC decoding method low in complexity
CN107005251A (en) * 2014-11-19 2017-08-01 领特投资两合有限公司 The LDPC decodings of dynamic adjustment with finite accuracy and iterations
CN105024704A (en) * 2015-07-17 2015-11-04 西安空间无线电技术研究所 Low-complexity column layered LDPC decoder realizing method
CN105846832A (en) * 2016-03-21 2016-08-10 联想(北京)有限公司 Check node operation unit, check node, storage device and information processing method
CN106330203A (en) * 2016-08-26 2017-01-11 晶晨半导体(上海)有限公司 Decoding method for LDPC (Low Density Parity Check Code)
CN106374940A (en) * 2016-11-14 2017-02-01 中国电子科技集团公司第五十四研究所 Multi-system LDPC decoding method and decoder
CN107707334A (en) * 2017-09-29 2018-02-16 桂林电子科技大学 It is a kind of based on the grid EC T MM interpretation methods additionally arranged

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SUWEN SONG 等: "A reduced complexity decoding algorithm for NB-LDPC codes", 《2017 IEEE 17TH INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY》 *
张亚林 等: "一种多进制LDPC编译码器硬件的实现方法", 《无线电工程》 *

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Application publication date: 20181106