CN105846832A - Check node operation unit, check node, storage device and information processing method - Google Patents
Check node operation unit, check node, storage device and information processing method Download PDFInfo
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- CN105846832A CN105846832A CN201610162828.6A CN201610162828A CN105846832A CN 105846832 A CN105846832 A CN 105846832A CN 201610162828 A CN201610162828 A CN 201610162828A CN 105846832 A CN105846832 A CN 105846832A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
Abstract
The invention discloses a check node operation unit, a check node, a storage devices and an information processing method. The check node operation unit includes a comparison module used for obtaining a minimum value in information transmitted to a check node by a variable node through comparison, and a mapping module used for obtaining a post-reduction minimum value or second smallest value according to mapping rules and the minimum value.
Description
Technical field
The present invention relates to areas of information technology, particularly relate to a kind of check-node arithmetic element, check-node, storage device and information processing method.
Background technology
Low density parity check code (Low Density Parity Check, LDPC) decoding algorithm is that channel information is at check-node (Check Node, CN) with variable node (Variable Node, VN) between the process of interative computation.
First, channel information passes to variable node and initializes, and the more newly obtained variable node of variable node is transferred to the information of check-node, passes to check-node, check-node more newly obtained C2V information, then passes to variable node.In iterative process, when check-node checking decoding result is correct, or when reaching maximum iteration time, result output will be decoded, complete once to decode.
At present, general ldpc decoder is mainly by check-node arithmetic element (Check Node computing Unit, CNU) module, variable node arithmetic element (Variable Node computing Unit, VNU) the part composition such as module and storage medium (described storage medium is usually EXCHANGE_RAM, is transferred to the information of check-node for storing C2V and variable node).
CNU, as the decoding operation module of most critical, occupies the logical resource that proportion is the highest, and the logical AND storage resource that directly affects other modules uses.Meanwhile, it, as the place part of critical path in general decoder, directly determines the maximum operation frequency of decoder, affects final handling capacity.
As shown in Figure 1, variable node is transferred to the information input data as CNU unit of check-node, first have to through comparison circuit, try to achieve minima min0 therein and sub-minimum min1, then, enter one and cut down submodule, reduce described min0 and the value of described min1, obtain min0-q and min1-q, pass as C2V information according to algorithmic rule afterwards.In the prior art, described for mlultiplying circuit, generally min0 and min1 is multiplied by one and cuts down coefficient, the spilling in subsequent process circuit.
In CNU unit, comparison circuit part is as the arithmetic element of most critical, and its function is that all of input data (C2V information) are tried to achieve minima and sub-minimum, and returns the port position of minima.This part needs to consume most logical resource, and in general can become critical path place.And how under ensureing the requirement that performance loss is less, the logical resource reducing this partial arithmetic uses as far as possible, shorten critical path, just become major issue during design decoder.
In some existing design of encoder, compare one by one for the data of serial input and draw minima and sub-minimum, carry out tree-shaped comparison with the data for parallel input, do not recall, show that minima intends sub-minimum with one, be all reasonable solution.But both schemes are in order to obtain sub-minimum, the former each input data are required for carrying out twice comparison operation with existing temporary value, each input data of the latter even need to compare more frequently with multiple data, and this resource usage amount taking in the decoder that CNU is larger is the most considerable.
It addition, during decoding iteration, the appearance of the error diffusion phenomenon produced to prevent from being overflowed by data accumulation, need to take advantage of to cut down a coefficient on minima with sub-minimum, they are cut down in proportion.But multiplication needs to have more considerable logical resource than computings such as additions in digital circuit can be realized, and needs within hardware to avoid as far as possible.Even and if have such measure, the constantly cumulative spilling that can still result in of some numbers through cutting down occurs.Typically in order to prevent from overflowing, designer can reserve enough width for data.But, the storage resource of decoder and the logical resource of each arithmetic element are all more sensitive to data width ratio, for the CNU unit at critical path place and the EXCHANGE_RAM of all side informations of storage, the data transmitted between module often reduce by a bit, and storage resource and logical resource that they take all can greatly reduce.
Summary of the invention
In view of this, embodiment of the present invention expectation provides check-node arithmetic element, check-node, storage device and the information processing method that a kind of difference is conventional.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that:
Embodiment of the present invention first aspect provides a kind of check-node arithmetic element, including:
Comparison module, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
Based on such scheme, described mapping ruler includes the first mapping ruler；
Described mapping block, including:
First mapping submodule, is connected with described comparison module, under described first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Cutting down submodule, be at least connected with described first mapping submodule, processing for respectively described minima and described sub-minimum being done reduction, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Based on such scheme, described first mapping submodule, including:
First lookup table circuit, for described minima for foundation of tabling look-up, sub-minimum table is preset in inquiry, it is thus achieved that described sub-minimum.
Based on such scheme, described mapping ruler also includes the second mapping ruler；
Described reduction submodule, the reduction value meeting described second mapping ruler specifically for lookup and described minima meets the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
Based on such scheme, described second mapping ruler includes that minima cuts down rule and sub-minimum cuts down rule；
Described reduction submodule includes:
Cut down lookup table circuit, minima after inquiry and described minima in the first reduction value table meet the described reduction of described minima reduction rule, in the second reduction value table, inquiry and described sub-minimum meet the sub-minimum after described sub-minimum cuts down regular described reduction.
Based on such scheme, described mapping ruler includes the second mapping ruler；
Described comparison module, is additionally operable to by comparing the sub-minimum that the described variable node of acquisition is transferred in the information of check-node；
Described mapping block, the reduction value meeting the second mapping ruler for lookup and described minima meets the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
Based on such scheme, mapping block includes:
Second lookup table circuit, for described minima for foundation of tabling look-up, inquires about the 3rd reduction value table preset, it is thus achieved that the minima after described reduction and the sub-minimum after reduction.
Embodiment of the present invention second aspect provides a kind of check-node, including the check-node arithmetic element described in any of the above-described item.
The embodiment of the present invention third aspect provides a kind of storage device, including storage medium and controller,
Described controller, for by comparing the minima that acquisition variable node is transferred in the information of check-node；According to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
Based on such scheme, described mapping ruler includes the first mapping ruler；
Described controller, specifically under described first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；Described minima and described sub-minimum are done reduction respectively process, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Based on such scheme, described mapping ruler also includes the second mapping ruler；
Described controller, it is additionally operable to by comparing the minima that the described variable node of acquisition is transferred in the information of check-node, and meet the reduction value of the second mapping ruler as the minima after described reduction specifically for searching with described minima, search and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction with described sub-minimum.
Based on such scheme, described controller, specifically with described minima for foundation of tabling look-up, the 3rd reduction value table that inquiry is preset, it is thus achieved that the minima after described reduction and the sub-minimum after reduction.
Embodiment of the present invention fourth aspect provides a kind of information processing method, including:
The minima that variable node is transferred in the information of check-node is obtained by comparing；
According to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
Based on such scheme, described mapping ruler includes the first mapping ruler；
Described according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum, including:
Under the first mapping ruler, obtain the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Described minima and described sub-minimum are done reduction respectively process, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Based on such scheme, described under the first mapping ruler, obtain the value the most corresponding with described minimum, including:
With described minima for foundation of tabling look-up, the described sub-minimum meeting described first mapping ruler in sub-minimum table with described minima is preset in inquiry.
Based on such scheme, described mapping ruler also includes the second mapping ruler；
Described respectively described minima and described sub-minimum are done reduction process, it is thus achieved that the minima after reduction and cut down after sub-minimum, including:
Lookup and described minima meet the reduction value of the second mapping ruler and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
Based on such scheme, described second mapping ruler includes that minima cuts down rule and sub-minimum cuts down rule；
Described lookup and described minima meet the reduction value of the second mapping ruler as the minima after described reduction, including:
In the first reduction value table, inquiry and described minima meet the minima after described minima cuts down regular described reduction；
Described lookup and described sub-minimum meet the reduction value of described second mapping ruler as the sub-minimum after described reduction, including:
In the second reduction value table, inquiry and described sub-minimum meet the sub-minimum after described sub-minimum cuts down regular described reduction.
Based on such scheme, described mapping ruler includes the second mapping ruler；
Described method also includes:
The sub-minimum that variable node is transferred in the information of check-node is obtained by comparing；
Described according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum, including:
Lookup and described minima meet the reduction value of the second mapping ruler and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
Based on such scheme, described according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum, including:
With described minima for foundation of tabling look-up, the 3rd reduction value table that inquiry is preset, it is thus achieved that the minima after described reduction and the sub-minimum after reduction.
A kind of check-node arithmetic element that the embodiment of the present invention provides, check-node, storage device and information processing method, the mapping block that check-node arithmetic element includes, mapping block is for determining the minima after reduction or sub-minimum according to mapping ruler and minima, relative to the sub-minimum after obtaining the minima after reduction by the comparison of comparison circuit and the multiplication process of mlultiplying circuit and cut down in prior art, have and realize structure difference, and at least substitute more comparison process and/or multiplication process with relatively simple mapping process, can simplified operation structure, promote operation efficiency.
Accompanying drawing explanation
Fig. 1 is the structural representation of the arithmetic element of a kind of existing check-node；
The structural representation of the first check-node arithmetic element that Fig. 2 provides for the embodiment of the present invention；
The structural representation of the second check-node arithmetic element that Fig. 3 A provides for the embodiment of the present invention；
The structural representation of the third check-node arithmetic element that Fig. 3 B provides for the embodiment of the present invention；
The structural representation of the 4th kind of check-node arithmetic element that Fig. 4 provides for the embodiment of the present invention；
The structural representation of the 5th kind of check-node arithmetic element that Fig. 5 provides for the embodiment of the present invention；
The structural representation of the storage device that Fig. 6 provides for the embodiment of the present invention；
The structural representation of a kind of information processing method that Fig. 7 provides for the embodiment of the present invention；
The schematic flow sheet of the another kind of information processing method that Fig. 8 provides for the embodiment of the present invention；
The acquisition structural representation of a kind of sub-minimum that Fig. 9 provides for the embodiment of the present invention；
A kind of reduction structural representation that Figure 10 provides for the embodiment of the present invention；
The structural representation of the 6th kind of check-node arithmetic element that Figure 11 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with Figure of description and specific embodiment, technical scheme is further elaborated.
Embodiment one:
As in figure 2 it is shown, the embodiment of the present invention provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block 120, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
Comparison module 110 described in the present embodiment may correspond to comparison circuit or has the process chip of comparing function.Described process chip can be that digital processing chip, programmable array chip or application process chip etc..Described comparison circuit or process chip, the most only by comparing the minima that acquisition variable node is transferred in the information of check-node.The information that variable node can be transferred to check-node in the present embodiment is referred to as V2C information.Described V2C information can include the generation noise information during decoding and/or error code information etc..
The most described comparison module 110 can determine the minima in V2C information by comparing.Noticeable comparison circuit herein or have the outfan processing chip of comparing function, is all connected with described mapping block 120, and this outfan is at least for exporting minima to mapping block 120.Described mapping block 120 in the present embodiment may correspond to the processor of the number of encapsulation or processes chip etc., it is also possible to corresponding to unencapsulated process circuit.Here process circuit can include special IC etc..
During concrete implementation, in V2C information, minima and sub-minimum generally have certain rule, the most described first mapping ruler to be the information reflecting described rule.Such as, when minima is a, usual sub-minimum is b, and the span of b is to have certain limit during decoding.And the minima after minima and reduction meets certain corresponding relation, sub-minimum with cut down after sub-minimum also meet certain corresponding relation.Therefore the most described mapping block, the sub-minimum after the minima after above-mentioned reduction can being utilized according to minima and cut down.
Like this, the check-node arithmetic element in the present embodiment, it is provided that a kind of new check-node arithmetic element, the arithmetic element of the sub-minimum after can having the easy minima obtained after cutting down equally and cutting down.
Embodiment two:
As in figure 2 it is shown, the embodiment of the present invention provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block 120, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
Described mapping ruler includes the first mapping ruler；As shown in Fig. 3 A or Fig. 3 B, mapping block 120 described in the present embodiment includes:
First mapping submodule 121, is connected with described comparison module 110, under the first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Cutting down submodule 122, be at least connected with described first mapping submodule 121, processing for respectively described minima and described sub-minimum being done reduction, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
As the minima in the V2C information that embodiment one is mentioned and sub-minimum have certain corresponding relation, the first mapping submodule 121 utilizes this corresponding relation between minima and sub-minimum in the present embodiment, obtains sub-minimum.Such as, the statistical value of the sub-minimum corresponding with this minima it is probably by the sub-minimum obtained of tabling look-up, the not true sub-minimum in this V2C information, but differ less with this true sub-minimum time due to this statistical value major part, and the degree of accuracy impact on calculating is the least.
The present embodiment provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
In the present embodiment when determining sub-minimum, no longer use comparison circuit to obtain by comparing, but determined by the first mapping submodule 121 being connected with comparison module 110.The most described first mapping submodule 121 can calculate described sub-minimum according to preset function relation, it is also possible to by the described sub-minimum of acquisition of tabling look-up.In a word, utilize the first mapping submodule 121 to substitute comparison module 110 in the present embodiment and compare the operation determining described sub-minimum.Relative to there being the check-node arithmetic element of two comparison modules 110, decrease a comparison module；Relative to only with a comparison module 110 by comparing the sub-minimum check-node arithmetic element of acquisition, it is possible to reduce number of comparisons, promote treatment effeciency.
Described first mapping submodule 121 in the present embodiment may correspond to the processor of the number of encapsulation or processes chip etc., it is also possible to corresponding to unencapsulated process circuit.Here process circuit can include special IC etc..
Described reduction submodule 130 is at least connected with the first mapping submodule 121 can include following two method:
The first scheme: as shown in Figure 3 B, described reduction submodule 130 is connected with described first mapping submodule 121 and described comparison module 110 respectively, by the connection with comparison module 110, receives described minima, by the connection with described first mapping submodule 121, receive described sub-minimum.
First scheme: as shown in Figure 3A, described reduction submodule 130 is only connected with described first mapping submodule 121, described first mapping submodule, the minima simultaneously received from comparison module 110, the sub-minimum determined with self, is transferred to described reduction submodule 130 respectively.
During concrete implementation, in V2C information, minima and sub-minimum generally have certain rule, the most described first mapping ruler to be the information reflecting described rule.Such as, when minima is a, usual sub-minimum is b, and the span of b is to have certain limit during decoding.Utilize this corresponding relation between minima and sub-minimum in the present embodiment, obtain sub-minimum.Such as, the statistical value of the sub-minimum corresponding with this minima it is probably by the sub-minimum obtained of tabling look-up, the not true sub-minimum in this V2C information, but differ less with this true sub-minimum time due to this statistical value major part, and the degree of accuracy impact on calculating is the least.
In the present embodiment, utilize the first mapping submodule to determine sub-minimum, it is provided that a kind of structure being different from existing check-node arithmetic element, there is efficiency height or the feature of simple in construction.
Embodiment three:
As in figure 2 it is shown, the embodiment of the present invention provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block 120, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
Described mapping ruler includes the first mapping ruler.As shown in Fig. 3 A or Fig. 3 B, mapping block 120 described in the present embodiment includes:
First mapping submodule 121, is connected with described comparison module 110, under the first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Cutting down submodule 122, be at least connected with described first mapping submodule 121, processing for respectively described minima and described sub-minimum being done reduction, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Described first mapping submodule 121, including: sub-minimum mapping look-up of table circuit, for described minima for foundation of tabling look-up, sub-minimum table is preset in inquiry, it is thus achieved that described sub-minimum.
The most described first mapping submodule 121 includes sub-minimum lookup table circuit, described sub-minimum lookup table circuit can include storage medium, disclosure satisfy that minima and the sub-minimum of described first mapping ruler, described sub-minimum lookup table circuit is by the connection with the comparison circuit in comparison module 110 or the process chip with comparing function, receive described minima, with described minima for foundation of tabling look-up, such as, with described minima as lookup table index, search the default sub-minimum table being stored in storage medium, it is thus achieved that described sub-minimum.
Such as, by decoder or the performance simulation of check-node or data statistics, if count that in V2C information, minima is a, sub-minimum may be b；Corresponding in described default sub-minimum table can store described a and described b in the present embodiment；If the minima of comparison module 110 output is a, i.e. with a as lookup table index, find b；B is considered as the sub-minimum of described V2C information.In this time, the minima that sub-minimum mapping look-up of table circuit determines can be the true sub-minimum in described V2C information, it is also possible to be not equal to the true sub-minimum in described V2C information, but close to a value of this true sub-minimum.The most described sub-minimum, thus literal meaning understands be only big than minima value, and minima is the minima in V2C information.Minima and the corresponding relation of sub-minimum in the most described sub-minimum lookup table circuit, be to be emulated by decoding or value that data statistics determines, can be to be set in advance in described arithmetic element.
The circuit of sub-minimum mapping look-up of table described in the present embodiment, relative to comparison module 110 by comparing acquisition sub-minimum, has simple in construction and sub-minimum determines the feature that efficiency is high.
Embodiment four:
As in figure 2 it is shown, the embodiment of the present invention provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block 120, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
Described mapping ruler includes the first mapping ruler.As shown in Figure 3 A and Figure 3 B, mapping block 120 described in the present embodiment includes:
First mapping submodule 121, is connected with described comparison module 110, under the first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Cutting down submodule 122, be at least connected with described first mapping submodule 121, processing for respectively described minima and described sub-minimum being done reduction, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Described mapping ruler also includes the second mapping ruler, described reduction submodule 130, the reduction value meeting the second mapping ruler specifically for lookup and described minima meets the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
Minima after generally cutting down is less than minima；Sub-minimum after reduction is less than sub-minimum, is processed by reduction, is possible to prevent to overflow.
The most described reduction submodule 122, by the way of lookup, cuts down minima and sub-minimum.Such as, described reduction submodule 122 can search the reduction value of correspondence in default cutting down in form, thus obtains the minima after described reduction and the sub-minimum after reduction.Use this lookup mode to carry out the reduction of minima and sub-minimum, it is possible to avoid using multiplier to cut down by minima and sub-minimum are multiplied by a reduction coefficient less than 1.
Reduction submodule 122 is set to lookup result by the present embodiment, and structure is simpler relative to multiplier.
As further improvement of this embodiment, described second mapping ruler includes that minima cuts down rule and sub-minimum cuts down rule；Described reduction submodule 122 includes: cut down lookup table circuit, minima after inquiry and described minima in the first reduction value table meet the described reduction of described minima reduction rule, in the second reduction value table, inquiry and described sub-minimum meet the sub-minimum after described sub-minimum cuts down regular described reduction.
The most described minima cuts down rule and sub-minimum cuts down rule, likely corresponds to different reduction coefficients.Such as, the minima reduction coefficient when cutting down may be for a1, and the sub-minimum reduction coefficient when cutting down may be for b1；A1 with b1 may be identical, it is also possible to different.If a1 is equal to b1, then minima is consistent with the reduction ratio of sub-minimum, if a1 is not equal to b1, the ratio of reduction is inconsistent.
In the present embodiment, described reduction submodule 122 will be used for being processed by the lookup such as table look-up, it is thus achieved that the minima after described reduction and the sub-minimum after cutting down, and have that realization is easy and the feature of simple in construction.
Embodiment five:
As in figure 2 it is shown, the embodiment of the present invention provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block 120, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
As shown in Figure 4, described mapping block 120 includes:
Second lookup table circuit, for described minima for foundation of tabling look-up, inquires about the 3rd reduction value table preset, it is thus achieved that the minima after described reduction and the sub-minimum after reduction.
The most described mapping block 120 includes the second lookup table circuit, stores the 3rd reduction value table in described second lookup table circuit, the minima after directly storage has minima, reduction in the 3rd reduction value table and the corresponding relation of the sub-minimum three after reduction.
Utilize the method in embodiment two to embodiment four, corresponding relation is had between minima and sub-minimum, minima after reduction and the minima after reduction, sub-minimum after reduction and sub-minimum have corresponding relation, above-mentioned relation will be passed through in the present embodiment, extracting directly goes out the corresponding relation of the sub-minimum after minima and reduction, like this, the sub-minimum after just can directly being found out the minima after reduction by a lookup table circuit and be cut down.Thus greatly simplified structure, decrease the number of times tabled look-up simultaneously, improve treatment effeciency.
It is below an example of the 3rd reduction value table described in the present embodiment:
| Minima | Minima after reduction | Sub-minimum after reduction |
| A | A1 | A2 |
| B | B1 | B2 |
| … | … | … |
Obviously by the inquiry of above table, the sub-minimum after obtaining the minima after cutting down and cutting down can directly be inquired about with minima as foundation.When designing described check-node arithmetic element, sub-minimum can be obtained according to minima according to performance simulation and empirical statistics, then by the no-spill reduction of minima and sub-minimum process obtain described reduction after minima and sub-minimum after cutting down；Finally remove this intermediate quantity of sub-minimum, extract the corresponding relation of three in above-mentioned table, form described check-node arithmetic element, thus can be only by once tabling look-up the sub-minimum after obtaining the minima after cutting down and cutting down simultaneously, comparison circuit is simplified relative to prior art, eliminate mlultiplying circuit, greatly simplify the arithmetic element of check-node, improve treatment effeciency simultaneously.
Embodiment six:
As it is shown in figure 5, the embodiment of the present invention provides a kind of check-node arithmetic element, including:
Comparison module 110, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block 120, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
Described comparison module 110, is additionally operable to by comparing the sub-minimum that the described variable node of acquisition is transferred in the information of check-node；
Described mapping ruler includes the second mapping ruler；Described comparison module 110, is additionally operable to by comparing the minima that the described variable node of acquisition is transferred in the information of check-node；Described mapping block 120, the reduction value meeting the second mapping ruler for lookup and described minima meets the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
The most described comparison module 110 is additionally operable to by comparing acquisition sub-minimum.The most described comparison module 110 can include two comparison circuits, one comparison circuit is for by comparing acquisition minima, another comparison circuit is for by comparing acquisition minima, it is also possible to only includes a comparison circuit, only relatively obtains minima and sub-minimum by recycle ratio.
Described map unit 120 is according to the second mapping ruler, based on minima and sub-minimum, the sub-minimum after obtaining the minima after described reduction in the way of tabling look-up and cutting down.
Use multiplicative operator to carry out minima and the check-node arithmetic element of sub-minimum reduction in relatively, there is simple in construction and realize easy feature.
Embodiment seven:
The present embodiment provides a kind of check-node, and this check-node includes that previous embodiment is arbitrarily to described check-node arithmetic element.
Use above-mentioned check-node arithmetic element to carry out the conversion to C2V information of the V2C information, there is simple in construction, realize easy and that efficiency is high feature.
Embodiment eight:
As shown in Figure 6, the present embodiment provides a kind of storage device, including storage medium 210 and controller 220,
Described controller, for according to mapping ruler and described minima, obtaining the minima after cutting down or sub-minimum.
The most described storage medium is connected with described controller, it is possible to be used for storing various data message.
Described storage medium in the present embodiment can be various types of storage medium, such as, CD, disk or portable hard drive etc..
The most described controller can obtain, by comparing, the minima that variable node is transferred in the information of check-node；According to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.Described controller 220 may correspond to various processor, such as, central processing unit, microprocessor, digital signal processor or programmable array etc..Described controller 220 also corresponds to process circuit, and described process circuit can include special IC.Described controller 220 by perform predetermined code can complete aforementioned can all operations performed by check-node arithmetic element.
Storage medium described in the present embodiment, can be used for storing in described executable code, V2C information and C2V information is one or more.
Aforementioned mapping ruler can include the first mapping ruler and the second mapping ruler；Hereinafter compare previous embodiment, it is provided that the concrete structure of several described controllers:
The first: described controller 220, specifically under described first mapping ruler, obtain the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；Described minima and described sub-minimum are done reduction respectively process, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
The most described first mapping ruler also can make mapping function etc., and described controller 220 also can obtain described sub-minimum according to the calculating beyond tabling look-up.
Further improvement as this kind of mode, described controller 220 can be additionally used in search and meets the reduction value of described second mapping ruler as the minima after described reduction with described minima, searches and meets the reduction value of described second mapping ruler as the sub-minimum after described reduction with described sub-minimum.The mode that so utilization is searched obtains the minima after reduction and the sub-minimum after reduction, it is possible to avoid using this complexity of multiplier computation at the uniform velocity, direct by tabling look-up the minima after being obtained with described reduction and sub-minimum.
The most such as, described controller 220 meets the minima after the described reduction of described minima reduction rule specifically for inquiry and described minima in the first reduction value table, and in the second reduction value table, inquiry and described sub-minimum meet the sub-minimum after described sub-minimum cuts down regular described reduction.
The second:
Described controller 220, specifically with described minima for foundation of tabling look-up, the 3rd reduction value table that inquiry is preset, it is thus achieved that the minima after described reduction and the sub-minimum after reduction.Minima that what the 3rd reduction value table was directly set up in the present embodiment is, cut down after minima and the corresponding relation of sub-minimum after cutting down, comparison circuit is the most only needed to compare minima, directly with minima as lookup table index, sub-minimum after just can directly finding out the minima after reduction and cutting down, simplifies the operation of controller and improves treatment effeciency.
The third:
Described controller 220, it is additionally operable to by comparing the minima that the described variable node of acquisition is transferred in the information of check-node, and meet the reduction value of the second mapping ruler as the minima after described reduction specifically for searching with described minima, search and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction with described sub-minimum.
In this kind of mode, described controller 220 by comparing acquisition minima, more respectively according to minima and sub-minimum, can carry out reduction process in the way of tabling look-up, it is possible to the minima after the reduction of simple and efficient acquisition and the sub-minimum after reduction.
In a word, what the storage device of the present embodiment offer can be simple and efficient obtains the minima after cutting down and sub-minimum.
Embodiment nine:
As it is shown in fig. 7, the present embodiment provides a kind of information processing method, including:
Step S110: obtain the minima that variable node is transferred in the information of check-node by comparing；
Step S120: according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
At the information processing method that the present embodiment provides, can be the western Sydney processing method being applied in check-node arithmetic element or check-node, comparison process can be passed through in step s 110, it is thus achieved that the minima in V2C information.
In the step s 120 will be according to mapping ruler and minima, sub-minimum after obtaining the minima after reduction or cutting down, relative to existing by comparing acquisition sub-minimum, the sub-minimum after obtaining the minima after cutting down by multiplying or cut down, have and realize simple and efficient feature.
Embodiment ten:
As it is shown in fig. 7, the present embodiment provides a kind of information processing method, including:
Step S110: obtain the minima that variable node is transferred in the information of check-node by comparing；
Step S120: according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
At the information processing method that the present embodiment provides, can be the western Sydney processing method being applied in check-node arithmetic element or check-node, comparison process can be passed through in step s 110, it is thus achieved that the minima in V2C information.
Described mapping ruler includes the first mapping ruler；
As shown in Figure 8, described step S110 comprises the steps that
Step S111: under the first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Step S112: respectively described minima and described sub-minimum are done reduction and processes, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
May utilize the first mapping ruler in the present embodiment, determine sub-minimum；The most respectively minima and sub-minimum are carried out reduction process, it is thus achieved that minima and sub-minimum, relative to prior art being passed through compare the method obtaining sub-minimum, it is possible to reduce number of comparisons, reduce because comparing the problem that the operand caused is big and arithmetic speed is slow in a large number.
Embodiment 11:
As it is shown in fig. 7, the present embodiment provides a kind of information processing method, including:
Step S110: obtain the minima that variable node is transferred in the information of check-node by comparing；
Step S120: according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
At the information processing method that the present embodiment provides, can be the information processing method being applied in check-node arithmetic element or check-node, comparison process can be passed through in step s 110, it is thus achieved that the minima in V2C information.
Described mapping ruler includes the first mapping ruler；
Described step S110 comprises the steps that
Step S111: under the first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Step S112: respectively described minima and described sub-minimum are done reduction and processes, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
It should be noted that the first mapping ruler useful functional relationship formula is expressed described in aforementioned the present embodiment, can occasionally utilize functional relation to calculate described sub-minimum.The most described step S111 includes:
With described minima for foundation of tabling look-up, the described sub-minimum meeting described first mapping ruler in sub-minimum table with described minima is preset in inquiry.
In the present embodiment in order to avoid the complexity of functional operation, mode utilization tabled look-up in the present embodiment is to obtain described sub-minimum, and further simplification processes, and promotes treatment effeciency.
Embodiment 12:
As it is shown in fig. 7, the present embodiment provides a kind of information processing method, including:
Step S110: obtain the minima that variable node is transferred in the information of check-node by comparing；
Step S120: according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
At the information processing method that the present embodiment provides, can be the information processing method being applied in check-node arithmetic element or check-node, comparison process can be passed through in step s 110, it is thus achieved that the minima in V2C information.
Described mapping ruler includes the first mapping ruler；
Described step S110 comprises the steps that
Step S111: under the first mapping ruler, obtains the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Step S112: respectively described minima and described sub-minimum are done reduction and processes, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Described mapping ruler also includes the second mapping ruler.
Described step S112 comprises the steps that
Lookup and described minima meet the reduction value of the second mapping ruler and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
In the present embodiment in order to reduce multiplying, mapping table can be utilized in the present embodiment to process minima and sub-minimum and to carry out reduction process, thus by mapping the sub-minimum obtained after cutting down.
As further improvement of this embodiment, described second mapping ruler includes that minima cuts down rule and sub-minimum cuts down rule；Described step S112 includes: in the first reduction value table, inquiry and described minima meet the minima after described minima cuts down regular described reduction；In the second reduction value table, inquiry and described sub-minimum meet the sub-minimum after described sub-minimum cuts down regular described reduction.
Sub-minimum after searching the minima after cutting down in different reduction value tables and cutting down, has that realization is easy and feature efficiently.
Embodiment 13:
As it is shown in fig. 7, the present embodiment provides a kind of information processing method, including:
Step S110: obtain the minima that variable node is transferred in the information of check-node by comparing；
Step S120: according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
At the information processing method that the present embodiment provides, can be the information processing method being applied in check-node arithmetic element or check-node, comparison process can be passed through in step s 110, it is thus achieved that the minima in V2C information.
Described step S120 comprises the steps that
With described minima for foundation of tabling look-up, the 3rd reduction value table that inquiry is preset, it is thus achieved that the minima after described reduction and the sub-minimum after reduction.
The most only include a 3rd reduction value table, with minima for foundation of tabling look-up, sub-minimum after directly finding out the minima after reduction and cutting down, obviously a retrieval of tabling look-up the most only is needed, carry out the sub-minimum the two value after a table lookup operation is obtained with the minima after cutting down and cuts down, there is realization simplicity, the feature that processing speed is high.
Embodiment 14:
As it is shown in fig. 7, the present embodiment provides a kind of information processing method, including:
Step S110: obtain the minima that variable node is transferred in the information of check-node by comparing；
Step S120: according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
At the information processing method that the present embodiment provides, can be the information processing method being applied in check-node arithmetic element or check-node, comparison process can be passed through in step s 110, it is thus achieved that the minima in V2C information.
Described method also includes:
The sub-minimum that variable node is transferred in the information of check-node is obtained by comparing；
Described step S120 comprises the steps that
Lookup and described minima meet the reduction value of the second mapping ruler and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction as the minima after described reduction, lookup and described sub-minimum.
Also need to by comparing the sub-minimum obtained in V2C information in the present embodiment, the most described method will directly utilize the second mapping ruler, the minima after cutting down is searched based on minima, the sub-minimum after cutting down is searched based on sub-minimum, sub-minimum after obtaining the minima after cutting down relative to utilizing multiplying and cut down, has and realizes easy and fireballing feature.
Below in conjunction with above-mentioned any embodiment one concrete example of offer:
As it is shown in figure 9, this example provides a kind of operating structure obtaining sub-minimum, including:
V2C message buffer, is used for caching V2C information；
Amount input comparator, for by comparing minima min0 asked in V2C information；
Min0 buffer, is used for caching min0,
Mapping block, for according to min0, determines sub-minimum min1.Wherein, meeting the first mapping ruler between min0 and sub-minimum min1, the most described first mapping ruler can be used for F () and represents.
Utilize this operating structure of this example, the comparison operation for trying to achieve sub-minimum can be avoided, thus avoid the comparison operation of more than the secondary to same data and secondary, in decoder CNU, comparison circuit structure is greatly simplified, eliminate at least half of comparison operation, decrease considerable logical resource usage amount.
As shown in Figure 10, the reduction structure during this example provides a kind of check-node arithmetic element.This little sword structure replaces multiplying with nonlinear mapping.By to the information quantization of transmission, amplitude limit etc. in iteration, the bit wide of the data of different piece being determined, and limits numerical range, the C2V information calculated through CNU be just also defined in a range of some worthwhile suffer.Next should be during the reduction in proportion to information carried out by multiplication is calculated, it is replaced with the nonlinear mapping of lookup table mode, first benefit is that of avoiding in hardware the complicated multiplying being not intended to see, next is result to be limited in the scope estimated, it is strictly on guard against that the data produced by CNU computing are overflowed, reduce data width, reduce logic and storage resource uses.
Before hardware designs, first have to determine suitable minima min0 Function Mapping rule F () to sub-minimum min1 by decoding performance emulation, cut down mapping ruler q () with the amplitude of minima min0 with sub-minimum min1, then start to build hardware circuit.
The storage that min0 ' and min ' represents in Fig. 10 is available for the minima after the reduction of inquiry and fourth finger；Min0-q represents the minima after the reduction that eventually passing through tables look-up obtains；Sub-minimum after the reduction obtained of tabling look-up that what min1-q represented eventually pass through.
Finally, in conjunction with the structure shown in Fig. 9 and Figure 10, the structure shown in Figure 11 is obtained, V2C information passes to CNU, inputs the simplified comparison circuit only asking for minima, exports minima min0, pass to sub-minimum mapping look-up of table circuit F (), obtain sub-minimum output min1.Then minima min0 is cut down lookup table circuit q () with sub-minimum min1 input amplitude, obtain value min0_q in restriction scope and min1_q, become the amplitude of the new C2V information finally distributing to each port.
In several embodiments provided herein, it should be understood that disclosed equipment and method, can realize by another way.Apparatus embodiments described above is only schematically, such as, the division of described unit, it is only a kind of logic function to divide, actual can have other dividing mode, such as when realizing: multiple unit or assembly can be in conjunction with, or are desirably integrated into another system, or some features can ignore, or do not perform.It addition, the coupling each other of shown or discussed each ingredient or direct-coupling or communication connection can be the INDIRECT COUPLING by some interfaces, equipment or unit or communication connection, can be being electrical, machinery or other form.
The above-mentioned unit illustrated as separating component can be or may not be physically separate, and the parts shown as unit can be or may not be physical location, i.e. may be located at a place, it is also possible to be distributed on multiple NE；Part or all of unit therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.
It addition, each functional unit in various embodiments of the present invention can be fully integrated in a processing module, it is also possible to be that each unit is individually as a unit, it is also possible to two or more unit are integrated in a unit；Above-mentioned integrated unit both can realize to use the form of hardware, it would however also be possible to employ hardware adds the form of SFU software functional unit and realizes.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program upon execution, performs to include the step of said method embodiment；And aforesaid storage medium includes: movable storage device, read only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), the various media that can store program code such as magnetic disc or CD.
The above; being only the detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; change can be readily occurred in or replace, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (19)
1. a check-node arithmetic element, including:
Comparison module, for by comparing the minima that acquisition variable node is transferred in the information of check-node；
Mapping block, for according to mapping ruler and described minima, obtaining the minima or secondary little after cutting down
Value.
Check-node arithmetic element the most according to claim 1, including:
Described mapping ruler includes the first mapping ruler；
Described mapping block, including:
First mapping submodule, is connected with described comparison module, under described first mapping ruler, obtains
Take the value the most corresponding with described minimum；Wherein, the value that described and described minima is corresponding is i.e. considered as described variable
Node-node transmission is to the sub-minimum in the information of check-node；
Cut down submodule, is at least connected with described first mapping submodule, for respectively to described minima with
Described sub-minimum does reduction and processes, it is thus achieved that the minima after reduction and the sub-minimum after reduction.
Check-node arithmetic element the most according to claim 2, it is characterised in that
Described first mapping submodule, including:
First lookup table circuit, for described minima for foundation of tabling look-up, sub-minimum table is preset in inquiry, it is thus achieved that
Described sub-minimum.
4. require the check-node arithmetic element described in 2 according to claim, it is characterised in that
Described mapping ruler also includes the second mapping ruler；
Described reduction submodule, meets cutting of described second mapping ruler specifically for searching with described minima
Depreciation, as the minima after described reduction, is searched and is met cutting of described second mapping ruler with described sub-minimum
Depreciation is as the sub-minimum after described reduction.
Check-node arithmetic element the most according to claim 2, it is characterised in that
Described second mapping ruler includes that minima cuts down rule and sub-minimum cuts down rule；
Described reduction submodule includes:
Cut down lookup table circuit, meet described minima for inquiry and described minima in the first reduction value table
Cutting down the minima after the described reduction of rule, in the second reduction value table, inquiry and described sub-minimum meet institute
State the sub-minimum after sub-minimum cuts down regular described reduction.
Check-node arithmetic element the most according to claim 1, it is characterised in that
Described mapping ruler includes the second mapping ruler；
Described comparison module, is additionally operable to be transferred to the information of check-node by comparing the described variable node of acquisition
In sub-minimum；
Described mapping block, meets the reduction value of the second mapping ruler as institute for searching with described minima
State the minima after reduction, search and meet the reduction value of described second mapping ruler as institute with described sub-minimum
State the sub-minimum after reduction.
Check-node arithmetic element the most according to claim 1, it is characterised in that
Mapping block includes:
Second lookup table circuit, for described minima for foundation of tabling look-up, inquires about the 3rd reduction value table preset,
Sub-minimum after obtaining the minima after described reduction and cutting down.
8. a check-node, it is characterised in that include the verification joint described in any one of claim 1 to 5
Point processing unit.
9. a storage device, it is characterised in that include storage medium and controller,
Described controller, for by comparing the minimum that acquisition variable node is transferred in the information of check-node
Value；According to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
Storage device the most according to claim 9, it is characterised in that
Described mapping ruler includes the first mapping ruler；
Described controller, specifically under described first mapping ruler, obtains the most corresponding with described minimum
Value；Wherein, the value that described and described minima is corresponding is i.e. considered as described variable node and is transferred to check-node
Sub-minimum in information；Described minima and described sub-minimum are done reduction respectively process, it is thus achieved that after reduction
Sub-minimum after minima and reduction.
11. storage devices according to claim 9, it is characterised in that
Described mapping ruler also includes the second mapping ruler；
Described controller, be additionally operable to by compare acquisition described variable node be transferred in the information of check-node
Minima, and specifically for search meet the reduction value of the second mapping ruler as described with described minima
Minima after reduction, searches and meets the reduction value of described second mapping ruler as described with described sub-minimum
Sub-minimum after reduction.
12. storage devices according to claim 9, it is characterised in that
Described controller, specifically with described minima for foundation of tabling look-up, the 3rd reduction value table that inquiry is preset,
Sub-minimum after obtaining the minima after described reduction and cutting down.
13. 1 kinds of information processing methods, including:
The minima that variable node is transferred in the information of check-node is obtained by comparing；
According to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum.
14. methods according to claim 12, it is characterised in that
Described mapping ruler includes the first mapping ruler；
Described according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum, including:
Under the first mapping ruler, obtain the value the most corresponding with described minimum；Wherein, described with described minimum
The value of value correspondence is i.e. considered as the sub-minimum that described variable node is transferred in the information of check-node；
Described minima and described sub-minimum are done reduction respectively process, it is thus achieved that the minima after reduction and reduction
After sub-minimum.
15. methods according to claim 14, it is characterised in that
Described under the first mapping ruler, obtain the value the most corresponding with described minimum, including:
With described minima for foundation of tabling look-up, inquiry is preset and is met described the in sub-minimum table with described minima
The described sub-minimum of one mapping ruler.
16. method according to claim 14, it is characterised in that
Described mapping ruler also includes the second mapping ruler；
Described respectively described minima and described sub-minimum are done reduction process, it is thus achieved that the minima after reduction and
Sub-minimum after reduction, including:
Search and meet the reduction value of the second mapping ruler as the minima after described reduction with described minima,
Search and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction with described sub-minimum.
17. methods according to claim 16, it is characterised in that
Described second mapping ruler includes that minima cuts down rule and sub-minimum cuts down rule；
Described lookup and described minima meet the reduction value of the second mapping ruler as the minimum after described reduction
Value, including:
In the first reduction value table, inquiry and described minima meet the described reduction of described minima reduction rule
After minima；
Described lookup and described sub-minimum meet the reduction value of described second mapping ruler as described reduction after
Sub-minimum, including:
In the second reduction value table, inquiry and described sub-minimum meet the described reduction of described sub-minimum reduction rule
After sub-minimum.
18. methods according to claim 13, it is characterised in that
Described mapping ruler includes the second mapping ruler；
Described method also includes:
The sub-minimum that variable node is transferred in the information of check-node is obtained by comparing；
Described according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum, including:
Search and meet the reduction value of the second mapping ruler as the minima after described reduction with described minima,
Search and meet the reduction value of described second mapping ruler as the sub-minimum after described reduction with described sub-minimum.
19. methods according to claim 13, it is characterised in that
Described according to mapping ruler and described minima, obtain the minima after cutting down or sub-minimum, including:
With described minima for foundation of tabling look-up, the 3rd reduction value table that inquiry is preset, it is thus achieved that after described reduction
Sub-minimum after minima and reduction.
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