CN108768161B

CN108768161B - Built-in compensation fixed conduction time circuit

Info

Publication number: CN108768161B
Application number: CN201810474528.0A
Authority: CN
Inventors: 毛锴; 曾明辉
Original assignee: Shenzhen Silandtech Electronic Technology Co ltd
Current assignee: Shenzhen Silandtech Electronic Technology Co ltd
Priority date: 2018-05-17
Filing date: 2018-05-17
Publication date: 2021-01-15
Anticipated expiration: 2038-05-17
Also published as: CN108768161A

Abstract

The invention discloses a built-in compensation fixed conduction time circuit, which comprises a current generation circuit module, a capacitance charge and discharge control module connected with the current generation circuit module, a comparator connected with the capacitance charge and discharge control module and a feedforward circuit module, wherein the current generation circuit module comprises an operational amplifier and a source electrode follower; the source follower comprises a MOS transistor M0, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a temperature compensation resistor R0; the capacitor charging and discharging control unit comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M7, a M8, a M9 and a M10, and the current of the current mirror copy current generating circuit module is controlled by a switching tube consisting of the seventh MOS tube M7 and the eighth MOS tube M8; the invention uses MOS tube and current mirror depending on matching precision to simulate traditional RC circuit, thereby improving integration level and reducing peripheral components and cost.

Description

Built-in compensation fixed conduction time circuit

Technical Field

The invention relates to the technical field of direct-current voltage converters, in particular to a built-in compensation fixed On Time (FCOT) circuit.

Background

The dc voltage converter (DCDC) can be divided into three structures according to the structural layout, namely a dc voltage converter capable of boosting (boost), a dc voltage converter capable of reducing (buck) and a dc voltage converter capable of outputting negative voltage (buck-boost). Each structure can be further classified into a Voltage type (Voltage Mode), a Peak Current type (Peak Current Mode), a Voltage Feedforward type (Voltage Mode with feedback), hysteresis (Hysteretic), a fixed On-Time (Constant On Time, abbreviated as COT), and the like according to a control Mode.

In the traditional fixed-time conducting circuit based on the RC, the generated pulse width depends on the product of the RC, the pulse width precision also depends on the precision of RC resistance and capacitance, most BCD (bipolar transistor-capacitor) processes in an integrated circuit do not support high-precision low-temperature drift resistance and capacitance, and the BCD processes are advanced monolithic integration process technologies and are used for manufacturing a bipolar device and a CMOS (complementary metal oxide semiconductor) device on the same chip. The bipolar transistor integrates the advantages of high transconductance and strong load driving capability of a bipolar device, high integration level of a CMOS (complementary metal oxide semiconductor) and low power consumption. Because most BCD processes do not support high-precision low-temperature floating resistor and capacitor, and a traditional RC circuit with low absolute precision (the error of RC product is more than plus or minus 40%) is not suitable for the BCD process of an integrated circuit, most DCDCDC in a COT control mode needs an external RC, the integration level is reduced, and peripheral components and cost are increased.

In view of the above-mentioned deficiencies in the prior art, it is necessary to develop and research a scheme for improving the external resistance and capacitance required based on the fixed on-time, and a conventional RC fixed on-time generating circuit is replaced by a fully integrated fixed on-time (FCOT) generating circuit, so as to improve the integration level and reduce the cost of peripheral components.

Disclosure of Invention

In order to solve the existing technical problems, embodiments of the present invention provide a fixed on-time circuit with built-in compensation to replace the conventional RC fixed on-time generation circuit, thereby improving the integration level and reducing the peripheral components and the cost.

In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:

a built-in compensation fixed conduction time circuit comprises a current generation circuit module, a capacitance charge and discharge control module connected with the current generation circuit module, a comparator connected with the capacitance charge and discharge control module and a feedforward circuit module, wherein the current generation circuit module comprises an operational amplifier and a source electrode follower; the source follower comprises a MOS transistor M0, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a temperature compensation resistor R0; the capacitor charging and discharging control unit comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M7, a M8, a M9 and a M10, and the current of the current mirror copy current generating circuit module is controlled by a switch tube formed by the seventh MOS tube M7 and the eighth MOS tube M8.

Preferably, the input of the operational amplifier is connected with a direct current level VREF input, and the output of the operational amplifier is respectively connected to the gate of the MOS transistor M0 and the gates of the first, second and third MOS transistors M1, M2 and M3; the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, and the source of the third MOS transistor M3 is connected to the temperature compensation resistor R0.

Preferably, the temperature compensation resistor R0 is a high-resistance polysilicon resistor with a negative temperature coefficient.

Preferably, the operational amplifier clamps the current to obtain a compensation current, and the compensation current is mirrored and supplied to the capacitor charge and discharge control module through the fourth and fifth MOS transistors M4 and M5.

Preferably, the comparator and feedforward circuit module comprises a comparator, first and second resistors R1 and R2 connected with the comparator, and a capacitor C0 connected in parallel with the second resistor R2.

The technical scheme provided by the embodiment of the invention has the beneficial effects that:

the invention uses MOS tube and current mirror depending on matching precision to simulate traditional RC circuit, abandons traditional RC circuit with low absolute precision in BCD technology (RC product error is more than plus or minus 40%), makes its dependence on absolute precision convert to dependence on matching precision, and most MOS tubes in BCD technology can achieve plus or minus 1% matching precision, at the same time, adds high resistance value polysilicon resistor (HR poly) or parasitic longitudinal P-type transistor (Varasitical Vertical PNP) with negative temperature coefficient to solve the temperature characteristic of MOS tube, to compensate its temperature characteristic, thus improving integration level, reducing peripheral components and cost.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a fixed on-time circuit with built-in compensation according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The built-in compensation fixed conduction time circuit uses an MOS tube and a current mirror which depend on matching precision to simulate a traditional RC circuit instead, the traditional RC circuit with low absolute precision in a BCD process is abandoned (the error of an RC product is more than plus or minus 40 percent), the dependence on the absolute precision is converted into the dependence on the matching precision, most MOS tubes in the BCD process can achieve the matching precision of plus or minus 1 percent, and meanwhile, a high-resistance polycrystalline silicon resistor (HR poly) with a negative temperature coefficient or a parasitic longitudinal P-type transistor (Varasitical Vertical PNP) is additionally added to solve the temperature characteristic of the MOS tubes so as to compensate the temperature characteristic of the MOS tubes.

Referring to fig. 1, the fixed on-time circuit with built-in compensation of the present invention includes a current generation circuit module, a capacitor charging and discharging control module connected to the current generation circuit module, and a comparator and a feedforward circuit module connected to the capacitor charging and discharging control module.

The current generation circuit module comprises an operational amplifier and a source electrode follower; the source follower comprises a MOS transistor M0, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a temperature compensation resistor R0. The input of the operational amplifier is connected with a direct current level VREF input, and the output of the operational amplifier is respectively connected with the grid electrode of the MOS tube M0 and the grid electrodes of the first, second and third MOS tubes M1, M2 and M3; the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, and the source of the third MOS transistor M3 is connected to the temperature compensation resistor R0. VREF is a stable direct current level, the voltage is clamped to the point A through an operational amplifier to obtain a compensation current, and the compensation current charges the capacitor through the capacitor charging and discharging control module. That is, a voltage at a point a is fixed and divided by the impedance formed by the first, second and third MOS transistors M1, M2 and M3 and the temperature compensation resistor R0 to obtain a current, which is mirrored and supplied to the capacitance charge/discharge control module through the fourth and fifth MOS transistors M4 and M5. In an embodiment of the invention, the temperature compensation resistor R0 is a polysilicon resistor with a negative temperature coefficient and a high resistance value. In the embodiment of the invention, the first, second and third MOS tubes are N-type MOS tubes.

The capacitor charging and discharging control unit comprises a sixth MOS tube M6, a seventh MOS tube M7, a ninth MOS tube M8, a tenth MOS tube M9 and a tenth MOS tube M10, wherein the gates of the sixth MOS tube M6 and the seventh MOS tube M7 are connected together. The current passing through the current mirror copy current generation circuit module is controlled by a switching tube composed of a seventh MOS transistor M7 and an eighth MOS transistor M8 to perform constant current discharge on the MOS capacitor of the tenth MOS transistor. The capacitor is charged by the ninth MOS transistor M9 directly conducting.

The comparator and feedforward circuit module comprises a comparator, a first resistor R1, a second resistor R2 and a capacitor C0, wherein the first resistor R1 and the second resistor R2 are connected with the comparator, and the capacitor C0 is connected with the second resistor R2 in parallel. The input voltage is filtered by the first and second resistors R1, the voltage division of R2 and the capacitor C0 and then connected to the negative terminal of the comparator, and the MOS capacitor of the tenth MOS transistor is connected to the positive terminal of the comparator. When the input voltage VIN changes, the pulse width output from the comparator end changes more. The comparator compares the voltage C point obtained by the feedforward circuit module with the charging and discharging current of the point B to obtain a pulse, and the pulse is output through an ON end.

Specifically, VREF dc level is clamped to a point a by an operational amplifier, assuming that R0=0, then the current flowing through the MOS transistor M0 is VREF voltage divided by the impedance of the first, second, and third MOS transistors, i.e., the impedance of M1+ M2+ M3, assuming that M1= M2= M3, and Vds is much smaller than Vgs-Vt, the MOS transistor operates in a linear region, and the small signal channel resistance Ron of the MOS transistor is:

wherein, the voltage of the point A is VREF, and the MOS tube MO works in a saturation region, neglecting the channel modulation effect, and obtaining the current formula of the MOS tube MO as follows

Since Vgsm1= VA + Vgsm0= VREF + Vgsm0, Vds = VREF

Therefore, it is not only easy to use

When the circuit works, S3_ is pulled down, the ninth MOS transistor M9 is switched on, S1 is pulled down, the eighth MOS transistor M8 is switched off, because the area of the ninth MOS transistor M9 is large, a point B is quickly pulled to Vdd, the voltage of a comparator VIP is Vdd, the voltage of Vin is a point C voltage, the voltage of the point C is VIN input voltage, the VIN input voltage is obtained by resistance voltage division and then filtering through a capacitor C0, and VIN is generally BUCK type DCDC input voltage. In order to ensure that the circuit works normally, the voltage at the point C is ensured to be less than the voltage at the point B when the BUCK DCDC works at the highest input voltage, and the output ON of the comparator is high. When S3_ is pulled high, the ninth MOS transistor M9 is turned off. When S1 is pulled high and the eighth MOS transistor M8 is turned on, the electric charge stored in the tenth MOS transistor M10 is discharged by the electric charge mirrored by the seventh MOS transistor M7. When the fourth, fifth, sixth and seventh MOS transistors satisfy the conditions M4: M5 and M6: M7 are all 1:1, the following formula can be obtained:

Tdischarge=Cm10*(VB-VC)/Im0

the tenth MOS transistor M10 is always arranged to be biased at a strong inversion layer, so that the effect of obtaining the voltage of the MOS transistor M10 can be achieved

Due to the fact that

Due to the overlapping effect, the proportion in the process is far less than 1 percent, so

Tdischarge=Cm10*In(VB-VC)*Ron

From the last expression it can be seen that there is a strong correlation with the absolute value of the process deviation

The terms are eliminated, and the rest are matching precision relative values and voltage absolute values such as VREF, VB, VC and the like, wherein the voltage absolute values can obtain a relatively accurate value through Bandgap, so that the built-in MOS tube M1 and the tenth MOS tube M10 are adopted for matching, and relatively large W and L values can also be obtained

Accurate discharge time.

But because the temperature of the MOS tube is very positive temperature characteristic and is not compensated, the temperature still exists between-40 and 125 DEG C

The deviation is also compensated for by temperature to be practical. Most of the common resistor and negative temperature coefficient devices such as bjt in the process are influenced by the process

The above absolute value deviation. Therefore, for the total equivalent resistance of the point a to ground, if a temperature compensation device is additionally added, the resistance of the temperature compensation device will have an influence on the accuracy of the whole system. Therefore, a proper temperature coefficient device is selected, the total resistance value of the temperature coefficient device only accounts for 10% of the total equivalent resistance value of the A point to the ground, even if the temperature compensation device has

The influence of the absolute value deviation on the overall accuracy is only additionally introduced

. After a reasonable temperature compensation device is introduced, the precision can be controlled to be equal to that of the temperature compensation device under all PVT conditions

Within.

The invention abandons the traditional RC circuit with low absolute precision (the error of RC product is more than plus or minus 40%) in the BCD process, and uses MOS tube and current mirror depending on the matching precision to simulate the traditional RC circuit, so that the dependence on the absolute precision is converted into the matching precision, and the temperature characteristic of the MOS tube is compensated by adding polysilicon resistor (HR poly) with high resistance value of negative temperature coefficient or parasitic longitudinal P-type transistor (Varasitical Vertical PNP).

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A built-in compensation fixed conduction time circuit is characterized by comprising a current generation circuit module, a capacitance charge and discharge control module connected with the current generation circuit module, a comparator connected with the capacitance charge and discharge control module and a feedforward circuit module; wherein:

the current generation circuit module comprises an operational amplifier and a source electrode follower; the source follower comprises a MOS transistor M0, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a temperature compensation resistor R0;

the gate of the MOS transistor M0 and the gates of the first, second and third MOS transistors M1, M2 and M3 are connected to the output end of the operational amplifier, the source of the MOS transistor M0 is connected to the drain of the first MOS transistor M1, the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, the source of the third MOS transistor M3 is connected to one end of the temperature compensation resistor R0, and the other end of the temperature compensation resistor R0 is grounded; the drain of the MOS transistor M0 is connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5, and the source of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5 and then connected to the power supply vdd;

the capacitor charging and discharging control unit comprises a sixth MOS transistor M6, a seventh MOS transistor M7, a ninth MOS transistor M8, a tenth MOS transistor M9 and a tenth MOS transistor M10; a source of the ninth MOS transistor M9 is connected to a source of the fifth MOS transistor M5, a drain of the ninth MOS transistor M9 is connected to a drain of the eighth MOS transistor M8, and a source of the eighth MOS transistor M8 is connected to a drain of the seventh MOS transistor M7; the gate of the tenth MOS transistor M10 is connected to the drain of the eighth MOS transistor M8, the drain of the ninth MOS transistor M9 and the positive terminal of the comparator, and the source and the drain of the tenth MOS transistor M10 are connected to the source of the seventh MOS transistor and ground; the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7, the drain of the sixth MOS transistor M6 is connected to the drain of the fifth MOS transistor M5, the source of the sixth MOS transistor M6 is connected to the source and the drain of the tenth MOS transistor M10, the source of the seventh MOS transistor M7 and ground, and the gate of the sixth MOS transistor M6 is further connected to the drain of the sixth MOS transistor M6;

the current passing through the current mirror copy current generation circuit module is controlled by a switching tube composed of a seventh MOS transistor M7 and an eighth MOS transistor M8.

2. The internally compensated fixed on-time circuit of claim 1, wherein the input of the operational amplifier is connected to a dc level VREF input.

3. The built-in compensated fixed on-time circuit of claim 2, wherein the temperature compensation resistor R0 is a negative temperature coefficient high resistance polysilicon resistor.

4. The fixed on-time circuit with built-in compensation of claim 3, wherein the operational amplifier clamps a compensation current and supplies the compensation current to the capacitor charge and discharge control module through the fourth and fifth MOS transistors M4 and M5.

5. The internally compensated fixed on-time circuit of claim 4, wherein the comparator and feed forward circuit block comprises a comparator, a first resistor R1, a second resistor R2, a capacitor C0;

one end of the first resistor R1 is connected to an input voltage VIN, the other end of the first resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the drain of the tenth MOS transistor M10, and the capacitor C0 is connected in parallel to two ends of the resistor R2;

a negative terminal of a comparator is connected between the resistor R1 and the resistor R2, the comparator compares the voltage between the positive terminal and the negative terminal and generates a pulse, and the pulse is output through an ON terminal of the comparator.