CN108766933A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN108766933A CN108766933A CN201810503195.XA CN201810503195A CN108766933A CN 108766933 A CN108766933 A CN 108766933A CN 201810503195 A CN201810503195 A CN 201810503195A CN 108766933 A CN108766933 A CN 108766933A
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- Prior art keywords
- semiconductor devices
- production method
- groove
- silicon nitride
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor devices of present invention offer and preparation method thereof, the production method of the semiconductor devices includes：Substrate is provided, there is groove on the substrate；Buffer oxide layer and silicon nitride layer are sequentially formed in the groove, the Si -- H bond ratio of the silicon nitride layer is below 10%；Interlayer dielectric layer is formed using high energy plasma mode in the groove, contact plunger is formed in the interlayer dielectric layer.In semiconductor devices provided by the invention and preparation method thereof, it is initially formed buffer oxide layer and silicon nitride layer in a groove, the Si -- H bond ratio of silicon nitride layer is below 10%, it is arranged by the ingredient of buffer oxide layer and silicon nitride to improve the plasma damage that filling interlayer dielectric layer is brought in a groove, the filling capacity for improving high energy plasma mode improves the yield of product.
Description
Technical field
The present invention relates to ic manufacturing technology fields more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
It is more and more small with the continuous diminution and the progress of manufacturing technology of device size in IC design
Defect will all have an immense impact on to the yield of semiconductor product, may seriously affect the function for the semiconductor devices to be formed, from
And yield is caused to lack.
With the reduction of device size, when forming contact plunger (Contact, CT) in a groove accompanying problem is that
The filling problem of interlayer dielectric layer (InterLayer Dielectrics, ILD), and the plasma damage thereby resulted in
(Plasma Induced Damage, PID) etc., the problems such as performance and yield of semiconductor devices may be influenced.
Therefore, how to provide it is a kind of when forming contact plunger improve plasma damage production method be this field skill
An art personnel technical problem urgently to be resolved hurrily.
Invention content
The purpose of the present invention is to provide a kind of semiconductor devices and preparation method thereof, the interlayer for improving semiconductor devices is situated between
The problem of filling capacity of matter layer is with ion dam age.
To solve the above-mentioned problems, the present invention provides a kind of production method of semiconductor devices, the semiconductor devices
Production method includes：
Substrate is provided, there is groove on the substrate；
Buffer oxide layer and silicon nitride layer are sequentially formed in the groove, the Si -- H bond ratio of the silicon nitride layer exists
10% or less；
Interlayer dielectric layer is formed using high energy plasma mode in the groove, the shape in the interlayer dielectric layer
At contact plunger.
Optionally, in the production method of the semiconductor devices, the width of the groove is in 500nm or less.
Optionally, in the production method of the semiconductor devices, the process conditions of the high energy plasma mode
Including：The power of high-frequency electric field is in 500W hereinafter, air pressure is 1Torr~20Torr.
Optionally, in the production method of the semiconductor devices, the material of the interlayer dielectric layer includes silica.
Optionally, in the production method of the semiconductor devices, the thickness of the buffer oxide layer is
Optionally, in the production method of the semiconductor devices, the thickness of the silicon nitride layer is
Optionally, in the production method of the semiconductor devices, the material that forms the silicon nitride layer include silane and
The flow of ammonia, the silane is 1sccm~500sccm, and the flow of the ammonia is 1sccm~1000sccm.
Optionally, in the production method of the semiconductor devices, the groove is between adjacent device architecture, institute
It includes grid to state device architecture.
Optionally, in the production method of the semiconductor devices, forming the contact plunger includes：
It is sequentially etched the interlayer dielectric layer, the silicon nitride layer and the buffer oxide layer and forms contact hole；
Fill the contact hole.
Optionally, in the production method of the semiconductor devices,
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes the making using above-mentioned semiconductor device
The contact plunger that method is formed.
In conclusion in semiconductor devices provided by the invention and preparation method thereof, it is initially formed buffering oxygen in a groove
Change layer and silicon nitride layer, the Si -- H bond ratio of silicon nitride layer is 10% hereinafter, being arranged by the ingredient of silicon nitride to improve recessed
The plasma damage that interlayer dielectric layer is brought is filled in slot, is improved the filling capacity of high energy plasma mode, is improved
The yield of product.
Description of the drawings
Fig. 1 is the flow chart of the production method of the semiconductor devices of the embodiment of the present invention；
Fig. 2 is the cross-sectional view of the substrate of the semiconductor devices of the embodiment of the present invention；
Fig. 3 is the cross-section structure of formation buffer oxide layer and nitration case in the groove of the semiconductor devices of the embodiment of the present invention
Schematic diagram；
Fig. 4 is cross-sectional view of the semiconductor devices of the embodiment of the present invention when forming interlayer dielectric layer；
Fig. 5 is cross-sectional view of the semiconductor devices of the embodiment of the present invention when forming contact plunger.
Specific implementation mode
In order to keep objects, features and advantages of the present invention more obvious and easy to understand, attached drawing is please referred to.It should be clear that this explanation
Structure, ratio, size etc. depicted in book institute accompanying drawings, only to coordinate the revealed content of specification, for being familiar with this
The personage of technology understands and reads, and is not limited to the enforceable qualifications of the present invention, therefore does not have technical essence meaning
Justice, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the effect of present invention can be generated and institute
Under the purpose that can reach, should all still it fall in the range of disclosed technology contents obtain and can cover.
Core of the invention thought is, improves plasma damage when forming contact plunger in groove and realizes preferable
Filling, that is, need when forming contact plunger to fill inter-level dielectric using high energy plasma mode in a groove
Layer, and by being initially formed buffer oxide layer and silicon nitride layer, change Si -- H bond ratio in silicon nitride layer and is realized below 10%
The purpose of the application.
As shown in Figure 1, the present invention provides a kind of production method of semiconductor devices, the production method of the semiconductor devices
Including：
S10, substrate is provided, there is groove on the substrate；
S20, buffer oxide layer and silicon nitride layer, the Si -- H bond ratio of the silicon nitride layer are sequentially formed in the groove
Below 10%；
S30, high energy plasma mode (High Density Plasma, HDP) forming layer is used in the groove
Between dielectric layer, in the interlayer dielectric layer formed contact plunger (Contact, CT).
It is understandable to enable the features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the specific implementation of the present invention
Example elaborates.
First, can be the substrate of the wafer in a certain technique, institute as shown in Fig. 2, providing substrate 10 according to step S10
Stating has groove 11 on substrate, groove 11 can by formation such as etching technics, due to carry out in a groove in other techniques by
The influence of filled media layer and size, to subsequent technological requirement higher.
In the present embodiment, the width of the groove 11 in 500nm hereinafter, when wider width of groove, carries out subsequent technique
The possibility for influencing groove both sides is smaller, when the width of groove 11 is in 500nm or less, such as 500nm, 400nm, 300nm,
200nm or 100nm and between them when arbitrary parameter, the width of groove 11 is considered as cross of the groove by center
Distance minimum between both sides in section usually can consider using the short side of specification figure such as cuboid as the width,
Method when forming contact plunger through the invention preferably solve inter-level dielectric filling and for groove side etc. from
The problem of daughter damages.
Then, according to step S20, as shown in figure 3, sequentially forming buffer oxide layer 20 and silicon nitride in the groove 11
Layer 30, that is, can be formed on substrate so as to be covered in the film layer of groove surfaces, buffer oxide layer 20 can play buffering
Effect, silicon nitride layer 30 can play the protective action of blocking, the Si -- H bond ratio of the silicon nitride layer 30 10% hereinafter,
Si -- H bond ratio can be come out by apparatus measures.
Optionally, the process conditions of the high energy plasma mode include：The power of high-frequency electric field in 500W hereinafter,
High-frequency electric field can be electromagnetic wave of the frequency in 100kHz~300MHz, and wave-length coverage can be from 1m~3000m, power
500W, 400W, 300W, 200W or 100W and arbitrary parameter between them, air pressure are 1Torr~20Torr, can pass through stabilization
Pressed gas such as N2, Ar or He etc. do not participate in the gas of reaction directly to keep the air pressure of process environments, such as pass through
The flow of 1000sccm~100000sccm maintains air pressure, by the setting to high-frequency electric field and air pressure meets different product
It is required that electromagnetic field of high frequency can refer to electromagnetic wave of the frequency in 100kHz~300MHz, wave-length coverage is from 1~3000m.
In order to more preferably realize that the requirement for preventing plasma damage, the thickness of the buffer oxide layer 20 beSubstrate can be positioned under oxygen-containing environment, such as buffering oxygen can be formed in substrate surface under oxygen atmosphere
Change layer, silica can then be formed for the substrate of silicon materials, thickness can beOrWith
And arbitrary parameter between them, preferably play the role of buffer protection for subsequent technique.
In the silicon nitride layer of formation, the thickness of the silicon nitride layer 30 isSilicon nitride has good
Chemical and physical properties preferably can prevent from forming gap and play protective action as barrier layer, and thickness can
ForOr And arbitrary parameter between them.
Optionally, the material for forming the silicon nitride layer 30 includes silane (SiH4) and ammonia (NH3), the stream of the silane
Amount is 1sccm~500sccm, and the flow of the ammonia is 1sccm~1000sccm, is met by different flow sets different
The requirement of product.
In the present embodiment, for the groove 11 between adjacent device architecture, the device architecture includes grid,
That is slot structure of the groove by formation such as device architecture and dielectric layers, it is slotting to form contact such as between two neighboring grid
Plug, contact plunger is to meet the needs of electric connection, and the contact plunger formed by way of the application prevents from influencing
The electric property of such as grid of semiconductor devices.
Then, according to step S30, as shown in Figures 4 and 5, high energy plasma mode shape is used in the groove 11
At interlayer dielectric layer 40, contact plunger 50, the metals such as 50 generally use copper of contact plunger are formed in the interlayer dielectric layer 40
Filling formed, and meet the requirement of product by techniques such as chemical mechanical grindings.In the present embodiment, it is connect described in formation
Touching plug 50 includes：It is sequentially etched the interlayer dielectric layer 40, the silicon nitride layer 30 and the formation of the buffer oxide layer 20
Contact hole can etch away interlayer dielectric layer, silicon nitride layer and buffer oxide layer by modes such as dry etchings and be formed to destination layer
Contact hole further includes specifically that photoetching agent pattern is formed on interlayer dielectric layer, can for mask, dielectric layer and photoresist etc.
Corresponding setting is needed by technique, thus contact hole needed for being formed in a groove；Fill the contact hole, can by the metals such as copper into
Row fill process, which is realized, to be electrically connected.
Optionally, the material of the interlayer dielectric layer includes silica, can by silane under oxygen and ar gas environment
Crystal column surface is formed by high energy plasma mode, and silica has stable chemical property, can pass through gaseous fluorination
Hydrogen carries out dry etching.
In the present embodiment, the process conditions of the high energy plasma mode include：The power of high-frequency electric field exists
500W is hereinafter, high-frequency electric field can be electromagnetic wave of the frequency in 100kHz~300MHz, and wave-length coverage is from 1m~3000m, work(
Rate can be 500W, 400W, 300W, 200W or 100W and arbitrary parameter between them, and air pressure is 1Torr~20Torr, can
The gas of reaction is not participated in directly by steady pressure gas such as N2, Ar or He etc. to keep the air pressure of process environments, such as logical
The flow of 1000sccm~100000sccm is crossed to maintain air pressure, different product is met by the setting to high-frequency electric field and air pressure
Requirement, electromagnetic field of high frequency can refer to electromagnetic wave of the frequency in 100kHz~300MHz, and wave-length coverage is from 1~3000m.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes the making using above-mentioned semiconductor device
The contact plunger that method is formed, improves the plasma damage of semiconductor devices, has preferable filling capacity to groove, and
Circuit connection is completed by contact plunger, improves the performance of semiconductor devices and the yield of product.
In conclusion in semiconductor devices provided by the invention and preparation method thereof, it is initially formed buffering oxygen in a groove
Change layer and silicon nitride layer, the Si -- H bond ratio of silicon nitride layer is 10% hereinafter, being arranged by the ingredient of silicon nitride to improve recessed
The plasma damage that interlayer dielectric layer is brought is filled in slot, is improved the filling capacity of high energy plasma mode, is improved
The yield of product.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of production method of semiconductor devices, which is characterized in that the production method of the semiconductor devices includes：
Substrate is provided, there is groove on the substrate；
Sequentially form buffer oxide layer and silicon nitride layer in the groove, the Si -- H bond ratio of the silicon nitride layer 10% with
Under；
Interlayer dielectric layer is formed using high energy plasma mode in the groove, is formed and is connect in the interlayer dielectric layer
Touch plug.
2. the production method of semiconductor devices as described in claim 1, which is characterized in that the width of the groove 500nm with
Under.
3. the production method of semiconductor devices as described in claim 1, which is characterized in that the high energy plasma mode
Process conditions include：The power of high-frequency electric field is in 500W hereinafter, air pressure is 1Torr~20Torr.
4. the production method of semiconductor devices as described in claim 1, which is characterized in that the material of the interlayer dielectric layer includes
Silica.
5. the production method of semiconductor devices as described in claim 1, which is characterized in that the thickness of the buffer oxide layer is
6. the production method of semiconductor devices as described in claim 1, which is characterized in that the thickness of the silicon nitride layer is
7. the production method of semiconductor devices as described in claim 1, which is characterized in that form the material packet of the silicon nitride layer
Silane and ammonia are included, the flow of the silane is 1sccm~500sccm, and the flow of the ammonia is 1sccm~1000sccm.
8. the production method of semiconductor devices as described in claim 1, which is characterized in that the groove is located at adjacent device junction
Between structure, the device architecture includes grid.
9. the production method of semiconductor devices as described in any one of claim 1-8, which is characterized in that form the contact
Plug includes：
It is sequentially etched the interlayer dielectric layer, the silicon nitride layer and the buffer oxide layer and forms contact hole；
Fill the contact hole.
10. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes using any one in such as claim 1-9
The contact plunger that the production method of the item semiconductor devices is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810503195.XA CN108766933A (en) | 2018-05-23 | 2018-05-23 | Semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810503195.XA CN108766933A (en) | 2018-05-23 | 2018-05-23 | Semiconductor devices and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108766933A true CN108766933A (en) | 2018-11-06 |
Family
ID=64005238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810503195.XA Pending CN108766933A (en) | 2018-05-23 | 2018-05-23 | Semiconductor devices and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1819121A (en) * | 2005-02-13 | 2006-08-16 | 联华电子股份有限公司 | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof |
| CN101908475A (en) * | 2009-06-04 | 2010-12-08 | 台湾积体电路制造股份有限公司 | Method for fabricating a semiconductor device |
| CN102446840A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for increasing breakdown voltage of double-Damascus structure dielectric barrier layer film |
| CN102903665A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105097650A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of contact plug |
-
2018
- 2018-05-23 CN CN201810503195.XA patent/CN108766933A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1819121A (en) * | 2005-02-13 | 2006-08-16 | 联华电子股份有限公司 | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof |
| CN101908475A (en) * | 2009-06-04 | 2010-12-08 | 台湾积体电路制造股份有限公司 | Method for fabricating a semiconductor device |
| CN102903665A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN102446840A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for increasing breakdown voltage of double-Damascus structure dielectric barrier layer film |
| CN105097650A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of contact plug |
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