CN108762819B - Method for realizing two-way server mainboard on backboard - Google Patents
Method for realizing two-way server mainboard on backboard Download PDFInfo
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- CN108762819B CN108762819B CN201810593169.0A CN201810593169A CN108762819B CN 108762819 B CN108762819 B CN 108762819B CN 201810593169 A CN201810593169 A CN 201810593169A CN 108762819 B CN108762819 B CN 108762819B
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- board card
- slave processor
- slave
- processor board
- processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Multi Processors (AREA)
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- Hardware Redundancy (AREA)
Abstract
The invention discloses a method for realizing a two-way server mainboard on a backboard, which comprises the following operation steps: 1) firstly, a directly-connected passage is configured between QPI buses of two board cards on a backboard; 2) distinguishing a master processor board card and a slave processor board card on a backboard, and determining the positions of the master processor board card and the slave processor board card; 3) when the mainboard is plugged into the slave processor board card position, judging that the board card is used as the slave processor; firstly, informing a main CPU board card to use a power-on logic to accord with a two-way power-on time sequence, and then configuring a processor ID of a slave CPU main board; 4) meanwhile, at least one GPIO PIN is reserved in the CPLDs of the two board cards to a back board and is used as an Enable signal and a Pwrgd signal when the dual-path processor is electrified; and cutting off the PCH and SPI power of the slave processor board card, so that the slave processor board card works in a slave CPU mode. The same board card of the invention can be used as a main processor and also can be used as a slave processor, and can not cause confusion.
Description
Technical Field
The invention relates to the technical field of computer servers, in particular to a method for realizing a two-way server mainboard on a backboard.
Background
The two-way server motherboard is far higher in performance than the one-way server motherboard. However, in the field of reinforcement such as CPCI and CPEX, dual-path interconnection technology in the same system cannot be realized due to the relationship of the area of the plate. Although a plurality of computing modules can be mounted by using a multi-unit server product, the application to the same operating system cannot be realized.
Disclosure of Invention
The technical task of the invention is to provide a method for realizing a two-way server mainboard on a backboard.
The technical task of the invention is realized by the following modes:
the method comprises the following operation steps:
step 1) firstly, a directly-connected passage is configured between QPI buses of two board cards on a backboard;
step 2) distinguishing a master processor board card and a slave processor board card on the backboard, and determining the positions of the master processor board card and the slave processor board card;
step 3) when the mainboard is inserted into the slave processor board card position, judging that the board card is used as the slave processor; firstly, informing a main CPU board card to use a power-on logic to accord with a two-way power-on time sequence, and then configuring a processor ID of a slave CPU main board;
step 4), reserving at least one GPIO PIN from the CPLDs of the two boards to a backboard to serve as an Enable signal and a Pwrgd signal when the dual-path processor is electrified; and cutting off the PCH and SPI power of the slave processor board card, so that the slave processor board card works in a slave CPU mode.
In the step 2), after the positions of the master processor board card and the slave processor board card are determined, reserving a Strap PIN in the slave processor board card to connect to a related PIN PIN of the CPLD.
In the step 3), the board is judged to be used as a slave processor, and the operation method is as follows:
according to the CPU ID design difference of the two-way server mainboard, when the mainboard is plugged into the position of the slave processor board card, the strap PIN in the CPLD is pulled to LOW, so that the board card is judged to be used as the slave processor.
In the step 3), the switch MOS is controlled by the CPLD to pull up the resistor, so as to configure the processor ID of the slave CPU board.
The Enable signal and the Pwrgd signal in the step 4) are used for synchronizing the power-on processes of the two processors.
And in the step 4), the power-on time sequence needs to be judged and selected in the CPLD, and the slave processor board card only uses the board card as the slave CPU and the PCIE HUB.
Compared with the prior art, the method for realizing the two-way server mainboard on the backboard has the characteristics of reasonable design, convenient use and the like, and the same board card can be used as a main processor and a secondary processor without confusion; and can effectually realize that two mainboards constitute a double-circuit server on same backplate, use same operating system.
Detailed Description
Example 1:
the implementation method of the two-way server mainboard on the backboard comprises the following operation steps:
step 1) firstly, a directly-connected passage is configured between QPI buses of two board cards on a backboard;
step 2) distinguishing a master processor board card and a slave processor board card on the backboard, and determining the positions of the master processor board card and the slave processor board card;
step 3) when the mainboard is inserted into the slave processor board card position, judging that the board card is used as the slave processor; firstly, informing a main CPU board card to use a power-on logic to accord with a two-way power-on time sequence, and then configuring a processor ID of a slave CPU main board;
step 4), reserving at least one GPIO PIN from the CPLDs of the two boards to a backboard to serve as an Enable signal and a Pwrgd signal when the dual-path processor is electrified; and cutting off the PCH and SPI power of the slave processor board card, so that the slave processor board card works in a slave CPU mode.
Example 2:
the implementation method of the two-way server mainboard on the backboard comprises the following operation steps:
step 1) firstly, a directly-connected passage is configured between QPI buses of two board cards on a backboard;
step 2) distinguishing a master processor board card and a slave processor board card on the backboard, and determining the positions of the master processor board card and the slave processor board card; and meanwhile, reserving a Strap PIN from a processor board card to be connected to a related PIN foot of the CPLD;
step 3) when the mainboard is inserted into the slave processor board card position, judging that the board card is used as the slave processor; firstly, informing a main CPU board card to use a power-on logic to accord with a two-way power-on time sequence, and controlling a switch MOS to pull up a resistor through a CPLD to configure a processor ID of a slave CPU board;
step 4), reserving at least one GPIO PIN from the CPLDs of the two boards to a backboard to serve as an Enable signal and a Pwrgd signal when the dual-path processor is electrified; and cutting off the PCH and SPI power of the slave processor board card, so that the slave processor board card works in a slave CPU mode.
Example 3:
the implementation method of the two-way server mainboard on the backboard comprises the following operation steps:
step 1) firstly, a directly-connected passage is configured between QPI buses of two board cards on a backboard;
step 2) distinguishing a master processor board card and a slave processor board card on the backboard, and determining the positions of the master processor board card and the slave processor board card; and meanwhile, reserving a Strap PIN from a processor board card to be connected to a related PIN foot of the CPLD;
step 3) designing differences according to the CPU ID of the two-way server mainboard, and when the mainboard is inserted into the board card position of the slave processor, pulling the strap PIN in the CPLD to be LOW, thereby judging that the board card is used as the slave processor; firstly, informing a main CPU board card to use a power-on logic to accord with a two-way power-on time sequence, and controlling a switch MOS to pull up a resistor through a CPLD to configure a processor ID of a slave CPU board;
step 4) at the same time, reserving at least one GPIO PIN from the CPLDs of the two boards to a backboard to be used as an Enable signal and a Pwrgd signal when the dual-path processor is electrified, wherein the Enable signal and the Pwrgd signal are used for synchronizing the electrifying processes of the two processors; cutting off a PCH (Power channel) and an SPI (Serial peripheral interface) power supply of the slave processor board card to enable the slave processor board card to work in a slave CPU (Central processing Unit) mode; at this time, the power-on time sequence is different from that of the single board card, judgment and selection are required to be made in the CPLD, the processor and the memory power supply are not powered on from the processor board card any more, and the board card is only used as the slave CPU and the PCIE HUB.
The present invention can be easily implemented by those skilled in the art from the above detailed description. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the basis of the disclosed embodiments, a person skilled in the art can combine different technical features at will, thereby implementing different technical solutions.
Claims (5)
1. A method for realizing a two-way server mainboard on a backboard is characterized by comprising the following operation steps:
step 1) firstly, a directly-connected passage is configured between QPI buses of two board cards on a backboard;
step 2) distinguishing a master processor board card and a slave processor board card on the backboard, and determining the positions of the master processor board card and the slave processor board card;
step 3) when the mainboard is inserted into the slave processor board card position, judging that the mainboard is used as the slave processor; firstly, informing a main processor board card that the power-on logic conforms to a two-way power-on time sequence, and then configuring a processor ID of a slave processor board card;
step 4) reserving at least one GPIO PIN from CPLDs of the main processor board card and the slave processor board card to be connected to a backboard to serve as an Enable signal and a Pwrgd signal when the dual-path processor is powered on, wherein the Enable signal and the Pwrgd signal are used for synchronizing the power-on processes of the two processors; and cutting off the PCH and SPI power of the slave processor board card, so that the slave processor board card works in a slave processor mode.
2. The method according to claim 1, wherein in step 2), after the positions of the master processor board and the slave processor board are determined, a Strap PIN is reserved in the slave processor board to connect to a PIN associated with the CPLD.
3. The method as claimed in claim 1, wherein the step 3) of determining that the motherboard is used as the slave processor comprises the following steps:
according to the CPU ID design difference of the two-way server mainboard, when the mainboard is plugged into the position of the slave processor board, the Strap PIN in the CPLD is pulled to be LOW, so that the board is judged to be used as the slave processor.
4. The method according to claim 1, wherein in step 3), the switch MOS is controlled by the CPLD to pull up the resistor, so as to configure the processor ID of the processor board.
5. The method according to claim 1, wherein in step 4), a determination selection needs to be made in the CPLD when the board is powered on, and the slave processor board only uses the board as the slave processor and the PCIE HUB.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810593169.0A CN108762819B (en) | 2018-06-11 | 2018-06-11 | Method for realizing two-way server mainboard on backboard |
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| CN201810593169.0A CN108762819B (en) | 2018-06-11 | 2018-06-11 | Method for realizing two-way server mainboard on backboard |
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| CN108762819B true CN108762819B (en) | 2021-01-22 |
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| CN111308934A (en) * | 2020-02-27 | 2020-06-19 | 浪潮商用机器有限公司 | Power supply time sequence power-on monitoring circuit |
| CN117520251A (en) * | 2024-01-05 | 2024-02-06 | 紫光恒越技术有限公司 | Computer motherboard and computer device of dual processor architecture |
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| CN102999140B (en) * | 2012-05-30 | 2015-12-09 | 国家计算机网络与信息安全管理中心 | A kind of electrifying timing sequence control system of PCIE board and method |
| CN104317364A (en) * | 2014-11-17 | 2015-01-28 | 浪潮电子信息产业股份有限公司 | Multi-path server architecture adopting passive backboard |
| CN107239126A (en) * | 2017-06-09 | 2017-10-10 | 山东超越数控电子有限公司 | A kind of two-way server mainboard power-on time sequence control method based on CPLD |
| CN107766282B (en) * | 2017-10-27 | 2021-04-27 | 郑州云海信息技术有限公司 | Design method of eight-path server back plate and double-buckle-plate interconnection system |
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