CN108735898B

CN108735898B - Resistance layer self-gating resistance random access memory and construction method and application thereof

Info

Publication number: CN108735898B
Application number: CN201810501815.6A
Authority: CN
Inventors: 蒋然; 季昊; 张鑫磊
Original assignee: Ningbo University
Current assignee: Shenzhen Research Institute Of Shandong University
Priority date: 2018-05-23
Filing date: 2018-05-23
Publication date: 2022-03-22
Anticipated expiration: 2038-05-23
Also published as: CN108735898A

Abstract

The invention relates to a resistance layer self-gating resistance random access memory and a construction method and application thereof. The resistive random access memory comprises a stack layer; the stacked layers include from the outsideA fourth Hf layer and a fourth Si layer sequentially arranged therein₃N₄Layer, third Hf layer, third Si₃N₄Layer, second Hf layer, second Si₃N₄Layer, first Hf layer and first Si₃N₄And (3) a layer. The invention is based on homogeneous HfO_xGating the 1R array of the substrate, and simultaneously taking the resistance change layer as a gating layer to avoid introducing an additional gating device of a third party; filling (or hollowing) is carried out based on the micro-nano processing asymmetric structure, a depletion region is formed around the filling region under the micro-nano scale, and the depletion region dynamically changes along with an external electric field; the self-gating effect is realized by utilizing the universal physical principle; therefore, the resistance change memory is not limited to HfO_xThe material, but applies to all materials that will form a depletion region.

Description

Resistance layer self-gating resistance random access memory and construction method and application thereof

Technical Field

The invention relates to a resistance layer self-gating resistance random access memory and a construction method and application thereof, belonging to the technical field of gating of a resistance random access memory array.

Background

In recent years, with the rise of the field of big data and artificial intelligence, Resistive Random Access Memory (RRAM) has shown great application prospect. For example, it is applied to the neuromorphic chip and the large-scale data storage with high integration density. Due to the simple two-end structure and the practical advantage of modulating storage through resistance change, the method has natural advantages in the aspect of miniaturization and high-density integration. In order to fully realize these advantages, it is necessary to make the resistive random access memory in the form of a crossbar array (crossbar array) to effectively exert its high-density memory and function as a biomimetic brain synapse. However, in the cross-matrix structure, there is a well-known fundamental problem, namely, a sneak path current problem. The cross-talk current is a current that does not go to the normal read cross point (crossbar point) but instead goes to the side branch cross point. Such currents are negative and may affect the read/write performance of the normal memory spot and may even lead to misreads.

In the prior art, the above problem is usually solved by adding a gate tube (or gate) connected in series to each cross point resistor. And the on-off of the resistance read-write process of each cross point is realized through the gate tube. The most effective current gate tube push-pull transistor is called 1T1R structure (T is crystal) together with the lower cross point (resistor)The initials of the tube trailer). Although the crosstalk current can be effectively limited by the switching function of the transistor, the transistor itself is a three-terminal (source, drain, gate) active device, and the switching of the transistor can be controlled by supplying a gate voltage to the gate. This in turn adds additional active loading and process complexity, while at the same time making the crossbar array less susceptible to scaling, which affects the high density integration of the crossbar array (especially today with high microelectronic integration, this contradiction is even more pronounced). Therefore, two-dimensional gate tubes such as diodes (diodes) or threshold voltage shift (threshold voltage shift) have a tendency to replace transistors. However, from the viewpoint of process simplicity and compatibility, any gate tube is not as attractive as the resistor of the cross point to gate itself directly (called 1R). Although there are some international work reports about 1R, only a limited number of materials (e.g., SiO) are available that can realize both a resistance change layer (resistance change layer) and a gate function_xAnd TaO_xEtc.); the prior art does not have a gating structure or a device based on a universal physical principle so as to break through the material limitation to a certain extent.

For example, chinese patent publication No. 105826468A discloses a self-gating resistive random access memory device and a method for manufacturing the same, in which a gating layer of the self-gating resistive random access memory device is limited to several types — tungsten oxide, titanium oxide, copper oxide, and the like. The gating structure of the device breaks through the material limitation without being based on the universal physical principle.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a resistance change layer self-gating resistance change memory.

The invention also provides a construction method of the resistive random access memory.

The invention also provides a working method of the resistive random access memory.

Description of terms:

the Lift-off process is to glue and photo-etch the substrate first, then to prepare the metal film, where there is photoresist, the metal film is formed on the photoresist, and where there is no photoresist, the metal film is directly formed on the substrate. When a solvent is used to remove the photoresist on the substrate, the unwanted metal is removed in the solvent as the photoresist dissolves, and the metal portion directly formed on the substrate remains to form a pattern. Lift-off is commonly used for patterning of platinum, gold, silicides, and refractory metals.

Bit lines, a memory matrix, are formed of an arrangement of a plurality of memory cells. Each memory cell stores a binary code (0 or 1), and a plurality of memory cells form a word (also called an information cell). A "bit line" corresponds to a "bit" in the memory matrix. One bit line connects the same bit of a particular word number.

Word lines, a memory matrix, are formed by an arrangement of a number of memory cells. Each memory cell stores a binary code (0 or 1), and a plurality of memory cells form a word (also called an information cell). A "word line" corresponds to a "word" in the memory matrix. One word line is connected to a word having a particular number of bits.

The cell refers to a resistive random access memory cell at each cross point (crossbar point). I.e. the individual device cells that make up the array.

The three-dimensional array cross structure is a structure formed by the same resistive random access memory cells (i.e., the cell cells) in an array manner and uniformly stacked on a three-dimensional architecture. Electrodes of the resistive random access memory cells are connected with each other to form a cross arrangement form of sub-lines and bit lines.

The technical scheme of the invention is as follows:

a resistance layer self-gating resistance random access memory comprises a stack layer; the stack layer comprises a fourth Hf layer and a fourth Si layer which are sequentially arranged from outside to inside₃N₄Layer, third Hf layer, third Si₃N₄Layer, second Hf layer, second Si₃N₄Layer, first Hf layer and first Si₃N₄A layer; the left side and the right side of the stacked layer are respectively provided with a bottom electrode and a top electrode; the bottom electrode and the fourth Si₃N₄Layer, third Si₃N₄The layer is communicated with the second Hf layer and is arranged on the upper surface of the second Hf layer; the top electrode is in communication with and disposed over the entire stackIn the first Si₃N₄The upper surface of the layer.

According to the invention, the resistance change layer self-gating resistance change memory preferably comprises a plurality of stacked layers arranged side by side; the top electrode is a bit line; the word lines are described.

Preferred according to the invention, the first Si₃N₄The thickness of the layer is 15-25 nm; the thickness of the first Hf layer is 90-110 nm; second Si₃N₄The thickness of the layer and the second Hf layer is 15-25 nm; third Si₃N₄The thickness of the layer is 15-25 nm; the thickness of the third Hf layer is 90-110 nm; fourth Si₃N₄The thickness of the layer and the fourth Hf layer is 15-25 nm.

A construction method of a self-gating resistive random access memory of a resistive layer comprises the following steps:

1) depositing a first Si on a substrate₃N₄A layer;

2) in the first Si₃N₄Depositing a first Hf layer on the layer, and then carrying out photoetching and lift-off treatment;

3) sequentially depositing a second Si layer on the first Hf layer₃N₄A layer, a second Hf layer;

4) depositing third Si on the second Hf layer₃N₄Layer on the third Si by the method of steps 2) and 3)₃N₄Depositing a third Hf layer and a fourth Si layer on the layer₃N₄A layer and a fourth Hf layer to finally obtain a stacked layer;

5) forming a first hole by photoetching and etching; the first hole is etched from the fourth Hf layer to the second Si layer₃N₄One side edge of the first hole is flush with one side edge of the first Hf layer and one side edge of the third Hf layer, and one side of the first Hf layer and one side of the third Hf layer are completely corroded to expose the first Hf layer and the third Hf layer; annealing for 5-15 min in an oxygen atmosphere at 250-350 ℃; oxygen enters from the first hole, and the first Hf layer and the third Hf layer exposed on the inner wall of the first hole are gradually oxidized to form self-limited HfO_xA resistance change region; due to Si₃N₄The oxidation resistance of the layer plays a role of blocking oxygen from diffusing out of the Hf metal layer; HfO_xThe material has perfect compatibility with the current silicon industry and is the best material in the resistance change material; its complete oxidation state is HfO₂In the anoxic state, HfO_xThe forbidden band width of the semiconductor is modulated by oxygen vacancy defects, and the insulating property is gradually changed towards the direction of the quasi-semiconductor.

With respect to the gradual oxidation, the oxygen first oxidizes the side that is contacted first, and then gradually diffuses and oxidizes to the other side, and the side close to the hole is more sufficiently oxidized than the side far from the hole, depending on the temperature and time of the annealing treatment.

6) Filling the first hole to obtain a top electrode of the cell or a bit line of the three-dimensional array cross structure;

7) forming a second hole on the other side of the first hole by electron beam exposure and dry etching to obtain a third Si₃N₄The layer is exposed in the second hole; to be heavily doped n⁺Si is filled into the second hole and used as a bottom electrode of the cell or a word line of the three-dimensional array cross structure; the heavy doping makes the Si have conductor characteristics, and can be used as a quasi-electrode. The electron beam exposure process includes an alignment step, which is required due to the exposure involving the multilayer stack and the different area positions of the plane.

Preferably, according to the present invention, the three-dimensional array intersection structure is formed by increasing the number of stacked layers or increasing parallel stacked layers; in the step 2), forming more than one first Hf layers; spaces are left among the first Hf layers; the intervals between the plurality of first Hf layers can be adjusted;

in the step 5), etching of the first holes is carried out in the spacing areas among the plurality of first Hf layers, and the diameters of the holes are the spacing distances;

in the step 7), etching of the second holes occurs in the spacing areas between the plurality of first Hf layers, and the diameter of the holes is equal to the spacing distance.

The three-dimensional array cross structure is an asymmetric structure, and the repetition frequency is not more than 6 times. As the number of stacked layers increases with increasing cycling, performance of the gated array device may be degraded due to interlayer stress and alignment limitations.

According to the bookPreferably, in step 1), the first Si is deposited on the substrate₃N₄The layer is realized by a CVD method; in the step 4), depositing a third Si layer on the second Hf layer₃N₄The layers are realized by a CVD method.

Preferably, in step 2), in the first Si₃N₄The deposition of the first Hf layer on the layer was achieved by a dc sputtering method.

Preferably, in step 3), the second Si is₃N₄The layer was deposited by CVD method and the second Hf layer was deposited by sputtering.

According to the invention, in the step 7), the heavily doped standard is n-type, 1-2 x 10¹⁹cm^-3。

According to the invention, the etching method in the step 5) is preferably dry etching.

According to the invention, in the step 6), the first holes are filled with Pt cylindrical electrodes; the implementation method for filling the Pt cylindrical electrode into the first hole is an electron beam evaporation and lift-off process or a direct current sputtering and lift-off process.

According to a preferred embodiment of the present invention, the substrate is a Si substrate.

According to the present invention, the bit lines of the three-dimensional array cross structure in step 6) and the word lines of the three-dimensional array cross structure in step 7) are both cross-shaped.

The working method of the resistive random access memory comprises the following steps:

a) applying voltage from one end of a top electrode or a bit line on the micro-nano scale; in HfO_xThe resistance change region is close to Si₃N₄A charge depletion region is formed, and the charge depletion region expands or contracts along with the direction of an external electric field; due to the charge depletion region, if the charge depletion region extends over the entire HfO_xIn the resistive switching region, only fixed charges exist, and free electrons do not exist, so that current cannot be formed, and the effect similar to unidirectional cut-off of a diode is achieved. The micro-nano scale refers to the scale of tens of nanometers;

b) when a negative voltage is applied, the depletion region expands to form a pinch-off effect and prevent carriers from passing through; pinch-off effect, which is similar to the gate-to-source contact of a fet, first pinches off the electron path through the channel when the gate voltage is lowered. The pinch-off effect of the present invention, specifically at the corners of the asymmetric structure, i.e. the side near n + Si, will pinch off first at negative voltage, since the space charge region is more easily formed and the extension space is wider than the side near Pt.

c) When a positive voltage is applied, the depletion region shrinks, reducing the passage of electrons through the HfO_xA potential barrier of the resistive switching region; the synchronous change of the potential barrier and the external electric field forms the self-rectification characteristic. Under a forward electric field, the current is conducted through electrons, and the resistance is reduced; under the reverse voltage, the electrons are inhibited from passing through, so that the resistance is improved, and the purpose of rectifying and gating is finally realized; i.e. the ability to allow passage of electrons only in a single electric field polarity.

The invention has the beneficial effects that:

1. the resistive random access memory constructed by the method is based on homogeneous HfO_xGating the 1R array of the substrate, and simultaneously taking the resistance change layer as a gating layer to avoid introducing an additional gating device of a third party; filling (or hollowing) is carried out based on the micro-nano processing asymmetric structure, a depletion region is formed around the filling region under the micro-nano scale, and the depletion region dynamically changes along with an external electric field; the self-gating effect is realized by utilizing the universal physical principle; therefore, the resistance change memory is not limited to HfO_xMaterial, but applies to all materials that will form a depletion region; the insulating material is particularly suitable for semiconductor materials or insulators of quasi-semiconductors under non-ideal matching conditions; the invention is based on the physical principle of asymmetric structure induced field effect, has universality for most semiconductor or semiconductor-like insulators (such as oxygen-deficient or doped insulators), and breaks through the material limitation of the 1R gate tube;

2. the thin film material and the process have good compatibility with the semiconductor industry, simple components, good thermal stability and easy process control, and are suitable for high-density integration of devices;

3. according to the resistive random access memory constructed by the method, the filling (or hollow) area is of an asymmetric structure in the longitudinal direction, and the field effect is induced by the asymmetric structure to realize nanoscale self-rectification; meanwhile, the resistance change unit can be integrally prepared into a three-dimensional cross array (3D cross array).

Drawings

FIG. 1 is a schematic representation after completion of one cycle;

FIG. 2 is a schematic structural view of the stacked layers of the present invention;

FIG. 3 is a schematic view of the stack after oxidation is complete;

FIG. 4 is a schematic view of the stack after completion of electrode deposition;

FIG. 5 results in a schematic representation of two stacked layers in parallel;

FIG. 6 is a schematic representation of two parallel stacked layers after completion of electrode deposition;

FIG. 7(a) is a TEM image demonstrating the results of the progressive oxidation;

FIG. 7(b) is an EDX spectrum demonstrating the results of progressive oxidation;

FIG. 8(a) is a current-voltage curve for a cell structure device;

fig. 8(b) is a resistance change threshold voltage transition curve of the unit structure device;

FIG. 8(c) is a high and low resistance switching ratio (on/off ratio) and a rectification ratio (rectification ratio) for realizing self-gating rectification of a unit structure device;

FIG. 8(d) is a retention characteristic of a unit structure device;

FIG. 9 is a schematic diagram of a cross-array structure of a layer;

wherein, 1, a first Hf layer; 2. a second Hf layer; 3. a third Hf layer; 4. a fourth Hf layer; 5. first Si₃N₄A layer; 6. second Si₃N₄A layer; 7. third Si₃N₄A layer; 8. fourth Si₃N₄A layer; 9. a first hole; 10. a second aperture.

Detailed Description

The invention is further described below, but not limited thereto, with reference to the following examples and the accompanying drawings.

Example 1

A resistance layer self-gating resistance random access memory comprises a stack layer; the stacked layer comprises a fourth Hf layer 4 and a fourth Si layer arranged from outside to inside in sequence₃N₄Layer 8, third Hf layer 3, third Si₃N₄Layer 7, second Hf layer 2, second Si₃N₄Layer 6, first Hf layer 1 and first Si₃N₄A layer 5; the left side and the right side of the stacked layer are respectively provided with a bottom electrode and a top electrode; the bottom electrode and the fourth Si₃N₄Layer 8, third Si₃N₄The layer 7 is communicated with the second Hf layer 2 and is arranged on the upper surface of the second Hf layer 2; the top electrode is in communication with the entire stack and is disposed in the first Si₃N₄The upper surface of layer 5.

First Si₃N₄The thickness of layer 5 is 25 nm; the thickness of the first Hf layer 1 was 110 nm; second Si₃N₄The thickness of layer 6 and the second Hf layer 2 was 25 nm; third Si₃N₄The thickness of layer 7 is 25 nm; the thickness of the third Hf layer 3 was 110 nm; fourth Si₃N₄The thickness of layer 8 and fourth Hf layer 4 was 25 nm.

Fig. 8(a) depicts the resistance change characteristics of the device from the current voltage perspective, and it can be observed that the ideal resistance change memory electrical behavior; fig. 8(b), it can be seen that the threshold voltage at which the resistance change occurs, shows stability in a plurality of cycles; device-level applications may be formed. FIG. 8(c), it can be seen that the rectification ratio (point of circle) can reach 10⁵I.e. 10 when the current at the time of gating (on) is at the time of non-gating (off)⁵And (4) doubling. This is an ideal rectification ratio, so that a gating effect can be formed; at the same time, a ratio of 10 between the high-resistance state and the low-resistance state can be observed³It is proved that the high resistance state and the low resistance state can be effectively distinguished. In fig. 8(d), it can be seen that the device retention characteristics are good, relatively stable, and there is no significant degradation.

Example 2

The resistance-change layer self-gating resistance-change memory according to embodiment 1, except that the resistance-change layer self-gating resistance-change memory comprises two stacked layers arranged side by side; the top electrode is a bit line; the word lines are described.

Example 3

A method for constructing a resistance layer self-gated resistance change memory according to embodiment 1, includes the following steps:

1) depositing a first Si on a substrate₃N₄A layer 5; depositing a first Si on a substrate₃N₄Layer 5 is realized by a CVD method; the substrate is a Si substrate;

2) in the first Si₃N₄Depositing a first Hf layer 1 on the layer 5, and then carrying out photoetching and lift-off treatment; in the first Si₃N₄The deposition of the first Hf layer 1 on the layer 5 is achieved by means of a dc sputtering method.

3) Depositing a second Si layer on the first Hf layer 1 in sequence₃N₄Layer 6, second Hf layer 2; as shown in fig. 1. Second Si₃N₄Layer 6 was deposited by CVD method and the second Hf layer 2 was deposited by sputtering.

4) Depositing a third Si on the second Hf layer 2₃N₄Layer 7 on the third Si by the method of steps 2) and 3)₃N₄ Third Hf layer 3, fourth Si layer 7₃N₄Layer 8 and fourth Hf layer 4, finally obtaining a stacked layer; as shown in fig. 2. Depositing a third Si on the second Hf layer 2₃N₄Layer 7 is realized by means of a CVD method.

5) Forming a first hole 9 by photolithography and etching; the first hole 9 is etched from the fourth Hf layer 4 to the second Si₃N₄A layer 6, wherein one side edge of the first hole 9 is flush with one side edge of the first Hf layer 1 and one side edge of the third Hf layer 3, and one side edge of the first Hf layer 1 and one side edge of the third Hf layer 3 are completely corroded to expose the first Hf layer 1 and the third Hf layer 3; annealing for 15min in an oxygen atmosphere at 350 ℃; oxygen enters from the first hole 9, and the first Hf layer 1 and the third Hf layer 3 exposed on the inner wall of the first hole 9 are gradually oxidized to form self-limited HfO_xA resistance change region; the etching method in the step 5) is dry etching. As shown in fig. 3. Due to Si₃N₄The oxidation resistance of the layer plays a role of blocking oxygen from diffusing out of the Hf metal layer; HfO_xThe material has perfect compatibility with the current silicon industry and is a resistance change materialThe best of the materials; its complete oxidation state is HfO₂In the anoxic state, HfO_xThe forbidden band width of the semiconductor is modulated by oxygen vacancy defects, and the insulating property is gradually changed towards the direction of the quasi-semiconductor. FIG. 7(a) shows a stacked structure of cells; FIG. 7(b) shows that the middle Hf metal layer has a state of gradual oxidation from right to left in chemical structure (the right side is more clearly oxidized near the Pt region); by observing FIG. 7(b), HfO can be seen₂The formation of (A) has the following characteristics: the side close to Pt is more fully oxidized and the side away from Pt is less oxidized, even in the unoxidized metallic state at the end. The metallic state and n⁺Si forms an ohmic contact.

6) Filling the first hole 9 to obtain a top electrode of the cell; the first hole is filled with a Pt cylindrical electrode; the implementation method for filling the Pt cylindrical electrode into the first hole is an electron beam evaporation and lift-off process or a direct current sputtering and lift-off process.

7) A second hole 10 is formed on the other side of the first hole 9 by electron beam exposure and dry etching to form a third Si₃N₄The layer 7 is exposed at the second hole 10; to be heavily doped n⁺Si is filled in the second hole 10 (the heavily doped standard is n-type, 1-2 x 10)¹⁹cm^-3) As the bottom electrode of the cell; as shown in fig. 4. The heavy doping makes the Si have conductor characteristics, and can be used as a quasi-electrode. The electron beam exposure process includes an alignment step, which is required due to the exposure involving the multilayer stack and the different area positions of the plane.

Step 1) to step 7) to complete the construction of a cell device;

the bit lines of the three-dimensional array crossing structure in the step 6) and the word lines of the three-dimensional array crossing structure in the step 7) are both in a cross shape.

Example 4

A method for constructing a resistance change layer self-gating resistance change memory as described in embodiment 3, except that the construction of the resistance change memory in embodiment 2 is implemented; in the step 2), two first Hf layers 1 are formed; a space is left between the two first Hf layers 1; the interval between the two first Hf layers 1 can be adjusted;

the step 4) is carried out twice at the same time, and two parallel stacked layers are obtained at the same time; after two parallel stacking layers are obtained, carrying out the operations of the steps 5) to 7) to obtain a first hole 9 and a second hole 10, and respectively carrying out filling operation; the first hole 9 is arranged at the center of the two parallel stacked layers; the second holes 10 are symmetrically disposed on both left and right sides of the stacked layers. As shown in fig. 5 and 6.

In the step 5), the etching of the first holes 9 is carried out in a spacing area between the two first Hf layers 1, and the diameters of the holes are the spacing distance;

in the step 5), the first holes 9 are filled to obtain bit lines of the three-dimensional array cross structure;

in the step 7), etching of the second holes 10 occurs in the spacing area between the two first Hf layers 1, and the hole diameter is equal to the spacing distance; to be heavily doped n⁺Si is filled in the second hole 10 to be used as a word line of the three-dimensional array cross structure;

as shown in fig. 9, it is a simple one-layer cross array structure: electrodes (word lines and bit lines) are arranged at two ends of the structure, hafnium oxide with an irregular structure is arranged in the middle of the structure, and Si is originally filled in hollow positions₃N₄(ii) a The upper and lower electrodes are in a cross array (crossbar). The cross array is the most basic and simplest three-dimensional array structure; on the basis of a one-layer cross array structure, a 2-layer or 3-layer three-dimensional array structure is realized through the circulation of a stacking layer process method;

example 5

An operating method of the resistive random access memory according to

embodiment

1 or 2 includes the following steps:

a) applying voltage from one end of a top electrode or a bit line on the micro-nano scale; in HfO_xThe resistance change region is close to Si₃N₄Will form a charge depletion region, charge depletionThe zone expands or contracts with the direction of the external electric field; due to the charge depletion region, if the charge depletion region extends over the entire HfO_xIn the resistive switching region, only fixed charges exist, and free electrons do not exist, so that current cannot be formed, and the effect similar to unidirectional cut-off of a diode is achieved. The micro-nano scale refers to the scale of tens of nanometers;

b) when a negative voltage is applied, the depletion region expands to form a pinch-off effect and prevent carriers from passing through;

Pt/HfO in the examples₂/n⁺Si structure as a cross-point resistive cell, the cell device is capable of forming a repeatable 10⁴～10⁵The rectification ratio of (2) to maintain a stable state. Forming a built-in electric field in a depletion region formed at the boundary of the filling (or hollow) region; under the action of a built-in electric field, a self-rectification behavior of passing electric charges under the micro-nano scale is formed.

Claims

1. A resistance layer self-gating resistance random access memory is characterized by comprising a stack layer; the stack layer comprises a fourth Hf layer and a fourth Si layer which are sequentially arranged from outside to inside₃N₄Layer, third Hf layer, third Si₃N₄Layer, second Hf layer, second Si₃N₄Layer, first Hf layer and first Si₃N₄A layer; the left side and the right side of the stacked layer are respectively provided with a bottom electrode and a top electrode; the bottom electrode and the fourth Si₃N₄Layer, third Si₃N₄The layer is communicated with the second Hf layer and is arranged on the upper surface of the second Hf layer; the top electrode is in communication with the entire stack and is disposed in the first Si₃N₄An upper surface of the layer; wherein the first Hf layer and the third Hf layer are oxygen-treatedAnnealing and gradual oxidizing under atmosphere to form self-limited HfO_xA resistance change region with a bottom electrode of heavily doped n⁺Si, and Pt is used as a top electrode; HfO_xIs HfO in an anoxic state₂。

2. The resistance-change layer self-gating resistance-change memory according to claim 1, wherein the resistance-change layer self-gating resistance-change memory comprises a plurality of stacked layers arranged side by side; the top electrode is a bit line; the bottom electrode is a word line.

3. The resistance layer self-gated resistance change memory according to claim 1, wherein the first Si is first Si₃N₄The thickness of the layer is 15-25 nm; the thickness of the first Hf layer is 90-110 nm; second Si₃N₄The thickness of the layer and the second Hf layer is 15-25 nm; third Si₃N₄The thickness of the layer is 15-25 nm; the thickness of the third Hf layer is 90-110 nm; fourth Si₃N₄The thickness of the layer and the fourth Hf layer is 15-25 nm.

4. A method for constructing a resistance change memory according to any one of claims 1 to 3, comprising the steps of:

1) depositing a first Si on a substrate₃N₄A layer;

5) forming a first hole by photoetching and etching; the first hole is etched from the fourth Hf layer to the second Si layer₃N₄A side of the first hole is flush with a side of the first Hf layer and the third Hf layerCompletely etching off one side of the first Hf layer and one side of the third Hf layer to expose the first Hf layer and the third Hf layer; annealing for 5-15 min in an oxygen atmosphere at 250-350 ℃; oxygen enters from the first hole, and the first Hf layer and the third Hf layer exposed on the inner wall of the first hole are gradually oxidized to form self-limited HfO_xA resistance change region;

7) forming a second hole on the other side of the first hole by electron beam exposure and dry etching to obtain a third Si₃N₄The layer is exposed in the second hole; to be heavily doped n⁺And Si is filled into the second hole and is used as a bottom electrode of the cell or a word line of the three-dimensional array cross structure.

5. The method for constructing a resistive random access memory according to claim 4, wherein the three-dimensional array cross structure is formed by increasing the number of stacked layers or by increasing parallel stacked layers; in the step 2), forming more than one first Hf layers; spaces are left among the first Hf layers;

6. The method for constructing a resistive random access memory according to claim 4, wherein in the step 1), the first Si is deposited on the substrate₃N₄The layer is realized by a CVD method; in the step 4), depositing a third Si layer on the second Hf layer₃N₄The layer is realized by a CVD method; in the step 2), in the first Si₃N₄Depositing a first Hf layer on the layer by a direct-current sputtering method; second Si₃N₄The layer was deposited by CVD method and the second Hf layer was deposited by sputtering.

7. The method for constructing the resistive random access memory according to claim 4, wherein in the step 7), the heavily doping standard is n-type, 1-2 x 10¹⁹ cm^-3。

8. The method for constructing the resistive random access memory according to claim 4, wherein in the step 6), the first hole is filled with a Pt cylindrical electrode; the implementation method for filling the Pt cylindrical electrode into the first hole is an electron beam evaporation and lift-off process or a direct current sputtering and lift-off process.

9. The method for constructing a resistive random access memory according to claim 4, wherein the bit lines of the three-dimensional array cross structure in the step 6) and the word lines of the three-dimensional array cross structure in the step 7) are both cross-shaped.

10. An operating method of the resistive random access memory according to any one of claims 1 to 3, characterized by comprising the steps of:

a) applying voltage from one end of a top electrode or a bit line on the micro-nano scale;

c) when a positive voltage is applied, the depletion region shrinks, reducing the passage of electrons through the HfO_xA potential barrier of the resistive switching region; the synchronous change of the potential barrier and the external electric field forms the self-rectification characteristic.