CN108733114B - Band gap reference and power-on reset composite function circuit and electronic system - Google Patents

Band gap reference and power-on reset composite function circuit and electronic system Download PDF

Info

Publication number
CN108733114B
CN108733114B CN201710273216.9A CN201710273216A CN108733114B CN 108733114 B CN108733114 B CN 108733114B CN 201710273216 A CN201710273216 A CN 201710273216A CN 108733114 B CN108733114 B CN 108733114B
Authority
CN
China
Prior art keywords
mos tube
coupled
power
circuit
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710273216.9A
Other languages
Chinese (zh)
Other versions
CN108733114A (en
Inventor
梁婷轩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710273216.9A priority Critical patent/CN108733114B/en
Publication of CN108733114A publication Critical patent/CN108733114A/en
Application granted granted Critical
Publication of CN108733114B publication Critical patent/CN108733114B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

A composite function circuit and electronic system of bandgap reference and power-on-reset, the composite function circuit comprising: a bandgap reference circuit powered by a supply voltage and generating a bandgap reference voltage, the bandgap reference circuit comprising a differential operational amplifier; a comparator having an offset voltage, the comparator adapted to compare voltages at first and second inputs of the differential operational amplifier to generate a power-on-reset signal. The scheme of the invention can reduce the complexity of circuit design and effectively improve the integration level of the integrated circuit.

Description

Band gap reference and power-on reset composite function circuit and electronic system
Technical Field
The invention relates to the field of electronic circuit design, in particular to a band-gap reference and power-on reset composite function circuit and an electronic system.
Background
With the continuous development of Integrated Circuit (IC) technology, IC design has entered the deep submicron era, and the batch production of Complementary Metal Oxide Semiconductor (CMOS) has adopted 90nm or even 65nm technology, and the development of IC still targets high frequency, high speed, high integration, multiple functions, and low power consumption. For years, the technology development follows the moore theorem, the integration level of IC chips is improved by 4 times every three years, but from the development point of view, even if the whole industry starts to develop to 10nm, the IC is not yet bound by the process limit and the economic tolerance, and the IC technology still develops according to the moore theorem. So far, based on market competition, continuously improving the cost performance of products is the development power of IC technology, and how to reduce the characteristic size design, improve the product performance and effectively improve the integration level of ICs becomes a crucial problem.
A Power-on Reset (POR) circuit can generate a Power-on Reset signal to operate the circuit in a known state, and thus is widely used in digital systems. A Bandgap reference (Bandgap) circuit is used to provide a Bandgap reference voltage with small temperature variation with a power supply voltage, typically 1.25V, and thus is widely used in analog and digital systems. Currently, in IC design, the two more commonly used circuit blocks are independent and separated from each other.
If a complex function circuit can be designed, two functions of band-gap reference generation and power-on reset are realized at the same time, namely, when an IC is powered on, band-gap reference voltage can be generated and a power-on reset signal can be generated, which is beneficial to the improvement of the integrated level of an integrated circuit.
Disclosure of Invention
The invention solves the technical problem of how to design a composite function circuit which can realize band gap reference generation and power-on reset simultaneously.
To solve the above technical problem, an embodiment of the present invention provides a composite function circuit of a bandgap reference and a power-on reset, where the composite function circuit includes: a bandgap reference circuit powered by a supply voltage and generating a bandgap reference voltage, the bandgap reference circuit comprising a differential operational amplifier; a comparator having an offset voltage, the comparator adapted to compare voltages at first and second inputs of the differential operational amplifier to generate a power-on-reset signal.
Optionally, the complex function circuit further comprises: and the offset voltage adjusting unit is coupled with the comparator and is suitable for adjusting the offset voltage of the comparator according to the power-on reset signal, and the logic level of the power-on reset signal indicates that the band gap reference circuit is in a power-on or power-off state.
Optionally, when the bandgap reference circuit is powered on, the power-on reset signal is a first logic level, and the offset voltage adjusting unit adjusts the offset voltage of the comparator to be equal to a first offset voltage; when the band-gap reference circuit is powered off, the power-on reset signal is a second logic level different from the first logic level, the offset voltage adjusting unit adjusts the offset voltage of the comparator to be equal to a second offset voltage, and the second offset voltage is larger than the first offset voltage.
Optionally, the comparator comprises: a control end of the first amplifying MOS tube is coupled with the first input end of the comparator and the first input end of the differential operational amplifier; and the control end of the second amplifying MOS tube is coupled with the second input end of the comparator and the second input end of the differential operational amplifier.
Optionally, the offset voltage adjusting unit includes: a control end of the third amplification MOS tube is coupled with a control end of the second amplification MOS tube, and an output end of the third amplification MOS tube is coupled with an output end of the second amplification MOS tube; and a data selector, a control terminal of which is connected with a data selection signal, the data selection signal is generated according to the power-on reset signal, an output terminal of the data selector is coupled to an input terminal of the third amplification MOS transistor, a first input terminal of the data selector is coupled to an output terminal of the third amplification MOS transistor, a second input terminal of the data selector is coupled to an input terminal of the second amplification MOS transistor, when the power-on reset signal is at the first logic level, the data selection signal controls the first input terminal of the data selector to be connected with the output terminal thereof, and when the power-on reset signal is at the second logic level, the data selection signal controls the second input terminal of the data selector to be connected with the output terminal thereof.
Optionally, the complex function circuit further comprises: and the input end of the inverter is connected with the power-on reset signal, and the output end of the inverter outputs the data selection signal.
Optionally, the width-to-length ratio of the first amplifying MOS transistor is smaller than the width-to-length ratio of the second amplifying MOS transistor.
Optionally, the comparator further comprises: the bias unit is coupled with the input end of the first amplification MOS tube and the input end of the second amplification MOS tube and is suitable for providing bias current for the first amplification MOS tube and the second amplification MOS tube; the input end of the first current mirror is coupled with the output end of the first amplifying MOS tube, and the common source electrode of the first current mirror is grounded; the input end of the second current mirror is coupled with the output end of the second amplifying MOS tube, and the common source electrode of the second current mirror is grounded; the input end of the first feedback MOS tube is connected with a power supply reference end, and the output end of the first feedback MOS tube is coupled with the output end of the first current mirror; and the input end of the second feedback MOS tube is connected with the power supply reference end, the output end of the second feedback MOS tube is coupled with the output end of the second current mirror and the output end of the comparator, and the control end of the second feedback MOS tube is coupled with the control end of the first feedback MOS tube.
Optionally, the bias unit comprises: the input end of the first bias MOS tube is connected with the power supply reference end, the output end of the first bias MOS tube is coupled with the first amplification MOS tube and the second amplification MOS tube, and the control end of the first bias MOS tube is connected with bias voltage.
Optionally, the differential operational amplifier comprises: the bias circuit comprises a fourth amplification MOS tube, a fifth amplification MOS tube and a second bias MOS tube, wherein the output end of the second bias MOS tube is coupled with the fourth amplification MOS tube and the fifth amplification MOS tube, and the control end of the second bias MOS tube is connected with the bias voltage.
Optionally, the bandgap reference circuit further comprises: the collector of the first triode is connected with the base electrode of the first triode, and the emitter of the first triode is coupled with the second input end of the differential operational amplifier; the collector of the second triode is connected with the base electrode of the second triode; a first end of the first resistor is coupled to the emitter of the second triode, and a second end of the first resistor is coupled to the first input end of the differential operational amplifier; the input end of the third feedback MOS tube is connected with the power supply voltage, the control end of the third feedback MOS tube is coupled with the output end of the differential operational amplifier, and the output end of the third feedback MOS tube is coupled with the emitting electrode of the first triode; the input end of the fourth feedback MOS tube is connected with the power supply voltage, the control end of the fourth feedback MOS tube is coupled with the output end of the differential operational amplifier, and the output end of the fourth feedback MOS tube is coupled with the second end of the first resistor; a collector of the third triode is connected with the base electrode of the third triode; a first end of the second resistor is coupled to an emitter of the third triode, and a second end of the second resistor outputs the bandgap reference voltage; and the control end of the mirror image MOS tube is coupled with the control end of the fourth feedback MOS tube, the input end of the mirror image MOS tube is connected with the power supply voltage, and the output end of the mirror image MOS tube is coupled with the second end of the second resistor.
In order to solve the above technical problem, an embodiment of the present invention further provides an electronic system, where the electronic system includes the bandgap reference and a power-on reset complex function circuit.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the band-gap reference and power-on reset composite function circuit of the embodiment of the invention can comprise a band-gap reference circuit and a comparator. When the band-gap reference circuit is powered on, the voltages of the first input end and the second input end of the differential operational amplifier inside the band-gap reference circuit rise from zero, and the band-gap reference circuit generates band-gap reference voltage. The comparator has offset voltage, and can be set after power supply voltage is stable, the voltages of the first input end and the second input end of the differential operational amplifier are greater than the offset voltage of the comparator, the comparator is suitable for comparing the voltages of the first input end and the second input end of the differential operational amplifier to generate a power-on reset signal, the logic levels of the output power-on reset signal are different before and after the band gap reference circuit is powered on to realize power-on reset, and when the band gap reference circuit is powered off, the logic level of the power-on reset signal is inverted to realize power-off detection. Therefore, the scheme of the invention can realize the band-gap reference and the power-on reset simultaneously during power-on by multiplexing the voltages of the first input end and the second input end of the differential operational amplifier, thereby reducing the complexity of circuit design and effectively improving the integration level of an integrated circuit.
Further, the complex function circuit according to the embodiment of the present invention may further include: and the offset voltage adjusting unit is suitable for adjusting the offset voltage of the comparator according to the power-on reset signal, and the logic level of the power-on reset signal indicates that the band gap reference circuit is in a power-on or power-off state. Specifically, when the bandgap reference circuit is powered on, the power-on reset signal is a first logic level, and the offset voltage adjusting unit adjusts the offset voltage of the comparator to be equal to a first offset voltage; when the band-gap reference circuit is powered off, the power-on reset signal is a second logic level different from the first logic level, and the offset voltage adjusting unit adjusts the offset voltage of the comparator to be equal to a second offset voltage. Because the second offset voltage is greater than the first offset voltage, when the bandgap reference circuit is powered down, only when the power supply voltage is restored again, the voltages of the first input end and the second input end of the differential operational amplifier exceed the higher second offset voltage, the bandgap reference circuit is identified as powered up, the difficulty of being identified as powered up is increased, when the power supply voltage is successfully powered up again, the offset voltage of the comparator is restored to the first offset voltage, only when the power supply voltage is powered down, the voltages of the first input end and the second input end of the differential operational amplifier are lower than the lower second offset voltage, the bandgap reference circuit is identified as powered down, the difficulty of being identified as powered down is increased, and therefore the design is beneficial to improving the power-up and reset stability of the composite functional circuit.
Further, the bias unit in the comparator includes: the control end of the first bias MOS tube is connected with a bias voltage, and a differential operational amplifier in the band-gap reference circuit comprises: and the control end of the second bias MOS tube is also connected with the bias voltage, so that the matching of the comparator and the differential operational amplifier is facilitated.
Drawings
Fig. 1 is a schematic block diagram of a power-on reset circuit in the prior art.
Fig. 2 is a circuit diagram of another prior art power-on-reset circuit.
Fig. 3 is a circuit diagram of a bandgap reference circuit in the prior art.
Fig. 4 is a circuit diagram of a dual function circuit for bandgap reference and power-on-reset in accordance with an embodiment of the present invention.
Fig. 5 is a circuit schematic diagram of another bandgap reference and power-on-reset complex function circuit according to an embodiment of the present invention.
Fig. 6 is a circuit diagram of a comparator and an offset voltage adjusting unit according to an embodiment of the present invention.
Fig. 7 is a simulation diagram of waveforms of a power supply voltage and a power-on reset signal at power-on in the embodiment of the present invention.
Fig. 8 is a waveform simulation diagram of the power supply voltage and the power-on reset signal when power is off in an embodiment of the invention.
Fig. 9 is a waveform simulation diagram of the bandgap reference voltage as a function of temperature in the embodiment of the present invention.
Fig. 10 is a waveform simulation diagram of the variation of the bandgap reference voltage with the supply voltage in the embodiment of the present invention.
Fig. 11 is a waveform simulation diagram of the power supply voltage rejection ratio of the bandgap reference voltage in the embodiment of the present invention.
Detailed Description
As described in the background section, in the current Integrated Circuit (IC) design, a Power-on Reset (POR) Circuit and a Bandgap reference (Bandgap) Circuit are both independent and separately configured, so that the IC integration still has room for improvement.
The inventor of the application analyzes the power-on reset circuit and the band-gap reference circuit in the prior art respectively.
First, the power-on reset circuits in the prior art can be mainly classified into two types: the power-on reset circuit based on time delay and the power-on reset circuit based on reference voltage.
As shown in fig. 1, the delay-based power-on reset circuit 100 may include a delay circuit 101 and a pulse generation circuit 102, where when a power supply voltage is detected, after a delay action of the delay circuit 101, the pulse generation circuit 102 generates a pulse signal P1, and a logic level of the pulse signal P1 may reflect a setup condition of the power supply voltage, so as to implement power-on reset. However, on the one hand, the delay of the delay circuit affects the timeliness of power-on reset detection, and on the other hand, the power-off (brown-out) condition cannot be detected timely.
Based on the above technical problems, a power-on reset circuit based on a reference voltage also exists in the prior art. As shown in fig. 2, the power-on-reset circuit 200 may include: resistance R1And a resistance R2A voltage divider circuit (not shown) for generating a reference voltage VREFIs adapted to compare said reference voltage VREFAnd a voltage division result V of the voltage division circuitRMay comprise an and gate L1, the and gate L1 being adapted to compare the result COMPOUT of the comparator CMP with a logic signal VCRDAnd performing logical operation. When the power supply voltage VDDWhen it is built, the instituteVoltage division result V of the voltage division circuitRCan be designed to be greater than the reference voltage VREFAt this time, the comparison result COMPOUT of the comparator CMP may be a logic high level, and the NMOS transistor N1, the pull-up resistor R3, and the inverter I1 in the logic circuit make the logic signal VCRDIs logic high, so that the reset signal RSTB output by the AND gate L1 is logic high when the power supply voltage V isDDWhen cancelled, no matter the voltage division result V of the voltage division circuit is enabledRIs less than the reference voltage VREFThe NMOS transistor N1 is turned off, and the reset signal RSTB is changed to a logic low level by the AND gate L1 to perform power down detection, although the power-on reset circuit 200 can perform power-on and power-down detection well, on one hand, there are more circuit elements and on the other hand, the resistor R is used for power down detection1And a resistance R2The occupied circuit area is large, so that the integration level of the integrated circuit is not high.
Next, a circuit diagram of a bandgap reference circuit in the prior art can be seen in fig. 3. As shown in fig. 3, the bandgap reference circuit 300 employs a voltage summing structure with a differential operational amplifier. Specifically, the bandgap reference circuit 300 may include the following circuits or devices:
a differential operational amplifier (OPA) having a first input (e.g., a positive input) a and a second input (e.g., a negative input) B;
a first triode Q1, the collector of which is connected to the base thereof, and the emitter of which is coupled to the second input terminal B of the differential operational amplifier OPA;
a second triode Q2, the collector of which is connected with the base thereof;
a first resistor R1, a first terminal of the first resistor R1 is coupled to the emitter of the second transistor Q2, and a second terminal of the first resistor R1 is coupled to the first input terminal a of the differential operational amplifier OPS;
a third feedback MOS transistor MP3, an input terminal of which is connected to the power voltage VDD, a control terminal of which is coupled to the output terminal of the differential operational amplifier OPA, and an output terminal of the third feedback MOS transistor MP3 is coupled to the emitter of the first transistor Q1;
a fourth feedback MOS transistor MP4, an input terminal of which is connected to the power voltage VDD, a control terminal of which is coupled to the output terminal of the differential operational amplifier OPA, and an output terminal of the fourth feedback MOS transistor MP4 is coupled to the second terminal of the first resistor R1;
a third triode Q3, the collector of which is connected with the base thereof;
a second resistor R2, a first end of the second resistor R2 being coupled to the emitter of the third transistor Q3, a second end of the second resistor R2 outputting the bandgap reference voltage VBG;
a mirror MOS transistor MP5, having a control terminal coupled to the control terminal of the fourth feedback MOS transistor MP4, an input terminal connected to the power voltage VDD, and an output terminal coupled to the second terminal of the second resistor R2.
The bandgap reference circuit 300 may further include a start-up circuit (not shown), an output terminal of which is coupled to the first input terminal a or the second input terminal B of the differential operational amplifier OPA, and is configured to provide a bias current for the third feedback MOS transistor MP3 or the fourth feedback MOS transistor MP4, so as to assist the bandgap reference circuit 300 to start up, and fail after the bandgap reference circuit 300 operates normally.
The operating principle of the bandgap reference circuit 300 is analyzed as follows: the bandgap reference circuit 300 generates a bandgap reference voltage VBG with zero temperature coefficient by combining a positive temperature coefficient device and a negative temperature coefficient device. Further, the base-emitter voltage difference of the bipolar transistor is set to Δ VBE) Has positive temperature coefficient under different current density bias, and the base-emitter voltage (set as V) of the selfBE) The reference voltage source has a negative temperature coefficient, and the two voltages are linearly superposed to obtain a more proper reference voltage source with an approximate zero temperature coefficient.
Let VAAnd VBVoltages, V, of a first input terminal A and a second input terminal B of a differential operational amplifier OPA, respectivelyBGIs the amplitude, R, of the bandgap reference voltage VBG1And R2The first resistor R1 and the second resistor R2, the fourth feedback MOS transistor MP4 and the third feedback MOS transistor MP3k are the same transistor, and k is the second resistor R2The ratio of the collector currents of transistor Q2 and transistor Q1, I3 being the collector current of the third transistor, I2 being the collector current of the second transistor,. DELTA.VBE12Is the difference between the base-emitter voltages of the second transistor Q2 and the first transistor Q1, VBE3Is the base-emitter voltage of the third transistor Q3.
Then there is VBG＝VBE3+I3×R2Since the gates and the sources of the fourth feedback MOS transistor MP4 and the fifth feedback MOS transistor MP5 are connected, I2 is equal to I3, and then V is equal to V3BG＝VBE3+I2×R2＝VBE3+ΔVBE12÷R1×R2＝VBE3+(VA-VB)÷R1×R2＝VBE3+VT×lnk÷n1×R2Wherein V isTIs a constant proportional to the temperature T.
In a specific implementation, the amplitude of the bandgap reference voltage VBG can be adjusted by adjusting the base-emitter voltage of the third transistor Q3, the resistance values of the first resistor R1 and the second resistor R2, and the ratio of the collector currents of the second transistor Q2 and the first transistor Q1 (i.e., the size ratio of the two).
In view of the above technical problems, embodiments of the present invention provide a band gap reference and power-on reset composite function circuit, which can simultaneously implement two functions of band gap reference and power-on reset during power-on by multiplexing voltages of a first input terminal and a second input terminal of a differential operational amplifier in the band gap reference circuit, thereby reducing complexity of circuit design and effectively improving integration level of an integrated circuit.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 is a circuit diagram of a dual function circuit for bandgap reference and power-on-reset in accordance with an embodiment of the present invention.
As shown in fig. 4, a bandgap reference and power-on-reset complex function circuit 400 may include a bandgap reference circuit 300 and a comparator 401.
The bandgap reference circuit 300 is powered by a power supply voltage VDD and generates a bandgap reference voltage VBG, and the bandgap reference circuit 300 includes a differential operational amplifier OPA. When the bandgap reference circuit 300 is powered on, the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA inside the bandgap reference circuit rise from zero and tend to be stable as the power supply voltage VDD is stable.
The bandgap reference circuit 300 may have the same circuit structure as that of the bandgap reference circuit shown in fig. 3, but is not limited thereto, and other bandgap reference circuits may be used as long as they can generate a bandgap reference voltage after power-up and include at least a differential operational amplifier. The embodiments of the present invention are illustrated in the drawings of the specification by taking the same circuit structure of the bandgap reference circuit 300 as that of the bandgap reference circuit shown in fig. 3 as an example.
The comparator 401 has an offset voltage, for example, the power supply voltage VDD may be 3.3V, and the offset voltage may be 1.2V. The comparator 401 is adapted to compare voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA to generate a power-on reset signal RST.
Preferably, after the power supply voltage VDD is stabilized, the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA may be set to be greater than the offset voltage of the comparator 401. Then, after the bandgap reference circuit 300 is powered on, the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA rise from 0, and when it is greater than the offset voltage of the comparator 401, the power-on reset signal RST is at a first logic level (e.g., logic low level); when the bandgap reference circuit 300 is powered down, the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA start to drop to 0, and when the voltages are smaller than the offset voltage of the comparator 401, the power-on reset signal RST is inverted to a second logic level (for example, a logic high level) different from the first logic level, so as to implement power-on reset and power-down detection.
Therefore, the complex function circuit 400 according to the embodiment of the present invention can simultaneously implement bandgap reference and power-on reset during power-on by multiplexing the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA, thereby reducing the complexity of circuit design and effectively improving the integration level of the integrated circuit. Further, the air conditioner is provided with a fan,
fig. 5 is a circuit schematic diagram of another bandgap reference and power-on-reset complex function circuit according to an embodiment of the present invention.
As shown in fig. 5, the bandgap reference and power-on-reset complex function circuit 500 is substantially similar to the complex function circuit 400 shown in fig. 4, with the difference that the complex function circuit 500 may further include an offset voltage adjusting unit 402. The offset voltage adjusting unit 402 is coupled to the comparator 401, and the offset voltage adjusting unit 402 is adapted to adjust the offset voltage of the comparator 401 according to the power-on reset signal RST, where a logic level of the power-on reset signal RST indicates that the bandgap reference circuit 300 is in a power-on or power-off state.
For example, when the bandgap reference circuit 300 is powered on, the power-on reset signal RST may be at the first logic level (e.g., a logic low level), and the offset voltage adjusting unit 402 may adjust the offset voltage of the comparator 401 to be equal to a first offset voltage; when the bandgap reference circuit 300 is powered down, the power-on reset signal RST is at the second logic level (e.g., a logic high level) different from the first logic level, and the offset voltage adjusting unit 402 may adjust the offset voltage of the comparator 401 to be equal to a second offset voltage, where the second offset voltage is greater than the first offset voltage.
Since the second offset voltage is greater than the first offset voltage, when the bandgap reference circuit 300 is powered down, only when the power supply voltage VDD is restored again, the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA exceed the higher second offset voltage, and the power-on reset signal RST is inverted, so that the difficulty of being identified as power-on is increased. When the power is successfully powered up again, the offset voltage of the comparator 401 is restored to the lower first offset voltage, and only when the power supply voltage VDD is powered down, the voltage of the first input end a and the second input end B of the differential operational amplifier OPA is lower than the first offset voltage, the power down can be identified. The design can resist the situation that the power supply voltage VDD is subjected to frequent and small fluctuation, but the function of the whole circuit is not influenced, the power supply voltage VDD cannot be identified as power-on or power-off, and the stability of power-on reset of the composite function circuit 500 is improved.
Fig. 6 is a circuit diagram of a comparator and an offset voltage adjusting unit according to an embodiment of the present invention.
As shown in fig. 6, in a specific implementation, the comparator (not shown) may include a first amplifying MOS transistor MPA1 and a second amplifying MOS transistor MPA 2. In the embodiment of the present invention, only the first amplification MOS transistor MPA1 and the second amplification MOS transistor MPA2 are PMOS transistors for example, but not limited thereto, and they may also be NMOS transistors. A control terminal (i.e., a gate) of the first amplifying MOS transistor MPA1 is coupled to a first input terminal (i.e., a positive input terminal, not shown) of the comparator and a first input terminal a of the differential operational amplifier OPA; a control terminal (i.e., a gate) of the second amplifying MOS transistor MPA2 is coupled to a second input terminal (i.e., a negative input terminal, not shown) of the comparator and the second input terminal B of the differential operational amplifier OPA.
Further, the offset voltage adjusting unit (not shown) may include: a third amplifying MOS transistor MPA3 and a data selector (MUX) 403. Wherein:
the type of the third amplifying MOS transistor MPA3 is the same as that of the first amplifying MOS transistor MPA1 and the second amplifying MOS transistor MPA2, and the third amplifying MOS transistor MPA3 is a PMOS transistor. A control terminal (i.e., a gate) of the third amplifying MOS transistor MPA3 is coupled to a control terminal of the second amplifying MOS transistor MPA2, and an output terminal (i.e., a drain) of the third amplifying MOS transistor MPA3 is coupled to an output terminal (i.e., a drain) of the second amplifying MOS transistor MPA 2.
A control terminal (not shown) of the data selector 403 accesses a data selection signal S, which is generated according to the power-on reset signal RST, for example, the logic level of the data selection signal S may be the same as or opposite to the power-on reset signal RST. An output terminal of the data selector 403 is coupled to an input terminal (i.e., a source) of the third amplifying MOS transistor MPA3, a first input terminal X of the data selector 403 is coupled to an output terminal of the third amplifying MOS transistor MPA3, and a second input terminal of the data selector 403 is coupled to an input terminal of the second amplifying MOS transistor MPA 2.
In a specific implementation, when the power-on reset signal RST is at the first logic level (e.g., a logic low level), the data selection signal S controls the first input terminal X of the data selector 403 to be connected to the output terminal Y thereof, which is denoted as X ═ Y for simplicity, so that the input terminal and the output terminal of the third amplification MOS transistor MPA3 are connected, and the third amplification MOS transistor MPA3 is short-circuited; when the power-on reset signal RST is at the second logic level (e.g., logic high level), the data selection signal S controls the second input terminal Z of the data selector 403 to be connected to the output terminal Y thereof, which is represented as Z ═ Y for simplicity, so that the third amplification MOS transistor MPA3 is connected in parallel with the second amplification MOS transistor MPA2, and the equivalent aspect ratio of the second amplification MOS transistor MPA2 is increased.
Referring to fig. 5 and 6 together, in an implementation, the complex function circuit 500 may further include: the input end of the inverter 404 is connected to the power-on reset signal RST, and the output end of the inverter outputs the data selection signal S, that is, the logic levels of the data selection signal S and the power-on reset signal RST are opposite.
Further, the width-to-length ratio of the first amplifying MOS transistor MPA1 may be smaller than the width-to-length ratio of the second amplifying MOS transistor MPA2 to cause mismatch (mismatch) of the comparator, so that the offset voltage of the comparator is equal to the first offset voltage. The second offset voltage can be adjusted by adjusting the width-to-length ratio of the third amplifying MOS transistor MPA3 properly. For example, the ratio of the width to length ratios of the first, second and third amplifying MOS transistors is 2:6:1, but is not limited thereto. When X of the data selector 403 is equal to Y, the width-to-length ratio of the two amplifying MOS transistors of the comparator is 1: 3, when Z of the data selector 403 is equal to Y, the ratio of the width to length ratios of the two amplifying MOS transistors of the comparator is 1: and 3.5, enabling the second offset voltage to be larger than the first offset voltage, and meeting the system design requirement.
With continued reference to fig. 6, in an embodiment of the present invention, the comparator may further include: a bias unit (not labeled in the figure), a first current mirror CM1, a second current mirror CM2, a first feedback MOS transistor MPF1 and a second feedback MOS transistor MPF 2. Wherein:
the bias unit is coupled to the input terminal of the first amplifying MOS transistor MPA1 and the input terminal of the second amplifying MOS transistor MPA2, and is adapted to provide bias currents for the first amplifying MOS transistor MPA1 and the second amplifying MOS transistor MPA 2.
The first and second current mirrors CM1 and CM2 are loads for the comparator. Also, as known to those skilled in the art, the current mirror has an input, an output, and a common source. The input end of the first current mirror CM1 is coupled to the output end of the first amplification MOS transistor MPA1, and the common source thereof is grounded; the input terminal of the second current mirror CM2 is coupled to the output terminal of the second amplifying MOS transistor MPA2, and the common source thereof is grounded.
An input end of the first feedback MOS transistor MPF1 is connected to a power reference end, and an output end of the first feedback MOS transistor MPF1 is coupled to an output end of the first current mirror CM 1; in this embodiment, the power reference terminal may be connected to the power supply voltage VDD, so that the bandgap reference circuit 300 and the comparator are powered on simultaneously, but not limited thereto, the power reference terminal may also be connected to other voltages as long as the comparator can be powered on and is synchronized with the variation trend of the power supply voltage VDD within an error allowable range.
An input terminal of the second feedback MOS transistor MPF2 is coupled to the power reference terminal, an output terminal of the second feedback MOS transistor MPF2 is coupled to the output terminal of the second current mirror CM2 and the output terminal of the comparator, and a control terminal of the second feedback MOS transistor MPF2 is coupled to the control terminal of the first feedback MOS transistor MPF 1.
In a specific implementation, the bias unit may include a first bias MOS transistor MPB1, an input terminal of which is connected to the power reference terminal, an output terminal of which is coupled to the first amplification MOS transistor MPA1 and the second amplification MOS transistor MPA2, and a control terminal of which is connected to a bias voltage Vb.
It should be noted that, the comparator is only exemplified by the circuit structure shown in fig. 6, but not limited thereto, for example, the amplifying MOS transistor, the feedback MOS transistor, and the bias MOS transistor may all be NMOS transistors, and the load, that is, the current mirror may be a P-type current mirror, even a load in other forms is adopted, only the connection mode of the circuit needs to be properly adjusted, and the embodiments of the present invention do not exemplify one another.
With continued reference to fig. 5 and 6, the differential operational amplifier OPA may include: the output end of the second bias MOS transistor is coupled to the fourth amplification MOS transistor and the fifth amplification MOS transistor, and the control end of the second bias MOS transistor is connected to the bias voltage Vb, which is favorable for matching the comparator and the differential operational amplifier OPA.
Fig. 7 to 11 are waveform simulation diagrams of internal signals according to the complex function circuit 500 shown in fig. 5 and 6. All simulations are based on 55nm process conditions, and the transistors in the complex function circuit 500 operate in a sub-threshold region, meeting the low power consumption requirements of the circuit. Table 1 shows parameters, symbols, conditions and results related to the simulation.
TABLE 1
Figure BDA0001277697040000131
The following description is made with reference to table 1. As shown in fig. 7, under the simulation conditions that the power supply voltage VDD is 3.3V, the rise time Tr is 10us, and the temperature T is 25 ℃, when the power supply voltage VDD starts to rise from 0, the power-on reset signal RST has a negligible jitter, and when the power supply voltage VDD rises to exceed 2.6V, the power-on reset signal RST is inverted, that is, Vtp-UP corresponding to the minimum power-on transition level (Trip voltage of power ramp-UP) in table 1 is 2.6V. Then, the power supply voltage VDD continues to rise until it rises to 3.3V at 12.45 μ s, and the logic level of the power-on reset signal RST is equal to the power supply voltage VDD.
As shown in fig. 8, under the same simulation conditions as the simulation waveforms of fig. 7, when the power voltage VDD is stabilized at 3.3V, the offset voltage of the comparator is equal to the first offset voltage. Referring to fig. 5 and 6 together, if the system is just powered down, the logic level of the power-on reset signal RST is kept equal to the power supply voltage VDD until the power supply voltage is powered down to be lower than 1.24V, so that the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA are smaller than the first offset voltage, the power-on reset signal RST is inverted to a logic low level in the figure, and the voltage thereof approaches 0, that is, Vtp-DN is 1.24V corresponding to the maximum power-down transition level (Trip voltage of power-down) in table 1. At this time, according to the action of the data selection signal S, Z in the data selector 403 is equal to Y, so that the offset voltage of the comparator is equal to the second offset voltage, and in the simulation result of this figure, if and only when the power supply voltage VDD is restored to exceed 2.6V, the voltages of the first input terminal a and the second input terminal B of the differential operational amplifier OPA are made to be greater than the second offset voltage, the logic level of the power-on reset signal RST is inverted again, the logic level of the subsequent power-on reset signal RST is equal to the power supply voltage VDD, and the offset voltage of the comparator is also restored to the first offset voltage. It can be seen that when the power supply voltage VDD is subject to frequent and small fluctuations, it is not recognized as a power failure, and after the power failure is completed, the small voltage rise is also not recognized as a power on, and the complex function circuit 500 has good detection stability of power on and power off.
As shown in fig. 5 and fig. 9, for the bandgap reference voltage VBG output by the bandgap reference circuit 300, under the simulation condition that the power supply voltage VDD is 3.3V, the temperature is scanned, the scanning range is-45 ℃ to 125 ℃, and simulation and analysis can obtain: the temperature coefficient of the band gap reference voltage VBG is 13.4 ppm/DEG C, and the band gap reference voltage VBG has a lower temperature coefficient.
As shown in fig. 5 and 10, the bandgap reference voltage VBG output by the bandgap reference circuit 300 is scanned again under the simulation condition of 25 ℃, so that the power supply voltage VDD changes in a stepwise manner from 2.97V to 3.63V, and the simulation results show that: the minimum value of the band-gap reference voltage VBG is 1.167V, the maximum value is 1.169V, and the stability is good.
As shown in fig. 5 and fig. 11, simulation is also performed on the Power Supply Rejection Ratio (PSRR) of the bandgap reference voltage VBG output by the bandgap reference circuit 300, where the Power supply voltage VDD is 3.3V, the temperature T is 25 ℃, and the obtained simulation result is that the PSRR is 50.89dB, and relatively speaking, the obtained PSRR meets the industrial standard, and the bandgap reference voltage VBG is less affected by the Power supply voltage variation.
In addition, the supply current Icc of the multi-function circuit 500 shown in fig. 5 is only 0.5 μ a, with low power consumption.
In summary, the band-gap reference and power-on reset composite functional circuit provided by the embodiment of the invention can detect power-on and power-off of a system while generating the band-gap reference voltage with the amplitude of 1.17V, the temperature coefficient of 13.4 ppm/DEG C and the PSRR of 50.89dB, and has the advantages of low power consumption, simple design and layout, small characteristic size and capability of meeting deep submicron design requirements.
The invention also discloses an electronic system which comprises the band gap reference and the power-on reset composite function circuit 400 or 500. In a specific implementation, the electronic system may be a circuit module carried on a printed circuit board, and may be carried on a chip, which is not particularly limited in this embodiment.
It should be noted that "logic high level" and "logic low level" in this document are relative logic levels, "logic high level" refers to a level range that can be recognized as a digital signal "1," logic low level "refers to a level range that can be recognized as a digital signal" 0, "and the specific level range is not particularly limited.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A composite function circuit with bandgap reference and power-on reset, comprising:
a bandgap reference circuit powered by a supply voltage and generating a bandgap reference voltage, the bandgap reference circuit comprising a differential operational amplifier;
a comparator having an offset voltage, the comparator adapted to compare voltages at first and second inputs of the differential operational amplifier to generate a power-on reset signal;
the offset voltage adjusting unit is coupled with the comparator and is suitable for adjusting the offset voltage of the comparator according to the power-on reset signal, and the logic level of the power-on reset signal indicates that the band-gap reference circuit is in a power-on or power-off state;
when the band-gap reference circuit is powered on, the power-on reset signal is a first logic level, and the offset voltage adjusting unit adjusts the offset voltage of the comparator to be equal to a first offset voltage; when the band-gap reference circuit is powered off, the power-on reset signal is a second logic level different from the first logic level, the offset voltage adjusting unit adjusts the offset voltage of the comparator to be equal to a second offset voltage, and the second offset voltage is larger than the first offset voltage.
2. The complex function circuit of claim 1, wherein the comparator comprises:
a control end of the first amplifying MOS tube is coupled with the first input end of the comparator and the first input end of the differential operational amplifier;
and the control end of the second amplifying MOS tube is coupled with the second input end of the comparator and the second input end of the differential operational amplifier.
3. The complex function circuit of claim 2, wherein the offset voltage adjusting unit comprises:
a control end of the third amplification MOS tube is coupled with a control end of the second amplification MOS tube, and an output end of the third amplification MOS tube is coupled with an output end of the second amplification MOS tube;
and a data selector, a control terminal of which is connected with a data selection signal, the data selection signal is generated according to the power-on reset signal, an output terminal of the data selector is coupled to an input terminal of the third amplification MOS transistor, a first input terminal of the data selector is coupled to an output terminal of the third amplification MOS transistor, a second input terminal of the data selector is coupled to an input terminal of the second amplification MOS transistor, when the power-on reset signal is at the first logic level, the data selection signal controls the first input terminal of the data selector to be connected with the output terminal thereof, and when the power-on reset signal is at the second logic level, the data selection signal controls the second input terminal of the data selector to be connected with the output terminal thereof.
4. The complex function circuit of claim 3, further comprising:
and the input end of the inverter is connected with the power-on reset signal, and the output end of the inverter outputs the data selection signal.
5. The complex function circuit of claim 2, wherein the width-to-length ratio of the first amplifying MOS transistor is smaller than the width-to-length ratio of the second amplifying MOS transistor.
6. The complex function circuit of any of claims 2-5, wherein the comparator further comprises:
the bias unit is coupled with the input end of the first amplification MOS tube and the input end of the second amplification MOS tube and is suitable for providing bias current for the first amplification MOS tube and the second amplification MOS tube;
the input end of the first current mirror is coupled with the output end of the first amplifying MOS tube, and the common source electrode of the first current mirror is grounded;
the input end of the second current mirror is coupled with the output end of the second amplifying MOS tube, and the common source electrode of the second current mirror is grounded;
the input end of the first feedback MOS tube is connected with a power supply reference end, and the output end of the first feedback MOS tube is coupled with the output end of the first current mirror;
and the input end of the second feedback MOS tube is connected with the power supply reference end, the output end of the second feedback MOS tube is coupled with the output end of the second current mirror and the output end of the comparator, and the control end of the second feedback MOS tube is coupled with the control end of the first feedback MOS tube.
7. The complex function circuit of claim 6, wherein the biasing unit comprises:
the input end of the first bias MOS tube is connected with the power supply reference end, the output end of the first bias MOS tube is coupled with the first amplification MOS tube and the second amplification MOS tube, and the control end of the first bias MOS tube is connected with bias voltage.
8. The complex function circuit of claim 7, wherein the differential operational amplifier comprises: the bias circuit comprises a fourth amplification MOS tube, a fifth amplification MOS tube and a second bias MOS tube, wherein the output end of the second bias MOS tube is coupled with the fourth amplification MOS tube and the fifth amplification MOS tube, and the control end of the second bias MOS tube is connected with the bias voltage.
9. The composite function circuit of any of claims 1 to 5, wherein the bandgap reference circuit further comprises:
the collector of the first triode is connected with the base electrode of the first triode, and the emitter of the first triode is coupled with the second input end of the differential operational amplifier;
the collector of the second triode is connected with the base electrode of the second triode;
a first end of the first resistor is coupled to the emitter of the second triode, and a second end of the first resistor is coupled to the first input end of the differential operational amplifier;
the input end of the third feedback MOS tube is connected with the power supply voltage, the control end of the third feedback MOS tube is coupled with the output end of the differential operational amplifier, and the output end of the third feedback MOS tube is coupled with the emitting electrode of the first triode;
the input end of the fourth feedback MOS tube is connected with the power supply voltage, the control end of the fourth feedback MOS tube is coupled with the output end of the differential operational amplifier, and the output end of the fourth feedback MOS tube is coupled with the second end of the first resistor;
a collector of the third triode is connected with the base electrode of the third triode;
a first end of the second resistor is coupled to an emitter of the third triode, and a second end of the second resistor outputs the bandgap reference voltage;
and the control end of the mirror image MOS tube is coupled with the control end of the fourth feedback MOS tube, the input end of the mirror image MOS tube is connected with the power supply voltage, and the output end of the mirror image MOS tube is coupled with the second end of the second resistor.
10. An electronic system comprising a bandgap reference and power-on-reset multifunctional circuit as claimed in any one of claims 1 to 9.
CN201710273216.9A 2017-04-24 2017-04-24 Band gap reference and power-on reset composite function circuit and electronic system Active CN108733114B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710273216.9A CN108733114B (en) 2017-04-24 2017-04-24 Band gap reference and power-on reset composite function circuit and electronic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710273216.9A CN108733114B (en) 2017-04-24 2017-04-24 Band gap reference and power-on reset composite function circuit and electronic system

Publications (2)

Publication Number Publication Date
CN108733114A CN108733114A (en) 2018-11-02
CN108733114B true CN108733114B (en) 2020-08-07

Family

ID=63934606

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710273216.9A Active CN108733114B (en) 2017-04-24 2017-04-24 Band gap reference and power-on reset composite function circuit and electronic system

Country Status (1)

Country Link
CN (1) CN108733114B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109474263A (en) * 2018-12-17 2019-03-15 上海贝岭股份有限公司 A kind of electrification reset circuit
KR102610062B1 (en) * 2019-04-15 2023-12-06 에스케이하이닉스 주식회사 Voltage generator, semiconductor apparatus and semiconductor system using the same
CN110868199B (en) * 2019-11-04 2023-12-22 西安恒松阳电气有限公司 Power-on long time delay protection circuit
CN116896364B (en) * 2023-09-06 2023-12-19 深圳市微源半导体股份有限公司 Power-on reset detection circuit, integrated circuit and chip
CN118041330B (en) * 2024-04-15 2024-07-02 上海芯炽科技集团有限公司 Band gap-based power-on reset circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102622038B (en) * 2012-03-29 2014-08-13 北京经纬恒润科技有限公司 Band-gap reference voltage source circuit and band-gap reference voltage source
CN103378830B (en) * 2012-04-17 2016-08-24 国民技术股份有限公司 Electrification reset circuit
CN103197716A (en) * 2013-03-29 2013-07-10 东南大学 Band-gap reference voltage circuit for reducing offset voltage influence
JP6082356B2 (en) * 2014-02-13 2017-02-15 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date
CN108733114A (en) 2018-11-02

Similar Documents

Publication Publication Date Title
CN108733114B (en) Band gap reference and power-on reset composite function circuit and electronic system
CN110212902B (en) Power-on reset circuit
US7176740B2 (en) Level conversion circuit
US8115559B2 (en) Oscillator for providing a constant oscillation signal, and a signal processing device including the oscillator
EP2498162B1 (en) Startup circuit for low voltage cascode beta multiplier current generator
US10707757B2 (en) Reference voltage generator with adaptive voltage and power circuit
CN108958344B (en) Substrate bias generating circuit
US8786324B1 (en) Mixed voltage driving circuit
US9136827B2 (en) Power-on reset circuit
KR20090009293A (en) Very low power analog compensation circuit
CN112527042B (en) Substrate bias generating circuit
JP2011039887A (en) Band gap reference circuit
JP5447293B2 (en) Reference current generation circuit and information processing apparatus including the same
KR100939291B1 (en) Reference voltage generating circuit
CN111446949B (en) Power-on reset circuit and integrated circuit
US9767861B2 (en) Regulated voltage supply with low power consumption and small chip area
US11705902B2 (en) Supply voltage detecting circuit and circuit system using the same
CN114610108A (en) Bias current generating circuit
KR100832887B1 (en) Fully cmos reference current generator with temperature compensation
CN108628379B (en) Bias circuit
US8836382B1 (en) Mixed voltage driving circuit
US11762410B2 (en) Voltage reference with temperature-selective second-order temperature compensation
US7868622B2 (en) Circuit for detecting power supply voltage drop
CN114995564B (en) Starting circuit, starting method and electronic equipment
CN106027029B (en) Gpio interface circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant