CN108712092A

CN108712092A - A method of keep double winding peak point current constant

Info

Publication number: CN108712092A
Application number: CN201810562305.XA
Authority: CN
Inventors: 张宾
Original assignee: Wuhan Sheung Shui Microelectronics Technology Co Ltd
Current assignee: Wuhan Sheung Shui Microelectronics Technology Co Ltd
Priority date: 2018-06-04
Filing date: 2018-06-04
Publication date: 2018-10-26
Anticipated expiration: 2038-06-04
Also published as: CN108712092B

Abstract

The embodiment of the invention discloses a kind of methods that holding double winding peak point current is constant, including：Chip passes through Rcs resistance samplings, obtain 50%VLIM peak-current signals, it is compared using comparator, obtained result is sent into IPK Loop peak point currents and is calculated in loop, loop is calculated by IPK Loop peak point currents to calculate, result TCX is sent into Logic logic modules, then by the control of Storage Time Control storage times control circuit and Drive drive modules, to achieve the purpose that be precisely controlled chip peak point current.The method for keeping double winding peak point current constant of the present invention can ensure that double winding peak point current is constant in the case where can't see inductive current.

Description

A method of keep double winding peak point current constant

Technical field

The present invention relates to a kind of holding constant method of peak point current more particularly to a kind of holding double winding peak point current is constant Method.

Background technology

In traditional double winding ACDC (exchange turns DC converter), since the VCC capacitances of chip need periodically Energy is supplemented by inductive current, causes actual peak point current bigger than what chip detected, chip tends not to accurate pre- The peak point current of inductance is counted, the size of peak point current and the various characteristics of transformer are directly related, such as maximum power, constant electricity The design etc. of stream, transformer ensures the constant significant of peak point current so in the case where can't see maximum current.

Invention content

Technical problem to be solved of the embodiment of the present invention is, in traditional double winding ACDC, can't see In the case of maximum current, a kind of the problem of how ensureing peak point current, it is proposed that side for keeping double winding peak point current constant Method.

In order to solve the above-mentioned technical problem, an embodiment of the present invention provides a kind of sides that holding double winding peak point current is constant Method, the constant method of the holding double winding peak point current include：

Chip is obtained 50%VLIM peak-current signals, is compared using comparator, obtained by Rcs resistance samplings Result be sent into IPK Loop peak point currents calculate loop in, by IPK Loop peak point currents calculate loop calculate, by result TCX is sent into Logic logic modules, then passes through Storage Time Control storage times control circuits and Drive The control of drive module, to achieve the purpose that be precisely controlled chip peak point current.

Wherein, the 50%VLIM of chip is the arbitrary proportion less than 100%, as long as calculating ring with IPK Loop peak point currents The amplification factor on road matches.

Wherein, the 50%VLIM of chip is 75%ILIM or 50%ILIM or 25%ILIM or 10%ILIM.

Wherein, the generation of the 50%VLIM of chip is by directly using sense resistance or using the sense of switching tube M1 Fet。

Wherein, IPK Loop peak point currents calculate loop and are not limited only to use capacitance, switch the form with comparator, as long as It realizes and the information of voltage is converted into correct time information.

Wherein, comparator circuit speed in frequency is 100KHz.

Implement the embodiment of the present invention, has the advantages that：The side for keeping double winding peak point current constant of the present invention Method can ensure that double winding peak point current is constant in the case where can't see inductive current.

Description of the drawings

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with Obtain other attached drawings according to these attached drawings.

Fig. 1 is the circuit structure diagram provided by the invention for keeping the constant method of double winding peak point current；

Fig. 2 is the electrical block diagram of the IPK Loop peak point currents calculating loop in Fig. 1；

Fig. 3 is the corresponding oscillograms of Fig. 2；

Fig. 4 is the electrical block diagram of the Logic logic modules in Fig. 1；

Fig. 5 is the electrical block diagram of the Storage Time Control storage time control circuits in Fig. 1.

Specific implementation mode

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

The present invention provides a kind of methods that holding double winding peak point current is constant, please participate in Fig. 1, Fig. 1 carries for the present invention The circuit structure diagram of the holding constant method of double winding peak point current of confession.The constant method packet of the holding double winding peak point current It includes：

Wherein, the 50%VLIM of chip is the arbitrary proportion less than 100%, as long as calculating ring with IPK Loop peak point currents The amplification factor on road matches, for example, 75%ILIM or 50%ILIM or 25%ILIM or 10%ILIM.VLIM is indicated Peak inrush current, ILIM indicate peak point current.

In the present embodiment, the generation of the 50%VLIM of chip is opened preferably by direct using sense resistance or use Close the sense Fet of pipe M1.IPK Loop peak point currents calculate loop and are not limited only to use capacitance, the shape of switch and comparator The information of voltage is converted to correct time information by formula as long as realizing, if selecting comparator, comparator circuit speed Degree frequency is 100KHz.

Fig. 2 is referred to, Fig. 2 is the electrical block diagram that IPK Loop peak point currents calculate loop.In Switching Power Supply It charges to C1 capacitances in pwm signal to the time of 50%ILIM, in 50%ILIM to TCX, charges to C2 capacitances, It is exactly final peak by comparing device output signal Tcx when identical to two capacitance voltages in this way as C1 with C2 sizes It is worth electric current.Fig. 3 is referred to, Fig. 3 is the corresponding oscillograms of Fig. 2.

Fig. 4 is referred to, Fig. 4 is the electrical block diagram of Logic logic modules.It is triggered using a RS flipflop Device, when the rising edge of oscillator OSC comes, setting pwm signal be height, when the rising edge of TCX comes, resetting pwm signal be it is low, Close the switching signal of entire chip.

Fig. 5 is referred to, Fig. 5 is the circuit structure of the Storage Time Control storage time control circuits in Fig. 1 Schematic diagram.

Left-hand component is EAMP error amplifiers, and wherein PM1, PM2, NM1, NM2, NM3 and tail current source Iss form one Simple OTA amplifiers, PM1 and PM2 are the load that input difference connects pipe, NM1, NM2 for diode, NM2 and NM3 compositions Current mirror form exports a current source directly proportional with REF1-VCCS eventually by NM3, can be counted with expression It calculates：

Iout=Gm×[REF1-VCCS]

Wherein：GM is mutual conductance of the input to pipe, i.e. PM1 in figure, the mutual conductance of PM2.

Fig. 5 right-hand components are Storage Time Control storage time control circuits, and wherein PM5, PM6 form one Current mirror, for receiving the Iout of EAMP (error amplifier) outputs, I0 is a fixed current, when Iout=0, is used Maximum storage time is set, and wherein NM4 is switched as one, when PWM failing edges, switch is closed, and Iout and I0 are simultaneously It charges to capacitance C1, when the voltage above C1 reaches the voltage of REF2, PWMBD outputs are low, so Δ t can be used down Face expression formula calculates：

It needs separately to illustrate, the IPK Loop peak point currents in Fig. 2 calculate the electrical block diagram of loop, Fig. 4 In Logic logic modules electrical block diagram, the Storage Time Control storage time control circuits in Fig. 5 Electrical block diagram be the present invention one of which embodiment, in other embodiments, as long as reaching identical Purpose also belongs to protection scope of the present invention.

The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention With within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention god.

Claims

1. a kind of method for keeping double winding peak point current constant, which is characterized in that the holding double winding peak point current is constant Method include：

Chip is obtained 50%VLIM peak-current signals, is compared using comparator by Rcs resistance samplings, obtained knot Fruit is sent into IPK Loop peak point currents and calculates in loop, and calculating loop by IPK Loop peak point currents calculates, and result TCX is sent Enter in Logic logic modules, mould is then driven by Storage Time Control storage times control circuits and Drive The control of block, to achieve the purpose that be precisely controlled chip peak point current.

2. the method according to claim 1 for keeping double winding peak point current constant, which is characterized in that the chip 50%VLIM is the arbitrary proportion less than 100%, as long as the amplification factor for calculating loop with IPK Loop peak point currents matches .

3. the method according to claim 2 for keeping double winding peak point current constant, which is characterized in that the chip 50%VLIM is 75%ILIM or 50%ILIM or 25%ILIM or 10%ILIM.

4. the method according to claim 1 for keeping double winding peak point current constant, which is characterized in that the chip The generation of 50%VLIM is by directly using sense resistance or using the sense Fet of switching tube M1.

5. the method according to claim 1 for keeping double winding peak point current constant, which is characterized in that the IPK Loop Peak point current calculates loop and is not limited only to that capacitance, the form of switch and comparator is used to convert the information of voltage as long as realizing For accurate temporal information.

6. the method according to claim 5 for keeping double winding peak point current constant, which is characterized in that the comparator electricity Road speed in frequency is 100KHz.