CN108710318A - A kind of computer system monitoring circuit - Google Patents
A kind of computer system monitoring circuit Download PDFInfo
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- CN108710318A CN108710318A CN201810322769.3A CN201810322769A CN108710318A CN 108710318 A CN108710318 A CN 108710318A CN 201810322769 A CN201810322769 A CN 201810322769A CN 108710318 A CN108710318 A CN 108710318A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21119—Circuit for signal adaption, voltage level shift, filter noise
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Debugging And Monitoring (AREA)
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Abstract
The invention discloses a kind of computer systems to monitor circuit, including arm processor, FPGA, memory, voltage and temperature measuring circuit；Arm processor, voltage and temperature measuring circuit have communication connection with FPGA；Memory is connect with arm processor and FPGA respectively；Arm processor is used to acquire the operation conditions and recording equipment fault message of the voltage value of mainboard battery, mainboard and its external equipment；FPGA is used to acquire the working time of mainboard, booting number, mainboard temperature information, the voltage value of each chip of mainboard and recording power exception information；Arm processor generates fault indication signal according to device fault information or abnormity of power supply information；And for generating corresponding warning information according to device fault information or abnormity of power supply information and being sent to processor platform by FPGA；The present invention, which can be realized, to be monitored in real time and records to the mainboard of computer system and its health information of peripheral equipment, is that the debugging for the computer system newly ground and improvement are improved and provide reference data.
Description
Technical field
The invention belongs to design of computer hardware technical fields, flat applied to Loongson processor more particularly, to one kind
The monitoring circuit of platform computer system.
Background technology
For a long time, China's computing device largely uses external software and hardware product, high-performance processor and operating system etc.
Core technology is completely enclosed to us, and technology is under one's control and there are security risks.Especially in terms of defence and military, to avoid
It is limited by ingress processor in wartime, develops and has become a urgent and necessary requirement using domestic processor.With state
Produce processor chips it is fast-developing with it is gradual perfect, ingress processor shoulder to shoulder is had begun in performance, in national defence, work
The application of industry production field is also increasingly wider, such as the Loongson processor of Godson company exploitation is with its entirely autonomous intellectual property and excellent
The opposite sex can obtain the concern of some scientific research institutions, start to research and develop the various general and special computer based on Loongson processor.
Although Godson company provides the exemplary computer scheme for reference, Loongson processor due to issuing time not
Long, the peripheral chip that can be adapted to it and the domestic operating system based on linux kernel are limited so that newly-designed to be based on Godson
All there is certain risk on hardware and software in the computer system of processor.Therefore, it is necessary to the Loongson processor newly ground
The working condition of platform computer system is monitored in real time and is recorded, to reinforce the stability of computer system, improving operation
System and the matching of hardware platform provide technical basis.
Invention content
For at least one defect or Improvement requirement of the prior art, the present invention provides a kind of computer system monitoring electricity
Road, the mainboard temperature of computer system, mainboard voltage, system event, the system failure and external equipment information are monitored and
Record, reference data is provided for the debugging and improvement of computer system.
To achieve the above object, according to one aspect of the present invention, a kind of computer system monitoring circuit is provided, including
Arm processor, FPGA, memory, voltage and temperature measuring circuit；Arm processor, voltage and temperature measuring circuit are and FPGA
With communication connection；Memory is connect with arm processor and FPGA respectively；
Arm processor is connected with the power circuit on CPCI mainboards, the voltage value for acquiring mainboard battery；And for leading to
It crosses IPMB buses with the sensor of external equipment or I2C smart machines to be connected, to acquire the operation shape of mainboard and its external equipment
Condition and recording equipment fault message；
FPGA is used to acquire working time and the booting number of mainboard；And for being acquired by voltage and temperature measuring circuit
The voltage value and recording power exception information of each chip of mainboard temperature information, mainboard；Arm processor according to device fault information or
Abnormity of power supply information generates fault indication signal；And for generating corresponding announcement according to device fault information or abnormity of power supply information
Alert information is simultaneously sent to processor platform by FPGA；
Memory is used to store the various parameters information of arm processor and FPGA acquisitions.
Preferably, above computer system monitoring circuit further includes being connected with FPGA LED circuit by I/O interfaces, LED
The fault indication signal control indicator light that circuit is used to be transmitted according to FPGA is lighted to indicate fault message.
Preferably, above computer system monitoring circuit, monitoring circuit is by the 3.3V power supplys independently of processor platform
Power supply.
Preferably, above computer system monitoring circuit further includes bus buffer and level shifting circuit；
One end of bus buffer is connected by TWI interfaces with arm processor, and the first of the other end and level shifting circuit
End is connected, and the second end of level shifting circuit passes through IPMB buses and external sensor and I2C smart machines are connected；Level conversion
The 3.3V level conversions that circuit is used to monitor IPMB buses inside circuit are the 5V level of external IP MB buses.
Preferably, above computer system monitoring circuit, arm processor further include UART interface and jtag interface, outside
Portion's serial equipment mutually communicates letter by UART interface and arm processor；Host computer carries out arm processor by jtag interface
Programming and debugging.
Preferably, above computer system monitoring circuit, FPGA are additionally operable to send out booting under the control of arm processor
Signal or reset signal realize the soft booting and warm reset of processor platform to processor platform.
Preferably, above computer system monitoring circuit, level shifting circuit include metal-oxide-semiconductor Q2, Q3, diode D1,
D2, D3, D4, D5, resistance R4, R5, R6, R7；
The source electrode of metal-oxide-semiconductor Q2 is connected with the clock bus of IPMB buses inside monitoring circuit, drain electrode and monitoring circuit external
The clock bus of IPMB buses is connected；The source electrode of metal-oxide-semiconductor Q3 is connected with the data/address bus of IPMB buses inside monitoring circuit, drains
It is connected with the data/address bus of monitoring circuit external IPMB buses, the grid of metal-oxide-semiconductor Q2 and NMOS tube Q3 connect 3.3V power supplys；Resistance R4
With the grid and sources connected in parallel of metal-oxide-semiconductor Q3, the grid and sources connected in parallel of resistance R5 and metal-oxide-semiconductor Q2；The anode and MOS of diode D1
The drain electrode of pipe Q2 is connected, and cathode connects 5V power supplys, and resistance R6 is arranged between diode D1 and metal-oxide-semiconductor Q2；The anode of diode D5
It is connected with the drain electrode of metal-oxide-semiconductor Q3, cathode connects 5V power supplys, and resistance R7 is arranged between diode D1 and metal-oxide-semiconductor Q3；Metal-oxide-semiconductor Q2 and
Diode D2 and D3 are connected between the drain electrode of metal-oxide-semiconductor Q3, the anode of diode D2 is connected with the drain electrode of metal-oxide-semiconductor Q2, cathode and two
The cathode of pole pipe D3 is connected, and the anode of diode D3 is connected with the drain electrode of metal-oxide-semiconductor Q3, the tie point of diode D2 and D3 and two poles
The cathode of pipe D4 is connected, the plus earth of diode D4.
Preferably, above computer system monitoring circuit, voltage and temperature measuring circuit include temperature-sensitive triode Q1, electricity
Hold C1, C2, resistance R1, R2, R3 and power monitoring chip U1；
The first voltage input pin of access power monitoring chip U1 after the collector of temperature-sensitive triode Q1 is connected with base stage,
Emitter accesses the second voltage input pin of power monitoring chip U1；First voltage input pin is as voltage monitoring channel
Anode, second voltage input pin constitute the cathode in voltage monitoring channel；The base stage and hair of capacitance C2 and temperature-sensitive triode Q1
Emitter-base bandgap grading is in parallel；One end of resistance R1, R2, R3 are connected with the address pin of power monitoring chip U1, the other end of resistance R1, R2
Connect 3.3V power supplys, another termination protecting field of resistance R3；A termination 3.3V power supplys of capacitance C1, another termination protecting field.
Preferably, above computer system monitoring circuit, arm processor use at the ATSAM4S16C of ATEML companies
Device chip is managed, FPGA uses the LCMX02-1200 chips of LATTICE companies.
Preferably, above computer system monitoring circuit, power monitoring chip U1 use the LTC2991CMS of LT companies
Chip；Temperature-sensitive triode Q1 incudes original paper using MMBT3904.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, can obtain down and show
Beneficial effect：
(1) computer system provided by the invention monitors circuit, is realized to department of computer science by arm processor combination FPGA
The operation of the mainboard cell voltage, each chip voltage, mainboard temperature, System production time, booting number and peripheral equipment of system
The information such as situation are monitored in real time and are recorded, and are that the debugging for the computer system newly ground and improvement are improved and provide reference data；
In addition, the program by changing arm processor and FPGA, it is convenient to carry out Function Extension to monitoring circuit.
(2) computer system provided by the invention monitors circuit, and arm processor is used to provide firmly for information collection and transmission
Part supports that FPGA compensates for the few defect of arm processor I/O pin, extends the function of monitoring circuit, low in energy consumption with operation,
The advantages that stabilization, signal acquisition speed is fast, and functional interface is resourceful；FPGA is articulated on the lpc bus of Godson 2H, in addition to can
It realizes processor platform and monitors the communication between circuit, also act as the Function Extension device of processor platform, improve
The utilization rate of FPGA.
Description of the drawings
Fig. 1 is the integrated connection block diagram of monitoring circuit and Loongson processor computer system provided in an embodiment of the present invention；
Fig. 2 is the logic diagram of monitoring circuit provided in an embodiment of the present invention；
Fig. 3 is the circuit diagram of IPMB bus levels conversion circuit provided in an embodiment of the present invention；
Fig. 4 is the circuit diagram of voltage and temperature measuring circuit provided in an embodiment of the present invention.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
It does not constitute a conflict with each other and can be combined with each other.
Fig. 1 is computer system monitoring circuit provided in an embodiment of the present invention and dragon chip processor platform computer system
It is connected block diagram；As shown in Figure 1, dragon chip processor platform computer system includes a Godson computer CPCI mainboard, with
And several CPCI functional cards being connected with Godson computer CPCI mainboards by cpci bus；Godson computer CPCI mainboards
Include the dragon chip processor platform being made of double Godson 3A1500 chips and Godson 2H bridge pieces, and is supplied for dragon chip processor platform
The power circuit of electricity；
Monitoring circuit is connected by LPC interfaces with dragon chip processor platform, and the sensing of IPMB buses and external equipment is passed through
Device and I2C smart machines are connected, and monitoring circuit is connect with power circuit to detect the voltage of mainboard battery.
Fig. 2 is the logic diagram of computer system monitoring circuit provided in an embodiment of the present invention；As shown in Fig. 2, of the invention
The monitoring circuit of offer includes arm processor, FPGA, FLASH, voltage and temperature measuring circuit；
It is connected by data/address bus, address bus, GPIO buses and spi bus between arm processor and FPGA；Voltage with
Temperature measuring circuit passes through I2C buses are connected with FPGA；FLASH is connected by spi bus with arm processor and FPGA；FPGA
It is connected with the Godson 2H bridge pieces in dragon chip processor platform by LPC interfaces；
Arm processor is connected as main control unit with the power circuit on CPCI mainboards, the electricity for acquiring mainboard battery
Pressure value, the function are realized by the A/D module integrated in arm processor；Arm processor passes through FPGA and LPC interface dragons
Core 2H bridge pieces realize that the data exchange between processor platform, FPGA play bus protocol conversion；In the present embodiment
Arm processor uses the ATSAM4S16C processor chips of ATEML companies.
Voltage is used to monitor the voltage value of each chip of mainboard with temperature measuring circuit, such as mainboard 5V supply voltages, processor
Kernel 1.15V voltages, exterior I/O 3.3V voltages etc.；It is additionally operable to measure mainboard temperature simultaneously；FPGA is surveyed by voltage and temperature
The voltage value that circuit obtains mainboard temperature information, each chip is measured, under-voltage, over-pressed information is recorded and sends it to arm processor,
FPGA uses the LCMX02-1200 chips of LATTICE companies.
Further, which further includes bus buffer and level shifting circuit；
Arm processor is connected by IPMB buses with the sensor of external equipment, to acquire the operation conditions of external equipment
Information simultaneously records fault message, for example, arm processor can pass through the temperature of IPMB bus monitorings and acquisition fan, rotating speed, voltage
And fault message；Various I2C smart machines such as EEPROM etc. is in communication with each other also by IPMB buses with arm processor；
Monitoring circuit use the 3.3V power supplys independently of processor platform, with external equipment sensor and I2C intelligence
When energy equipment communication, needing 3.3V power supplys being converted to 5V power supplys, arm processor is connected by TWI Interface & Bus buffers,
Bus buffer connects level shifting circuit, and level shifting circuit passes through IPMB buses and external sensor and I2C smart machines
It is connected, ARM sensors and external sensor and I is realized with this2The communication connection of C smart machines；Bus buffer selects LT public
The LTC4307IMS8 chips of department.
Further, which further includes the LED circuit being connected with FPGA by I/O interfaces, which is used for
Control indicator light instruction power information and device fault information；
When processor platform breaks down, such as when the failure of over-pressed or under-voltage, fan occurs in mainboard voltage, ARM
Processor generates fault indication signal according to fault message and sends it to FPGA, and FPGA is controlled according to fault indication signal
LED circuit lights indicator light, realizes the instruction of the information such as power supply, failure；On the other hand, arm processor is given birth to according to fault message
At corresponding warning information and processor platform is sent to by FPGA, display alarm in the monitoring programme on processor platform
Information.
By the parameters information storage of acquisition in the FLASH that power down is not lost, computer system can lead to ARM sensors
It crosses upper layer software (applications) and checks each item data being stored in FLASH；FALSH uses the W25Q64FVSIG chips of winbond companies.
Further, arm processor further includes UART interface and jtag interface；Arm processor is by UART interface and outside
Portion's serial equipment is connected, such as the computer with RS-232 serial ports, modem etc., external serial equipment pass through UART interface
It is communicated with arm processor；
When monitoring circuit by UART interface connection MODEM access network based on ethernet, remote computer can pass through real-time performance
The long-range soft booting or warm reset of processor platform, FPGA sent out under the control of arm processor booting (PWRBTN) signal or
(SYSRST) signal is resetted to processor platform, realizes the soft booting and warm reset of dragon chip processor platform；
Arm processor is connected by jtag interface with host computer, and host computer compiles arm processor by jtag interface
Journey and debugging.
Monitoring circuit is independently of the control system except processor platform, uses independently of processor platform
3.3V power supplys after processor platform power-off is out of service, as long as the power supply of monitoring circuit is not disconnected, monitor circuit by continuous service,
External serial equipment still may have access to monitoring circuit at this time；The present invention is realized using arm processor combination FPGA to Loongson processor
The monitoring of platform computer system, by the program for changing arm processor and FPGA, it is convenient to which function is carried out to monitoring circuit
Extension.
Fig. 3 is the circuit diagram of level shifting circuit provided in an embodiment of the present invention；Level shifting circuit will be for that will monitor electricity
The 3.3V level conversions of IPMB buses are the 5V level of external IP MB buses inside road, as shown in figure 3, the level shifting circuit packet
Include NMOS tube Q2, Q3, diode D1, D2, D3, D4, D5, resistance R4, R5, R6, R7；
The source electrode of NMOS tube Q2 is connected with the clock bus (IPMB ALCK) of IPMB buses inside monitoring circuit, drain electrode and
The clock bus (IPMB SCL) for monitoring circuit external IPMB buses is connected；The source electrode of NMOS tube Q3 and IPMB inside monitoring circuit
The data/address bus (IPMB ADAT) of bus is connected, the data/address bus (IPMB SDA) of drain electrode and monitoring circuit external IPMB buses
It is connected；The grid of NMOS tube Q2 and NMOS tube Q3 connect 3.3V power supplys；The grid and sources connected in parallel of resistance R4 and NMOS tube Q3, resistance
The grid and sources connected in parallel of R5 and NMOS tube Q2；The anode of diode D1 is connected with the drain electrode of NMOS tube Q2, and cathode connects 5V power supplys,
Resistance R6 is arranged between diode D1 and NMOS tube Q2；The anode of diode D5 is connected with the drain electrode of NMOS tube Q3, and cathode connects
5V power supplys, resistance R7 are arranged between diode D1 and NMOS tube Q3；It is connected to two between NMOS tube Q2 and the drain electrode of NMOS tube Q3
Pole pipe D2 and D3, the anode of diode D2 are connected with the drain electrode of NMOS tube Q2, and cathode is connected with the cathode of diode D3, diode
The anode of D3 is connected with the drain electrode of NMOS tube Q3, and the tie point of diode D2 and D3 are connected with the cathode of diode D4, diode
The plus earth of D4.
It is illustrated by taking IPMB ALCK as an example, 3.3V voltages are applied to the grid of NMOS tube Q2, Q2 conductings, IPMB ALCK
Signal be output on IPMB SCL；When IPMB ALCK are high level, since 5V voltages are applied on IPMB SCL, at this time
The high level of IPMB SCL is 5V, and when IPMB ALCK are low level, IPMB SCL are similarly low level；Due to NMOS tube
One-way conduction, the state of IPMB SCL do not interfere with the state of IPMB ALCK, thus complete the level conversion of 3.3V to 5V；
Resistance R4, R5, R6, R7 mainly play metering function, and diode D2, D3, D4 are used for circuit protection.
Fig. 4 is the circuit diagram of voltage and temperature measuring circuit provided in an embodiment of the present invention；The temperature measuring circuit includes
Temperature-sensitive triode Q1, capacitance C1, C2, resistance R1, R2, R3 and power monitoring chip U1；
7 feet of access power monitoring chip U1 after the collector of temperature-sensitive triode Q1 is connected with base stage, i.e. voltage monitoring are logical
The anode in road, emitter access 8 feet of power monitoring chip, the i.e. cathode in voltage monitoring channel；Capacitance C2 and temperature-sensitive triode
The base stage and emitter of Q1 is in parallel；One end of resistance R1 is connected with the address pin 15 of power monitoring chip U1, another termination
3.3V power supplys, one end of resistance R2 are connected with the address pin 13 of power monitoring chip U1, another termination 3.3V power supplys；Resistance R3
One end be connected with the address pin 14 of power monitoring chip U1, another termination protecting field；A termination 3.3V power supplys of capacitance C1,
Another termination protecting field；Capacitance C1, C2 are played a filtering role in circuit；Power monitoring chip is set by address pin 13~15
In I2Address in C buses.
V1~V2 pins of power monitoring chip U1 are connected with 5V motherboard power supplies, and for detecting motherboard power supply voltage, V3 draws
Foot is connected with 1.15V processor cores power supplys, is used for measurement processor core voltage；V4 pins are connected with exterior I/O, for examining
Survey exterior I/O voltages.
Voltage between the collector and emitter of temperature-sensitive triode Q1 can change with the variation of temperature, power supply
Monitoring chip U1 can calculate corresponding temperature according to the variation of voltage, to realize the measurement to mainboard temperature；Power Supply Monitoring
Chip uses the LTC2991CMS chips of LT companies；Temperature-sensitive triode Q1 incudes original paper using MMBT3904.
Computer system provided by the invention monitors circuit, is realized to computer system by arm processor combination FPGA
Mainboard cell voltage, each chip voltage, mainboard temperature, System production time, booting number and peripheral equipment operation shape
The real time monitoring and record of the information such as condition information are that the debugging for the computer system newly developed and improvement are improved and provide reference number
According to；In addition, the program by changing arm processor and FPGA, it is convenient to carry out Function Extension to monitoring circuit.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all within the spirits and principles of the present invention made by all any modification, equivalent and improvement etc., should all include
Within protection scope of the present invention.
Claims (8)
1. a kind of computer system monitors circuit, which is characterized in that including arm processor, FPGA, memory, voltage and temperature
Measuring circuit；The arm processor, voltage and temperature measuring circuit have communication connection with FPGA；The memory difference
It is connect with arm processor and FPGA；
The arm processor is connected with the power circuit on CPCI mainboards, the voltage value for acquiring mainboard battery；And for leading to
Cross the sensor or I of IPMB buses and external equipment2C smart machines are connected, to acquire the operation shape of mainboard and its external equipment
Condition and recording equipment fault message；
The FPGA is used to acquire working time and the booting number of mainboard；And for passing through the voltage and temperature measuring circuit
Acquire mainboard temperature information, the voltage value of each chip of mainboard and recording power exception information；Arm processor is according to equipment event
Hinder information or abnormity of power supply information generates fault indication signal；And for according to the device fault information or abnormity of power supply information
It generates corresponding warning information and processor platform is sent to by FPGA；
The memory is used to store the various parameters information of arm processor and FPGA acquisitions.
2. computer system as described in claim 1 monitors circuit, which is characterized in that further include by I/O interfaces and FPGA
Be connected LED circuit, and the fault indication signal control indicator light that the LED circuit is used to be transmitted according to FPGA is lighted to indicate
Fault message.
3. computer system as claimed in claim 1 or 2 monitors circuit, which is characterized in that the monitoring circuit by independently of
The 3.3V power supply power supplies of processor platform.
4. computer system as claimed in claim 3 monitors circuit, which is characterized in that further include that bus buffer and level turn
Change circuit；
One end of the bus buffer is connected by TWI interfaces with arm processor, and the first of the other end and level shifting circuit
End is connected, and the second end of level shifting circuit passes through IPMB buses and external sensor and I2C smart machines are connected；
The 3.3V level conversions that the level shifting circuit is used to monitor IPMB buses inside circuit are external IP MB buses
5V level.
5. computer system as described in claim 1 or 4 monitors circuit, which is characterized in that the arm processor further includes
UART interface and jtag interface, external serial equipment are in communication with each other by the UART interface with arm processor；Host computer passes through
The jtag interface is programmed and debugs to arm processor.
6. computer system as described in claim 1 monitors circuit, which is characterized in that the FPGA is additionally operable in ARM processing
Starting-up signal or reset signal are sent out under the control of device to processor platform, realize the soft booting and warm reset of processor platform.
7. computer system as described in claim 1 monitors circuit, which is characterized in that the voltage and temperature measuring circuit packet
Include temperature-sensitive triode Q1, capacitance C1, C2, resistance R1, R2, R3 and power monitoring chip U1；
The first voltage input pin of access power monitoring chip U1 after the collector of the temperature-sensitive triode Q1 is connected with base stage,
Emitter accesses the second voltage input pin of power monitoring chip U1；The first voltage input pin and second voltage input
Pin constitutes the anode and cathode in voltage monitoring channel；The base stage and emitter of the capacitance C2 and temperature-sensitive triode Q1 is simultaneously
Connection；One end of described resistance R1, R2, R3 are connected with the address pin of power monitoring chip U1, another termination of resistance R1, R2
3.3V power supplys, another termination protecting field of resistance R3；A termination 3.3V power supplys of the capacitance C1, another termination protecting field.
8. computer system as claimed in claim 3 monitors circuit, which is characterized in that the level shifting circuit includes MOS
Pipe Q2, Q3, diode D1, D2, D3, D4, D5, resistance R4, R5, R6, R7；
The source electrode of the metal-oxide-semiconductor Q2 is connected with the clock bus of IPMB buses inside monitoring circuit, drain electrode and monitoring circuit external
The clock bus of IPMB buses is connected；The source electrode of the metal-oxide-semiconductor Q3 is connected with the data/address bus of IPMB buses inside monitoring circuit,
It drains and is connected with the data/address bus of monitoring circuit external IPMB buses, the grid of metal-oxide-semiconductor Q2 and metal-oxide-semiconductor Q3 connect 3.3V power supplys；Institute
State the grid and sources connected in parallel of resistance R4 and metal-oxide-semiconductor Q3, the grid and sources connected in parallel of the resistance R5 and metal-oxide-semiconductor Q2；Described two
The anode of pole pipe D1 is connected with the drain electrode of metal-oxide-semiconductor Q2, and cathode connects 5V power supplys, and the resistance R6 is arranged in diode D1 and metal-oxide-semiconductor
Between Q2；The anode of the diode D5 is connected with the drain electrode of metal-oxide-semiconductor Q3, and cathode connects 5V power supplys, and the resistance R7 is arranged two
Between pole pipe D1 and metal-oxide-semiconductor Q3；Diode D2 and D3, the diode are connected between the metal-oxide-semiconductor Q2 and the drain electrode of metal-oxide-semiconductor Q3
The anode of D2 is connected with the drain electrode of metal-oxide-semiconductor Q2, and cathode is connected with the cathode of diode D3, the anode and MOS of the diode D3
The drain electrode of pipe Q3 is connected, and the tie point of diode D2 and D3 are connected with the cathode of diode D4, and the anode of the diode D4 connects
Ground.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810322769.3A CN108710318B (en) | 2018-04-11 | 2018-04-11 | Computer system monitoring circuit |
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|---|---|---|---|
| CN201810322769.3A CN108710318B (en) | 2018-04-11 | 2018-04-11 | Computer system monitoring circuit |
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| CN108710318A true CN108710318A (en) | 2018-10-26 |
| CN108710318B CN108710318B (en) | 2020-01-14 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110058978A (en) * | 2019-03-22 | 2019-07-26 | 山东超越数控电子股份有限公司 | A kind of error log recording device for computer |
| CN111510510A (en) * | 2020-04-16 | 2020-08-07 | 广东盈嘉科技工程发展股份有限公司 | Method and system compatible with multiple communication interfaces |
| CN112596552A (en) * | 2020-12-29 | 2021-04-02 | 湖南博匠信息科技有限公司 | Calculation board health management method and system based on Loongson processor |
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| CN111510510A (en) * | 2020-04-16 | 2020-08-07 | 广东盈嘉科技工程发展股份有限公司 | Method and system compatible with multiple communication interfaces |
| CN112596552A (en) * | 2020-12-29 | 2021-04-02 | 湖南博匠信息科技有限公司 | Calculation board health management method and system based on Loongson processor |
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| CN108710318B (en) | 2020-01-14 |
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