CN108683426A - A kind of ECC system and memory based on BCH code - Google Patents
A kind of ECC system and memory based on BCH code Download PDFInfo
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- CN108683426A CN108683426A CN201810478220.3A CN201810478220A CN108683426A CN 108683426 A CN108683426 A CN 108683426A CN 201810478220 A CN201810478220 A CN 201810478220A CN 108683426 A CN108683426 A CN 108683426A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a kind of ECC system and memory based on BCH code, the ECC system include：BCH decoders and error correcting capability control circuit, the BCH decoders include multiple arithmetic elements；Wherein, the error correcting capability control circuit is used to control the working condition of arithmetic element in the BCH decoders according to the bit error rate of data to decode, to change the error correcting capability of the BCH decoders.The ECC system controls the working condition of arithmetic element in the BCH decoders by error correcting capability control circuit according to the bit error rate of data to decode, the quantity that circuit is opened when changing the operation of BCH decoders, it is set to only have partial circuit running in low error rate, but it remains to complete corresponding error correcting capability, while power consumption is also greatly lowered.
Description
Technical field
The present invention relates to memory technology fields, more specifically more particularly to a kind of ECC system based on BCH code and
Memory.
Background technology
With the continuous development of science and technology, various memories are widely used to daily life and work
In work, bring great convenience for people’s lives.
Based on " big data " epoch, the memory of high power capacity and low-power consumption is developing rapidly, since 3D nand flash memories exist
Enter after market within 2014, the capacity of flash memory almost can all double every year.With the increase of memory capacity, ECC (Error
Correcting Code, error checking and correction) complexity and the power consumption of system be consequently increased, and power consumption mostlys come from
ECC module.
Since error rates of data uses relatively low, the ECC module in memory chip at this time when starting in memory chip
Working efficiency is very low, and error rates of data is a very slow uphill process, that is to say, that at ECC module meeting for a long time
There are the consumption of more redundant power when the error correcting capability of unsaturated working condition, traditional ECC module is fixed and circuit is run,
The power consumption consumed for the different data of the bit error rate is essentially identical, and then just has a large amount of power consumption and be wasted.
So, it is those skilled in the art's urgent problem to be solved to carry out low-power consumption processing to ECC module.
Invention content
To solve the above problems, the present invention provides a kind of ECC system and memory based on BCH code, the ECC system are big
Amplitude reduction power consumption.
To achieve the above object, the present invention provides the following technical solutions：
A kind of ECC system based on BCH code, the ECC system include：BCH decoders and error correcting capability control circuit, institute
It includes multiple arithmetic elements to state BCH decoders；
Wherein, the error correcting capability control circuit is used to control the BCH decoders according to the bit error rate of data to decode
The working condition of middle arithmetic element, to change the error correcting capability of the BCH decoders.
Preferably, in above-mentioned ECC system, the ECC system further includes：Parameter configuration module；
Wherein, the parameter configuration module is used to configure the BCH decoders according to the error correcting capability of the BCH decoders
The operating parameter of middle arithmetic element.
Preferably, in above-mentioned ECC system, the error correcting capability control circuit is used for the bit error rate according to data to decode
The working condition for controlling arithmetic element in the BCH decoders, to change the method packet of the error correcting capability of the BCH decoders
It includes：
The bit error rate of the error correcting capability control circuit according to the data to decode controls more in the BCH decoders
Corresponding arithmetic element works in a arithmetic element, remaining arithmetic element is stopped, and is decoded with changing the BCH
The error correcting capability of device.
Preferably, in above-mentioned ECC system, the BCH decoders include multiple error correction submodules, the error correction submodule
Including at least one arithmetic element；
The error correcting capability of the error correction submodule is directly proportional to the arithmetic element number that it includes；
The big error correction submodule of error correcting capability includes at least one operation list of the small error correction submodule of error correcting capability
Member.
Preferably, in above-mentioned ECC system, the ECC system further includes：Bose-Chaudhuri-Hocquenghem Code device, the Bose-Chaudhuri-Hocquenghem Code device include
Multiple arithmetic elements；
Wherein, the error correcting capability control circuit is additionally operable to control the Bose-Chaudhuri-Hocquenghem Code according to the bit error rate of data to be encoded
The working condition of arithmetic element in device, to change the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device；
The parameter configuration module is additionally operable to configure in the Bose-Chaudhuri-Hocquenghem Code device according to the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device
The operating parameter of arithmetic element.
Preferably, in above-mentioned ECC system, the error correcting capability control circuit is used for the bit error rate according to data to be encoded
The working condition for controlling arithmetic element in the Bose-Chaudhuri-Hocquenghem Code device, to change the method packet of the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device
It includes：
The bit error rate of the error correcting capability control circuit according to the data to be encoded controls more in the Bose-Chaudhuri-Hocquenghem Code device
Corresponding arithmetic element works in a arithmetic element, remaining arithmetic element is stopped, to change the Bose-Chaudhuri-Hocquenghem Code
The error correcting capability of device.
Preferably, in above-mentioned ECC system, the Bose-Chaudhuri-Hocquenghem Code device includes multiple error correction submodules, the error correction submodule
Including at least one arithmetic element；
The error correcting capability of the error correction submodule is directly proportional to the arithmetic element number that it includes；
The big error correction submodule of error correcting capability includes at least one operation list of the small error correction submodule of error correcting capability
Member.
The present invention also provides a kind of memories, including ECC system described in any one of the above embodiments.
By foregoing description it is found that a kind of ECC system based on BCH code provided by the invention includes：It BCH decoders and entangles
Wrong capability control circuit, the BCH decoders include multiple arithmetic elements；Wherein, the error correcting capability control circuit be used for according to
The working condition that arithmetic element in the BCH decoders is controlled according to the bit error rate of data to decode, to change the BCH decoders
Error correcting capability.
The bit error rate of the ECC system by error correcting capability control circuit according to data to decode controls the BCH decoders
The working condition of middle arithmetic element, that is, the quantity that circuit is opened when changing the operation of BCH decoders, makes it only have in low error rate
Partial circuit is being run, but remains to complete corresponding error correcting capability, while power consumption is also greatly lowered.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of working environment principle schematic of ECC system in the prior art；
Fig. 2 is a kind of working environment principle schematic of the ECC system based on BCH code provided in an embodiment of the present invention；
Fig. 3 is the structure and working environment original of a kind of adjustable BCH decoders of error correcting capability provided in an embodiment of the present invention
Manage schematic diagram；
Fig. 4 is structure and the signal of working environment principle of a kind of BCH decoders integration module provided in an embodiment of the present invention
Figure；
Fig. 5 is the working environment principle schematic of another ECC system based on BCH code provided in an embodiment of the present invention；
Fig. 6 is the structure and working environment original of a kind of adjustable Bose-Chaudhuri-Hocquenghem Code device of error correcting capability provided in an embodiment of the present invention
Manage schematic diagram；
Fig. 7 is structure and the signal of working environment principle of a kind of Bose-Chaudhuri-Hocquenghem Code device integration module provided in an embodiment of the present invention
Figure；
Fig. 8 is a kind of electrical block diagram for the Bose-Chaudhuri-Hocquenghem Code device that serial error correcting capability can configure.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, original information bits data needed before being stored in mass storage 15 first by ECC system 11 in BCH
Encoder 12 is encoded according to the corresponding control signal that controller 14 is sent, and then mass storage 15 is according to control
Coded data is stored in its designated position by the corresponding control signal that device 14 is sent.Similarly, it is taken from mass storage 15
When going out data, it is also desirable to be treated according to the corresponding control signal that controller 14 is sent by BCH decoders 13 in ECC system 11
Decoding data is decoded, and corrects restoring data.
Wherein, mass storage 15 includes but is not limited to NAND FLASH memories.
Based on this, traditional Bose-Chaudhuri-Hocquenghem Code device 12 and BCH decoders 13 are substantially and are carried out according to the index set in advance
Work, can not arbitrarily adjust error correcting capability, therefore change of power consumption is little in the case of the bit error rate difference of data.But
With the increase of 13 error correcting capability of traditional Bose-Chaudhuri-Hocquenghem Code device 12 and BCH decoders, 11 power consumption of ECC system also becomes larger, thus
It is found that the fixed ECC system of error correcting capability underaction on optimised power consumption.
For example, the data storing reliability of the storage unit of flash chip can be with the increase of program/erase cycle times
And it is deteriorated, that is to say, that it is of less demanding to ECC system error correcting capability when the bit error rate is very low at the initial stage that chip uses,
ECC system need not be in saturated.
Based on the above issues, the present invention provides a kind of ECC system based on BCH code, which considerably reduces
Power consumption.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
Embodiment one
With reference to figure 2, Fig. 2 is that a kind of working environment principle of the ECC system based on BCH code provided in an embodiment of the present invention is shown
It is intended to, the ECC system 21 includes：BCH decoders 23 and error correcting capability control circuit 26, the BCH decoders 23 include more
A arithmetic element.
Wherein, the error correcting capability control circuit 26 is used to control the BCH decodings according to the bit error rate of data to decode
The working condition of arithmetic element in device 23, to change the error correcting capability of the BCH decoders 23.
That is, the bit error rate of the error correcting capability control circuit 26 according to the data to decode, controls the BCH
Corresponding arithmetic element works in multiple arithmetic elements in decoder 23, remaining arithmetic element is stopped, to change
Become the error correcting capability of the BCH decoders 23.
Specifically, for according to 23 characteristic of BCH decoders, as long as the bit error rate of data is not above its error correcting capability all
The resource that can be corrected, and be consumed required for the BCH decoders 23 of its error correction procedure, only has with the error correcting capability of setting
It closes, therefore the ECC system 21 is transported for the different bit error rates come Selection and call accordingly by the way that error correcting capability control circuit 26 is arranged
Unit is calculated to change the error correcting capability of BCH decoders 23, the arithmetic element called when to reduce low error rate makes ECC systems
Some is in running order for system 21, and then effectively reduces power consumption.
As shown in Fig. 2, the ECC system 21 further includes：The fixed Bose-Chaudhuri-Hocquenghem Code device 22 of error correcting capability, the Bose-Chaudhuri-Hocquenghem Code device
22 are realized according to actual conditions using the fixed mode of maximum error correcting capability.
Based on the embodiment of the present invention one, the concrete operating principle of ECC system is as follows：
As shown in Fig. 2, original information bits data are first consolidated by use maximum error correcting capability before being stored in mass storage 25
Fixed Bose-Chaudhuri-Hocquenghem Code device 22 is encoded according to the corresponding control signal that controller 24 is sent, then mass storage 25
Coded data is stored in its designated position by the corresponding control signal sent according to controller 24.Similarly, from massive store
When taking out data in device 25, controller 24 is sent accordingly according to the bit error rate of data to decode to error correcting capability control circuit 26
Signal and mode select signal are controlled, enters corresponding error correction to control BCH decoders 23 by error correcting capability control circuit 26
Ability mode is decoded data to decode, and corrects restoring data.
It follows that Bose-Chaudhuri-Hocquenghem Code device 22 is realized using the fixed mode of maximum error correcting capability first, make it to any error code
The data of rate can be carried out encoding operation, and during decoding, the error correcting capability of BCH decoders 23 can be according to number to be decoded
According to the bit error rate configured, the arithmetic element called when to reduce low error rate, make ECC system only some be in
Working condition, and then effectively reduce power consumption.
Further, the arithmetic element to work in the big BCH decoders 23 of 21 error correcting capability of the ECC system includes
Or part includes the arithmetic element to work in the small BCH decoders 23 of error correcting capability, that is to say, that the BCH decoders
23 include multiple error correction submodules, and the error correction submodule includes at least one arithmetic element；The error correction submodule
Error correcting capability is directly proportional to the arithmetic element number that it includes；The big error correction submodule of error correcting capability, which includes that error correcting capability is small, to be entangled
At least one arithmetic element of wrong submodule..
Specifically, as shown in figure 3, according to the structure of BCH decoders 23, it is weight to have many arithmetic elements during decoding
It appears again existing, only configures parameter difference, therefore the mode of arithmetic element multiplexing may be used, i.e., BCH when error correcting capability is T
The arithmetic element to work in decoder 23 will be multiplexed the operation to work in BCH decoders 23 when error correcting capability is T/2, T/4 or T/8
Unit.That is, during improving error correcting capability, only increasing a small amount of logic control can realize that BCH decoders 23 entangle
The configurable function of wrong ability, while 21 power consumption of ECC system is greatly lowered in low error rate, also, pass through multiplexing
Arithmetic element will not make chip area increase.
It further, i.e., will be more as shown in figure 4, the BCH decoders 23 can be replaced BCH decoders integration module 41
Kind of different BCH decoders of fixed error correcting capability are integrally disposed together (such as to be entangled the BCH decoders ... that error correcting capability is x
The decoder that BCH decoders ... the error correcting capability that wrong ability is y is z integrates), by configuration control signal, with selection
The corresponding BCH decoders of different error correcting capabilities work.
It should be noted that the division about error correcting capability T/2, T/4, T/8 and T is in embodiments of the present invention only to lift
The form of example embodies, and is not construed as limiting.
Based on this, as shown in figure 3, the ECC system 21 further includes：Parameter configuration module 27.
Wherein, the parameter configuration module 27 is used to configure the BCH according to the error correcting capability of the BCH decoders 23 and translate
The operating parameter of arithmetic element in code device 23.
Specifically, the error correcting capability control circuit 26 sends parameter configuration instruction to the parameter configuration module 27, with
The parameter configuration module 27 is set to configure the operating parameter of corresponding arithmetic element in the BCH decoders 23, institute
The error correcting capability that parameter configuration instruction is stated according to the BCH decoders 23 generates.
That is, by hardware scheduling and configuration adjustment data trend, changing the circuit structure of the BCH decoders and correcting and transport
The operations such as result are calculated, to reach the different error correcting capabilities of the BCH decoders.
It should be noted that the parameter configuration module 27 include but is not limited in FPGA " the programmable inputs of IBO are defeated
Go out unit ", simple connecting line that not can configure etc. can also be made.
Embodiment two
Based on the above embodiment of the present invention one, as shown in figure 5, Fig. 5 is provided in an embodiment of the present invention another based on BCH
The working environment principle schematic of the ECC system of code, the ECC system 31 include：BCH decoders 23 and error correcting capability control electricity
Road 26, the BCH decoders 23 include multiple arithmetic elements.
Wherein, the error correcting capability control circuit 26 is used to control the BCH decodings according to the bit error rate of data to decode
The working condition of arithmetic element in device 23, to change the error correcting capability of the BCH decoders 23.
That is, the bit error rate of the error correcting capability control circuit 26 according to the data to decode, controls the BCH
Corresponding arithmetic element works in multiple arithmetic elements in decoder 23, remaining arithmetic element is stopped, to change
Become the error correcting capability of the BCH decoders 23.
Specifically, for according to 23 characteristic of BCH decoders, as long as the bit error rate of data is not above its error correcting capability all
The resource that can be corrected, and be consumed required for the BCH decoders 23 of its error correction procedure, only has with the error correcting capability of setting
It closes, therefore the ECC system 31 is by being arranged error correcting capability control circuit for the different bit error rates come the corresponding operation of Selection and call
Unit changes the error correcting capability of BCH decoders 23, and the arithmetic element called when to reduce low error rate makes ECC system
31 some is in running order, and then effectively reduces power consumption.
As shown in figure 5, the ECC system 31 further includes：Bose-Chaudhuri-Hocquenghem Code device 32, the Bose-Chaudhuri-Hocquenghem Code device include multiple operation lists
Member.
Wherein, the error correcting capability control circuit 26 is additionally operable to the error code according to data to be encoded (original information bits data)
Rate controls the working condition of arithmetic element in the Bose-Chaudhuri-Hocquenghem Code device 32, to change the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device 32.
That is, the bit error rate of the error correcting capability control circuit 26 according to the data to be encoded, controls the BCH
Corresponding arithmetic element works in multiple arithmetic elements in encoder 32, remaining arithmetic element is stopped, to change
Become the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device 32.
Specifically, for according to 32 characteristic of Bose-Chaudhuri-Hocquenghem Code device, as long as the bit error rate of data is not above its error correcting capability all
The resource that can be corrected, and be consumed required for the Bose-Chaudhuri-Hocquenghem Code device 32 of its error correction procedure, only has with the error correcting capability of setting
It closes, therefore the ECC system 31 is transported for the different bit error rates come Selection and call accordingly by the way that error correcting capability control circuit 26 is arranged
Unit is calculated to change the error correcting capability of Bose-Chaudhuri-Hocquenghem Code device 32, the arithmetic element called when to reduce low error rate makes ECC systems
Some is in running order for system, and then effectively reduces power consumption.
Based on the embodiment of the present invention two, the concrete operating principle of ECC system is as follows：
As shown in figure 5, original information bits data, when being stored in mass storage 25, controller 24 is according to original information bits
The bit error rate of data sends corresponding control signal and mode select signal to error correcting capability control circuit 26, to pass through error correction energy
Power control circuit 26 controls Bose-Chaudhuri-Hocquenghem Code device 32 and enters corresponding error correcting capability pattern, is encoded to original information bits data, so
Coded data is stored in its designated position by the corresponding control signal that mass storage 25 is sent according to controller 24 afterwards.Together
Reason, when taking out data from mass storage 25, controller 24 is controlled according to the bit error rate of data to decode to error correcting capability
Circuit 26 sends corresponding control signal and mode select signal, to control BCH decoders by error correcting capability control circuit 26
23 enter corresponding error correcting capability pattern, are decoded to data to decode, and correct restoring data.
It follows that in an encoding process, the error correcting capability of Bose-Chaudhuri-Hocquenghem Code device 32 can be according to the mistake of original information bits data
Code check is configured, and during decoding, the error correcting capability of BCH decoders 23 can be carried out according to the bit error rate of data to decode
Configuration, the arithmetic element that Bose-Chaudhuri-Hocquenghem Code device 32 and BCH decoders 23 are called when to reduce low error rate make ECC system 31
Some is in running order, and then effectively reduces power consumption.
Further, the arithmetic element to work in the big Bose-Chaudhuri-Hocquenghem Code device 32 of 31 error correcting capability of the ECC system includes
Or part includes the arithmetic element to work in the small Bose-Chaudhuri-Hocquenghem Code device 32 of error correcting capability, 31 error correcting capability of the ECC system is big
The BCH decoders 23 in the arithmetic element that works include or part includes in the small BCH decoders 23 of error correcting capability
The arithmetic element of work, that is to say, that the Bose-Chaudhuri-Hocquenghem Code device 32 includes multiple error correction submodules, and the error correction submodule includes
At least one arithmetic element；The error correcting capability of the error correction submodule is directly proportional to the arithmetic element number that it includes；It entangles
The big error correction submodule of wrong ability includes at least one arithmetic element of the small error correction submodule of error correcting capability.Similarly, institute
It includes multiple error correction submodules to state BCH decoders 23, and the error correction submodule includes at least one arithmetic element；It is described to entangle
The error correcting capability of wrong submodule is directly proportional to the arithmetic element number that it includes；The big error correction submodule of error correcting capability includes error correction
At least one arithmetic element of the small error correction submodule of ability.
Specifically, as shown in Figure 3 and Figure 6, according to the structure of Bose-Chaudhuri-Hocquenghem Code device 32 and BCH decoders 23, in cataloged procedure and
There are many arithmetic elements to repeat during decoding, only configures parameter difference, therefore it is multiple that arithmetic element may be used
Mode, i.e., the arithmetic element to work in the Bose-Chaudhuri-Hocquenghem Code device 32 when error correcting capability is T are T/2, T/4 by error correcting capability is multiplexed
Or the arithmetic element to work in Bose-Chaudhuri-Hocquenghem Code device 32 when T/8, the arithmetic element that works in the BCH decoders 23 when error correcting capability is T
The arithmetic element to work in BCH decoders 23 when error correcting capability is T/2, T/4 or T/8 will be multiplexed.That is, improving error correction
During ability, only increasing a small amount of logic control can realize that Bose-Chaudhuri-Hocquenghem Code device 32 and 23 error correcting capability of BCH decoders are configurable
Function, while being greatly lowered 31 power consumption of ECC system in low error rate, also, by being multiplexed arithmetic element, will not
So that chip area increases.
Further, as shown in figs. 4 and 7, the BCH decoders 23 can be replaced BCH decoders integration module 41, i.e.,
By the different BCH decoders of a variety of fixed error correcting capabilities it is integrally disposed together (such as by error correcting capability be x BCH decode
The decoder that BCH decoders ... the error correcting capability that device ... error correcting capability is y is z integrates), by configuration control signal,
To select the corresponding BCH decoders of different error correcting capabilities to work.Similarly, the Bose-Chaudhuri-Hocquenghem Code device can also replace with BCH volumes
Code device integration module 71, i.e., it is the different Bose-Chaudhuri-Hocquenghem Code device of a variety of fixed error correcting capabilities is integrally disposed together (such as by error correction energy
The encoder that Bose-Chaudhuri-Hocquenghem Code device ... the error correcting capability that Bose-Chaudhuri-Hocquenghem Code device ... the error correcting capability that power is x is y is z integrates), pass through
Configuration control signal, to select the corresponding Bose-Chaudhuri-Hocquenghem Code device of different error correcting capabilities to work.
It should be noted that the division about error correcting capability T/2, T/4, T/8 and T is in embodiments of the present invention only to lift
The form of example embodies, and is not construed as limiting.
Based on this, as shown in Figure 3 and Figure 6, the ECC system further includes：Parameter configuration module 27.
Wherein, the parameter configuration module 27 is used to configure the BCH according to the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device 32 and compile
The operating parameter of arithmetic element in code device 32 is additionally operable to configure the BCH decodings according to the error correcting capability of the BCH decoders 23
The operating parameter of arithmetic element in device 23.
Specifically, the error correcting capability control circuit 26 sends parameter configuration instruction to the parameter configuration module 27, with
Make fortune of the parameter configuration module 27 to corresponding arithmetic element in the Bose-Chaudhuri-Hocquenghem Code device 32 or the BCH decoders 23
Row parameter is configured, and the parameter configuration instructs the error correcting capability or the BCH decoders 23 according to the Bose-Chaudhuri-Hocquenghem Code device 32
Error correcting capability generate.
That is, by hardware scheduling and configuration adjustment data trend, changing the Bose-Chaudhuri-Hocquenghem Code device or the BCH decoders
The operations such as circuit structure and amendment operation result, to reach the different error correction energy of the Bose-Chaudhuri-Hocquenghem Code device or the BCH decoders
Power.
It should be noted that the parameter configuration module include but is not limited in FPGA " IBO may be programmed input and output
Unit " can also make simple connecting line that not can configure etc..
Further, with reference to figure 8, Fig. 8 is a kind of circuit structure signal for the Bose-Chaudhuri-Hocquenghem Code device that serial error correcting capability can configure
Figure, in Fig. 8, each register D is to be passed through this by the enable signal control sent out by error correcting capability control circuit 26
Kind of mode controls Bose-Chaudhuri-Hocquenghem Code device circuit overall feedback loop structure, while error correcting capability control circuit can also be entangled according to difference
Wrong ability provides the required generator polynomial g (n-1 of Bose-Chaudhuri-Hocquenghem Code device circuit:1).
Wherein, the enable signal that error correcting capability control circuit is sent out can be gated clock, gate power supply or general
Register Enable Pin etc. in embodiments of the present invention and is not construed as limiting.
It should be noted that similarly using the method for the Bose-Chaudhuri-Hocquenghem Code device that parallel error correction ability can configure, it is only necessary to
Unrelated resource is limited by enable signal, then relevant configuration parameter is provided by parameter configuration module and can be realized.
Based on the embodiment of the present invention one and embodiment two, the present invention also provides a kind of memory, the memory includes
ECC system described above.
By foregoing description it is found that the bit error rate of the ECC system by error correcting capability control circuit according to data to decode
Control the working condition of arithmetic element in the BCH decoders, that is, the quantity of circuit unlatching when changing the operation of BCH decoders, or,
The work of arithmetic element in the Bose-Chaudhuri-Hocquenghem Code device is controlled according to the bit error rate of original information bits data by error correcting capability control circuit
Make state, that is, the quantity that circuit is opened when changing the operation of Bose-Chaudhuri-Hocquenghem Code device makes it only have partial circuit transporting in low error rate
Row, but remain to complete corresponding error correcting capability, while power consumption is also greatly lowered.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (8)
1. a kind of ECC system based on BCH code, which is characterized in that the ECC system includes：BCH decoders and error correcting capability control
Circuit processed, the BCH decoders include multiple arithmetic elements；
Wherein, the error correcting capability control circuit is used to control in the BCH decoders according to the bit error rate of data to decode and transport
The working condition for calculating unit, to change the error correcting capability of the BCH decoders.
2. ECC system according to claim 1, which is characterized in that the ECC system further includes：Parameter configuration module；
Wherein, the parameter configuration module is used to configure in the BCH decoders according to the error correcting capability of the BCH decoders and transport
Calculate the operating parameter of unit.
3. ECC system according to claim 1, which is characterized in that the error correcting capability control circuit is used for foundation and waits translating
The bit error rate of code data controls the working condition of arithmetic element in the BCH decoders, to change the error correction of the BCH decoders
The method of ability includes：
The bit error rate of the error correcting capability control circuit according to the data to decode, controls multiple fortune in the BCH decoders
It calculates corresponding arithmetic element in unit to work, remaining arithmetic element is stopped, to change the BCH decoders
Error correcting capability.
4. ECC system according to claim 3, which is characterized in that the BCH decoders include multiple error correction submodules,
The error correction submodule includes at least one arithmetic element；
The error correcting capability of the error correction submodule is directly proportional to the arithmetic element number that it includes；
The big error correction submodule of error correcting capability includes at least one arithmetic element of the small error correction submodule of error correcting capability.
5. ECC system according to claim 2, which is characterized in that the ECC system further includes：Bose-Chaudhuri-Hocquenghem Code device, it is described
Bose-Chaudhuri-Hocquenghem Code device includes multiple arithmetic elements；
Wherein, the error correcting capability control circuit is additionally operable to control in the Bose-Chaudhuri-Hocquenghem Code device according to the bit error rate of data to be encoded
The working condition of arithmetic element, to change the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device；
The parameter configuration module is additionally operable to configure operation in the Bose-Chaudhuri-Hocquenghem Code device according to the error correcting capability of the Bose-Chaudhuri-Hocquenghem Code device
The operating parameter of unit.
6. ECC system according to claim 5, which is characterized in that the error correcting capability control circuit is additionally operable to foundation and waits for
The bit error rate of coded data controls the working condition of arithmetic element in the Bose-Chaudhuri-Hocquenghem Code device, to change entangling for the Bose-Chaudhuri-Hocquenghem Code device
The method of wrong ability includes：
The bit error rate of the error correcting capability control circuit according to the data to be encoded, controls multiple fortune in the Bose-Chaudhuri-Hocquenghem Code device
It calculates corresponding arithmetic element in unit to work, remaining arithmetic element is stopped, to change the Bose-Chaudhuri-Hocquenghem Code device
Error correcting capability.
7. ECC system according to claim 6, which is characterized in that the Bose-Chaudhuri-Hocquenghem Code device includes multiple error correction submodules,
The error correction submodule includes at least one arithmetic element；
The error correcting capability of the error correction submodule is directly proportional to the arithmetic element number that it includes；
The big error correction submodule of error correcting capability includes at least one arithmetic element of the small error correction submodule of error correcting capability.
8. a kind of memory, which is characterized in that including above-mentioned such as claim 1-7 any one of them ECC systems.
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