CN108666233B - Wafer preparation method capable of being used as separation blade or control blade and wafer - Google Patents
Wafer preparation method capable of being used as separation blade or control blade and wafer Download PDFInfo
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- CN108666233B CN108666233B CN201710208599.1A CN201710208599A CN108666233B CN 108666233 B CN108666233 B CN 108666233B CN 201710208599 A CN201710208599 A CN 201710208599A CN 108666233 B CN108666233 B CN 108666233B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The invention provides aA method for preparing a wafer usable as a dummy wafer or a control wafer by providing a substrate comprising Si3N4A ceramic substrate; and forming a covering layer on the substrate, wherein the covering layer wraps the substrate and covers the whole surface of the substrate. The wafer formed by the invention has a composite structure of the substrate and the covering layer, and can be used as a separation blade or a wafer in an integrated circuit process; the substrate has high stability and strength, and the durability of the wafer is effectively improved; moreover, by configuring the covering layers of different materials, the wafer can be widely applied to various integrated circuit processes, and has high flexibility.
Description
Technical Field
The invention relates to the technical field of semiconductor wafer preparation, in particular to a wafer preparation method capable of being used as a separation blade or a control wafer and a wafer.
Background
With the development of semiconductor technology, various circuit device structures can be fabricated on a wafer by ion implantation, chemical vapor deposition, photolithography, and other processes, thereby forming a semiconductor integrated circuit having specific electrical functions.
In the manufacture of semiconductor integrated circuits, it is generally necessary to use Dummy wafers and Monitor wafers. The main function of the baffle plate in the semiconductor integrated circuit manufacturing process is to maintain the stability and uniformity of the process, and the baffle plate is usually placed in the furnace for stabilizing the gas flow and balancing the temperature of the furnace, or used for warming up during the start-up and recovery of the machine. The control wafer is mainly used for monitoring the stability and the repeatability of the machine; the use method of the control wafer mainly comprises two methods, one method is that before the product wafer is formally manufactured, the control wafer is used for carrying out an experiment, the control wafer is tested after the experiment, whether a machine is normal or not is judged according to a test result, and the test is called an off-line test; the other method is to enter the machine together with the product wafer to perform the process, and test the control wafer to determine whether the operation is normal after the process is completed, which is called an on-line test.
At present, a silicon wafer is often used as a baffle or a control wafer, but the silicon wafer is easy to crack and damage, and the service life is short, so that the silicon wafer can be frequently replaced in the preparation process of an integrated circuit to meet the production requirement. Therefore, how to improve the durability of the barrier sheet and the control sheet is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for preparing a wafer and a wafer, which can be used as a barrier wafer and a control wafer, for solving the problem of poor durability of the barrier wafer and the control wafer in the prior art.
To achieve the above and other related objects, the present invention provides a method for preparing a wafer, which can be used as a barrier wafer and a control wafer, the method comprising the steps of:
providing a substrate comprising Si3N4A ceramic substrate;
and forming a covering layer on the substrate, wherein the covering layer wraps the substrate and covers the whole surface of the substrate.
Optionally, the providing a substrate comprises:
using SiN as a raw material and Lu2O3 as a sintering additive, and sintering by using a high isostatic pressing method to form Si3N4A ceramic substrate.
Alternatively, the sintering using a isostatic pressing process to form Si3N4The ceramic substrate includes:
sintering to form Si under the conditions of pressure of 10 atm-200 atm and temperature of 1700-2200 ℃ in nitrogen atmosphere3N4A ceramic substrate.
Alternatively, the sintering using a isostatic pressing process to form Si3N4A ceramic substrate comprising:
sintering to form Si under the conditions of 50 atm-100 atm pressure and 1800-2000 deg.C in nitrogen atmosphere3N4A ceramic substrate.
Optionally, the capping layer is a SiC layer, and forming the capping layer on the substrate includes:
forming a SiC layer on the substrate at a temperature of 1500 ℃ to 1700 ℃ and a pressure of 600Torr to 900Torr using SiHCl3 and C3H8 as reaction gases.
Optionally, the SiC layer has a thickness of between 600 μm and 800 μm.
Optionally, the capping layer is a Si layer, and forming the capping layer on the substrate includes:
forming a Si layer on the substrate at a temperature of 1000 ℃ to 1500 ℃ and a pressure of 600Torr to 900Torr using SiHCl3 as a reaction gas.
Optionally, the Si layer has a thickness of between 300 μm and 600 μm.
An embodiment of the present invention further provides a wafer, where the wafer includes:
a substrate, and the substrate comprises Si3N4A ceramic substrate;
a cover layer wrapping the substrate and covering the entire surface of the substrate.
Alternatively, the Si3N4The ceramic substrate is formed by sintering SiN serving as a raw material and Lu2O3 serving as a sintering additive under the conditions of pressure of 10atm to 200atm and temperature of 1700 ℃ to 2200 ℃ in a nitrogen atmosphere.
Alternatively, the Si3N4The ceramic substrate is formed by sintering SiN serving as a raw material and Lu2O3 serving as a sintering additive under the conditions of the pressure of 50atm to 100atm and the temperature of 1800 ℃ to 2000 ℃ in a nitrogen atmosphere.
Optionally, the capping layer comprises a SiC layer.
Optionally, the SiC layer is formed under conditions of a temperature of 1500 ℃ to 1700 ℃ and a pressure of 600Torr to 900Torr, with SiHCl3 and C3H8 as reaction gases.
Optionally, the SiC layer has a thickness of between 600 μm and 800 μm.
Optionally, the capping layer comprises a Si layer.
Optionally, the Si layer is formed by using SiHCl3 as a reaction gas at a temperature of 1000 ℃ to 1500 ℃ and a pressure of 600Torr to 900 Torr.
Optionally, the Si layer has a thickness of between 300 μm and 600 μm.
As described above, the wafer and the method for manufacturing the wafer capable of being used as the barrier wafer and the control wafer according to the present invention have the following advantages: by providing a substrate comprising Si3N4A ceramic substrate; in the liningA cover layer is formed over the substrate, the cover layer wrapping the substrate and covering an entire surface of the substrate. The wafer formed by the invention has a composite structure of the substrate and the covering layer, and can be used as a separation blade or a wafer in an integrated circuit process; the substrate has high stability and strength, and the durability of the wafer is effectively improved; moreover, by configuring the covering layers of different materials, the wafer can be widely applied to various integrated circuit processes, and has high flexibility.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a wafer that can be used as a barrier wafer or a control wafer according to an embodiment of the invention.
Fig. 2 to fig. 3 are schematic structural diagrams of a wafer in the process steps of a wafer manufacturing method for a barrier wafer or a control wafer according to an embodiment of the present invention.
Description of the element reference numerals
100 substrate
200 cover layer
S1-S2
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, a flow chart of a method for manufacturing a wafer that can be used as a barrier wafer or a control wafer according to an embodiment of the present invention is shown in fig. 1, and the method includes the following steps:
step S1: providing a substrate 100, said substrate 100 comprising Si3N4A ceramic substrate;
step S2: forming a covering layer 200 on the substrate 100, wherein the covering layer 200 wraps the substrate 100 and covers the entire surface of the substrate 100.
The wafer fabrication method is described in detail below with reference to specific examples.
In step S1, the substrate 100 is Si as shown in fig. 23N4A ceramic substrate, the substrate 100 may be any shape, such as circular, square, etc.; since the silicon wafer for manufacturing the integrated circuit is generally circular, in order to accommodate the manufacturing process of the integrated circuit, in a preferred embodiment, the substrate 100 is a disk-shaped substrate; in the embodiment of the present invention, the size of the substrate 100 is not limited, and the substrate 100 with any size, such as 8 inches, 12 inches, etc., may be set according to the actual use requirement of the barrier sheet or the control sheet.
For the preparation of the substrate 100, SiN may be used as a raw material, Lu2O3As the sintering additive, Si is sintered to form Si by using a High Isostatic Pressing (HIP)3N4A ceramic substrate. Said Si3N4The ceramic substrate has low thermal expansion coefficient, high thermal conductivity, excellent thermal shock resistance, and high strength and impact resistance at high temperature.
In the first embodiment, SiN is used as the raw material, and Lu is used2O3As sintering additives, Si is formed by sintering using a high isostatic pressing process3N4The process conditions of the ceramic substrate may be: sintering in a nitrogen atmosphere at a pressure of 10atm to 200atm and a temperature of 1700 ℃ to 2200 ℃ to form Si3N4A ceramic substrate. In a preferred embodiment, in embodiments of the present invention, Si is formed3N4The ceramic substrate may have a pressure of 10atm and a temperature of 2000 deg.C。
In the second embodiment, SiN is used as the raw material and Lu is used2O3As sintering additives, Si is formed by sintering using a high isostatic pressing process3N4The process conditions of the ceramic substrate may be: sintering to form Si under the conditions of 50 atm-100 atm pressure and 1800-2000 deg.C in nitrogen atmosphere3N4A ceramic substrate.
In step S2, as shown in fig. 3, a cover layer 200 is formed on the substrate 100, and the cover layer 200 wraps the substrate 100 and covers the entire surface of the substrate 100.
In a first implementation, the cap layer 200 may be a SiC layer for SiC-based integrated circuit processes in order to meet their requirements for the barrier and control pads. The SiC layer covers all surfaces of the substrate 100, and the thickness of the SiC layer is between 600 μm and 800 μm.
To form the SiC layer, SiHCl may be used3And C3H8As a reaction gas, a SiC layer is formed on the substrate 100 under conditions of a temperature of 1500 ℃ to 1700 ℃ and a pressure of 600Torr to 900 Torr. Wherein, in a preferred embodiment, the pressure at which the SiC layer is formed may be selected to be 760 Torr.
In a second implementation, the cap layer 200 may be a Si layer for Si-based integrated circuit processes in order to meet their requirements for the barrier and control pads. The Si layer covers all surfaces of the substrate 100, and the thickness of the Si layer is between 300 μm and 600 μm.
To form the Si layer, SiHCl may be used3As a reaction gas, a Si layer is formed on the substrate 100 under the conditions of a temperature of 1000 to 1500 ℃ and a pressure of 600to 900 Torr. Wherein, in a preferred embodiment, the pressure at which the Si layer is formed may be selected to be 760 Torr.
It should be noted that, of course, the above embodiments are only exemplary embodiments, and the capping layer 200 may also be a capping layer made of other materials to meet the requirements of the process based on different materials for the barrier wafer and the control wafer, for example, for the integrated circuit process based on GaN, the capping layer 200 may also be a GaN layer, and the like.
As can be seen from the above description of the embodiments, the embodiments of the present invention provide a method for preparing a wafer that can be used as a barrier wafer and a control wafer, by providing a substrate 100, wherein the substrate 100 comprises Si3N4A ceramic substrate; forming a covering layer 200 on the substrate 100, wherein the covering layer 200 wraps the substrate 100 and covers the entire surface of the substrate 100. The wafer formed by the invention has a composite structure of the substrate 100 and the covering layer 200, and can be used as a separation blade or a wafer in an integrated circuit process; the substrate 100 has high stability and strength, and the durability of the wafer is effectively improved; moreover, by configuring the cover layer 200 of different materials, the wafer can be widely applied to various integrated circuit processes, and has high flexibility.
Corresponding to the embodiment of the wafer preparation method, the invention also provides a wafer.
Referring also to fig. 3, embodiments of the invention provide a wafer comprising a substrate 100 and a cover layer 200. Wherein the substrate 100 comprises Si3N4A ceramic substrate; the cover layer 200 includes the substrate 100 and covers the entire surface of the substrate 100.
To ensure the Si3N4Strength of the ceramic substrate, improved wafer durability, in the first embodiment, the Si3N4The ceramic substrate is made of SiN and Lu2O3As a sintering additive, sintering the formed substrate under a pressure of 10 to 200atm and a temperature of 1700 to 2200 ℃ in a nitrogen atmosphere; wherein, as a preferred embodiment, Si is formed3N4The pressure of the ceramic substrate may be 10atm, and the temperature may be 2000 ℃. In the second embodiment, the Si is3N4The ceramic substrate is SiN as raw material and Lu2O3As a sintering additive, the formed substrate is sintered under a pressure of 50atm to 100atm and a temperature of 1800 ℃ to 2000 ℃ in a nitrogen atmosphere.
In the embodiment of the present invention, since the semiconductor integrated circuit has different process steps, the cap layer 200 may be a SiC layer for the SiC-based integrated circuit process step; for a Si-based integrated circuit process, the cap layer 200 may be a Si layer. Moreover, in order to adapt to different semiconductor integrated circuit process, the capping layer 200 may also be a capping layer 200 of any other material, for example, for a GaN-based integrated circuit process, the capping layer 200 may also be a GaN layer, etc.
In the embodiment of the present invention, the covering layer 200 is an SiC layer or an Si layer, and the structure of the wafer is described in detail.
When the capping layer 200 is a SiC layer, the SiC layer may be SiHCl3And C3H8A SiC layer formed as a reaction gas under a temperature of 1500 ℃ to 1700 ℃ and a pressure of 600Torr to 900 Torr; in a preferred embodiment, the pressure for forming the SiC layer may be 760 Torr. Furthermore, the thickness of the SiC layer is between 600 μm and 800 μm.
When the capping layer 200 is a Si layer, the Si layer may be SiHCl3A Si layer formed as a reaction gas at a temperature of 1000 to 1500 ℃ and a pressure of 600to 900 Torr; wherein, as a preferred embodiment, the pressure for forming the Si layer may be 760 Torr. Furthermore, the thickness of the Si layer is between 300 and 600 μm.
As can be seen from the above description of the embodiments, the wafer provided by the embodiments of the present invention includes the substrate 100, and the substrate 100 includes Si3N4A ceramic substrate; a cover layer 200, said cover layer 200 wrapping said substrate 100 and covering the entire surface of said substrate 100. The wafer of the embodiment of the invention has a composite structure of the substrate 100 and the covering layer 200, thereby ensuring that the wafer can be used as a separation blade or a wafer to be applied to an integrated circuit process; the substrate 100 has high stability and strength, and the durability of the wafer is effectively improved; moreover, by configuring the cover layer 200 of different materials, the wafer can be widely applied to various integrated circuit processes, and has high flexibility.
In summary, the present invention provides a method for preparing a wafer used as a barrier wafer or a control wafer, and a wafer, wherein the wafer is formed based on Si3N4The composite structure of the ceramic substrate and the covering layer fully utilizes Si3N4The ceramic substrate has the characteristics of high stability and high strength, so that the durability of the wafer is effectively improved; moreover, the wafer can be suitable for various integrated circuit process procedures by configuring the covering layers of different materials. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (15)
1. A preparation method of a wafer capable of being used as a separation blade or a control wafer is characterized by comprising the following steps:
providing a substrate comprising Si3N4A ceramic substrate;
forming a covering layer on the substrate, wherein the covering layer wraps the substrate and covers the whole surface of the substrate; the capping layer includes a SiC layer or a Si layer.
2. The method of claim 1, wherein the providing a substrate comprises:
SiN as raw material and Lu as solvent2O3As sintering additives, Si is formed by sintering using an isostatic pressing method3N4A ceramic substrate.
3. Wafer preparation method according to claim 2, useful as a barrier or control waferMethod, characterized in that said sintering to form Si using an isostatic pressing method3N4The ceramic substrate includes:
sintering to form Si under the conditions of pressure of 10 atm-200 atm and temperature of 1700-2200 ℃ in nitrogen atmosphere3N4A ceramic substrate.
4. The method for preparing a wafer used as a baffle or a control wafer as claimed in claim 2, wherein the Si is formed by sintering using an isostatic pressing method3N4A ceramic substrate comprising:
sintering to form Si under the conditions of 50 atm-100 atm pressure and 1800-2000 deg.C in nitrogen atmosphere3N4A ceramic substrate.
5. The method for preparing a wafer usable as a barrier wafer or a control wafer as claimed in any one of claims 1 to 4, wherein when the capping layer is a SiC layer, forming a SiC capping layer on the substrate comprises:
with SiHCl3And C3H8As a reaction gas, an SiC layer is formed on the substrate at a temperature of 1500 ℃ to 1700 ℃ and a pressure of 600Torr to 900 Torr.
6. The method for preparing a wafer capable of being used as a baffle or a control wafer according to claim 5, wherein the thickness of the SiC layer is 600 μm to 800 μm.
7. The method as claimed in any one of claims 1 to 4, wherein when the capping layer is a Si layer, forming a Si capping layer on the substrate comprises:
with SiHCl3As a reaction gas, a Si layer is formed on the substrate at a temperature of 1000 to 1500 ℃ and a pressure of 600to 900 Torr.
8. The method as claimed in claim 7, wherein the thickness of the Si layer is between 300 μm and 600 μm.
9. A wafer, wherein the wafer comprises:
a substrate, and the substrate comprises Si3N4A ceramic substrate;
a cover layer wrapping the substrate and covering the entire surface of the substrate; the capping layer includes a SiC layer or a Si layer.
10. The wafer of claim 9, wherein the Si is present3N4The ceramic substrate is made of SiN and Lu2O3As a sintering additive, the formed substrate is sintered under a pressure of 10atm to 200atm and a temperature of 1700 ℃ to 2200 ℃ in a nitrogen atmosphere.
11. The wafer of claim 9, wherein the Si is present3N4The ceramic substrate is SiN as raw material and Lu2O3As a sintering additive, the formed substrate is sintered under a pressure of 50atm to 100atm and a temperature of 1800 ℃ to 2000 ℃ in a nitrogen atmosphere.
12. The wafer of claim 9, wherein the SiC layer is SiHCl3And C3H8As a reaction gas, a SiC layer is formed under conditions of a temperature of 1500 ℃ to 1700 ℃ and a pressure of 600Torr to 900 Torr.
13. The wafer of claim 9, wherein the thickness of the SiC layer is between 600 μ ι η and 800 μ ι η.
14. The wafer of claim 9, wherein the Si layer is SiHCl3As a reaction gas, a bar at a temperature of 1000 to 1500 ℃ and a pressure of 600to 900TorrAnd an Si layer formed under the substrate.
15. The wafer of claim 9, wherein the thickness of the Si layer is between 300 μ ι η and 600 μ ι η.
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| CN201710208599.1A CN108666233B (en) | 2017-03-31 | 2017-03-31 | Wafer preparation method capable of being used as separation blade or control blade and wafer |
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| CN108666233B true CN108666233B (en) | 2021-02-05 |
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| EP0743677A2 (en) * | 1995-05-19 | 1996-11-20 | KABUSHIKI KAISHA KOBE SEIKO SHO also known as Kobe Steel Ltd. | Dummy Wafer |
| US5770324A (en) * | 1997-03-03 | 1998-06-23 | Saint-Gobain Industrial Ceramics, Inc. | Method of using a hot pressed silicon carbide dummy wafer |
| JP2000034184A (en) * | 1998-07-14 | 2000-02-02 | Toyo Tanso Kk | Part for oxidation treatment oven for soi substrate |
| JP2000119080A (en) * | 1998-10-12 | 2000-04-25 | Furukawa Co Ltd | Ceramic material and its production |
| US6322716B1 (en) * | 1999-08-30 | 2001-11-27 | Cypress Semiconductor Corp. | Method for conditioning a plasma etch chamber |
| CN1768414A (en) * | 2003-03-31 | 2006-05-03 | 新日本石油株式会社 | Dummy wafer |
| CN102484188A (en) * | 2009-07-31 | 2012-05-30 | 电气化学工业株式会社 | Led Equipment Purpose Wafer, Method For Manufacturing Same, And Led-equipped Structure Using Led Equipment Purpose Wafer |
| CN104098336A (en) * | 2013-04-15 | 2014-10-15 | 中国科学院上海硅酸盐研究所 | Method for preparing high-thermal-conductivity high-strength silicon nitride ceramic |
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2017
- 2017-03-31 CN CN201710208599.1A patent/CN108666233B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0743677A2 (en) * | 1995-05-19 | 1996-11-20 | KABUSHIKI KAISHA KOBE SEIKO SHO also known as Kobe Steel Ltd. | Dummy Wafer |
| US5770324A (en) * | 1997-03-03 | 1998-06-23 | Saint-Gobain Industrial Ceramics, Inc. | Method of using a hot pressed silicon carbide dummy wafer |
| JP2000034184A (en) * | 1998-07-14 | 2000-02-02 | Toyo Tanso Kk | Part for oxidation treatment oven for soi substrate |
| JP2000119080A (en) * | 1998-10-12 | 2000-04-25 | Furukawa Co Ltd | Ceramic material and its production |
| US6322716B1 (en) * | 1999-08-30 | 2001-11-27 | Cypress Semiconductor Corp. | Method for conditioning a plasma etch chamber |
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