CN108666233A - A kind of chip preparation method and chip can be used as catch or control wafer - Google Patents
A kind of chip preparation method and chip can be used as catch or control wafer Download PDFInfo
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- CN108666233A CN108666233A CN201710208599.1A CN201710208599A CN108666233A CN 108666233 A CN108666233 A CN 108666233A CN 201710208599 A CN201710208599 A CN 201710208599A CN 108666233 A CN108666233 A CN 108666233A
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- substrate
- chip
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- catch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The present invention provides a kind of chip preparation method and chip can be used as catch or control wafer, and by providing substrate, the substrate includes Si3N4Ceramic substrate；In forming coating on the substrate, the coating wraps up the substrate and covers all surfaces of the substrate.The chip that the present invention is formed has the composite construction of substrate and coating, ensure that the chip can be used as catch or chip to be applied in integrated circuit technology；The substrate has very high stability and intensity, has effectively improved the durability of chip；Moreover, the coating by configuring different materials so that the chip can be widely used in a variety of integrated circuit technologies, have very high flexibility.
Description
Technical field
The present invention relates to semiconductor wafer preparing technical fields, more particularly to a kind of chip can be used as catch or control wafer
Preparation method and chip.
Background technology
It, can be with using techniques such as ion implanting, chemical vapor deposition and photoetching with the development of semiconductor process technique
Various circuit component structures are made on chip, to form the semiconductor integrated circuit with specific electrical functionality.
In the manufacturing process of semiconductor integrated circuit, it usually needs use catch (English：Dummy Wafer) and control wafer
(English：Monitor Wafer).Wherein, main function of the catch in semiconductor integrated circuit manufacturing process is to maintain technique
Stability and homogeneity, catch is placed in boiler tube generally for steady air flow and balance furnace tube temperature, or in board
In startup and recovery process catch is used for warming-up.The main function of control wafer is stability and the repetition for monitoring board
Property；There are mainly two types of the application methods of control wafer, one is before formally manufacture product piece, is first tested, is tested with control wafer
After test control wafer, judge whether board normal according to test result, this test is called off-line test；Another kind is with product
Piece does technique into board together, tests control wafer after the completion of technique to judge whether this subjob is normal, this test is called
Line is tested.
Currently, silicon chip is used often as catch or control wafer, however silicon chip is easy to that embrittlement damage occurs, and uses the longevity
Life is shorter, and may be needed to frequently replace in the preparation process of integrated circuit could meet production requirement in this way.Therefore, how to carry
The technical issues of durability of high catch and control wafer is those skilled in the art's urgent need to resolve.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of catch and control wafers of can be used as
Chip preparation method and chip, for solving the problems, such as catch in the prior art and control wafer poor durability.
In order to achieve the above objects and other related objects, the present invention provides a kind of chip preparation can be used as catch and control wafer
Method, this approach includes the following steps：
Substrate is provided, the substrate includes Si3N4Ceramic substrate；
In forming coating on the substrate, the coating wraps up the substrate and covers whole tables of the substrate
Face.
Optionally, the offer substrate includes：
Using SiN as raw material, using Lu2O3 as sinter additives, it is sintered to form Si using high hydrostatic pressure method3N4Ceramic liner
Bottom.
Optionally, described to be sintered to form Si using high hydrostatic pressure method3N4Ceramic substrate includes：
In nitrogen atmosphere, under conditions of pressure is 10atm to 200atm and temperature is 1700 DEG C to 2200 DEG C,
Sintering forms Si3N4Ceramic substrate.
Optionally, described to be sintered to form Si using high hydrostatic pressure method3N4Ceramic substrate, including：
In nitrogen atmosphere, under conditions of pressure is 50atm to 100atm and temperature is 1800 DEG C to 2000 DEG C,
Sintering forms Si3N4Ceramic substrate.
Optionally, the coating is SiC layer, includes in forming coating on the substrate：
Using SiHCl3 and C3H8 as reaction gas, temperature be 1500 DEG C to 1700 DEG C and pressure be 600Torr extremely
Under conditions of 900Torr, in forming SiC layer on the substrate.
Optionally, the thickness of the SiC layer is between 600 μm to 800 μm.
Optionally, the coating is Si layers, in forming coating on the substrate, including：
Using SiHCl3 as reaction gas, temperature be 1000 DEG C to 1500 DEG C and pressure be 600Torr extremely
Under conditions of 900Torr, in Si layers of formation on the substrate.
Optionally, Si layers of the thickness is between 300 μm to 600 μm.
The embodiment of the present invention also provides a kind of chip, and the chip includes：
Substrate, and the substrate includes Si3N4Ceramic substrate；
Coating, the coating wrap up the substrate and cover all surfaces of the substrate.
Optionally, the Si3N4Ceramic substrate is using SiN as raw material, using Lu2O3 as sinter additives, in nitrogen atmosphere
In, the substrate of formation is sintered under conditions of pressure is 10atm to 200atm and temperature is 1700 DEG C to 2200 DEG C.
Optionally, the Si3N4Ceramic substrate is that SiN is raw material, using Lu2O3 as sinter additives, in nitrogen atmosphere
In, the substrate of formation is sintered under conditions of pressure is 50atm to 100atm and temperature is 1800 DEG C to 2000 DEG C.
Optionally, the coating includes SiC layer.
Optionally, the SiC layer is using SiHCl3 and C3H8 as reaction gas, is 1500 DEG C to 1700 DEG C in temperature,
And pressure is the SiC layer that is formed under conditions of 600Torr to 900Torr.
Optionally, the thickness of the SiC layer is between 600 μm to 800 μm.
Optionally, the coating includes Si layers.
Optionally, described Si layers is using SiHCl3 as reaction gas, is 1000 DEG C to 1500 DEG C and pressure in temperature
For the Si layers formed under conditions of 600Torr to 900Torr.
Optionally, Si layers of the thickness is between 300 μm to 600 μm.
As described above, the chip preparation method and chip that can be used as catch and control wafer of the present invention, has below beneficial to effect
Fruit：By providing substrate, the substrate includes Si3N4Ceramic substrate；In forming coating, the coating packet on the substrate
It wraps up in the substrate and covers all surfaces of the substrate.The chip that the present invention is formed has the composite junction of substrate and coating
Structure ensure that the chip can be used as catch or chip to be applied in integrated circuit technology；The substrate has very high stabilization
Property and intensity, have effectively improved the durability of chip；Moreover, the coating by configuring different materials so that the chip energy
It is enough widely used in a variety of integrated circuit technologies, there is very high flexibility.
Description of the drawings
The flow that Fig. 1 is shown as a kind of chip preparation method can be used as catch or control wafer provided in an embodiment of the present invention is shown
It is intended to.
Fig. 2 to Fig. 3 is shown as the embodiment of the present invention and provides a kind of chip preparation method technique can be used as catch or control wafer
The structural schematic diagram of chip in step.
Component label instructions
100 substrates
200 coatings
S1~S2 steps
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Fig.3.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in illustrating then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
It is a kind of flow for the chip preparation method can be used as catch or control wafer provided in an embodiment of the present invention referring to Fig. 1
Schematic diagram, as shown in Figure 1, this approach includes the following steps：
Step S1：Substrate 100 is provided, the substrate 100 includes Si3N4Ceramic substrate；
Step S2：In forming coating 200 on the substrate 100, the coating 200 wraps up the substrate 100 and covers
Cover all surfaces of the substrate 100.
The chip preparation method is described in detail with reference to specific embodiment.
In step sl, as shown in Fig. 2, the substrate 100 uses Si3N4Ceramic substrate, the substrate 100 can be to appoint
Meaning shape, such as round, rectangular etc.；Since the silicon wafer for preparing integrated circuit is generally circular, in order to adapt to integrated circuit
Preparation process, in a preferred embodiment, the substrate 100 are disk-shaped substrate；And in embodiments of the present invention to described
The size of substrate 100 does not limit, and can actually use demand according to catch or control wafer, the substrate 100 of arbitrary dimension, example is arranged
Such as 8 cun, 12 cun.
It, can be using SiN as raw material, with Lu in order to prepare the substrate 1002O3As sinter additives, high hydrostatic pressure is used
Method (English：High Isostatic Pressing, referred to as：HIP) sintering forms Si3N4Ceramic substrate.The Si3N4Ceramics
Substrate coefficient of thermal expansion is low, thermal conductivity is high, and thermal shock resistance is splendid, and at a higher temperature, have very high intensity and
Impact resistance.
Under the first performance, using SiN as raw material, with Lu2O3As sinter additives, high hydrostatic pressure method is used
Sintering forms Si3N4The process conditions of ceramic substrate can be：In nitrogen atmosphere, in pressure be 10atm to 200atm, and
Sintering forms Si under conditions of temperature is 1700 DEG C to 2200 DEG C3N4Ceramic substrate.In a preferred embodiment, of the invention real
It applies in example, forms Si3N4The pressure of ceramic substrate can be 10atm and temperature can be 2000 DEG C.
Under second of performance, using SiN as raw material, with Lu2O3As sinter additives, high hydrostatic pressure method is used
Sintering forms Si3N4The process conditions of ceramic substrate can be：In nitrogen atmosphere, in pressure be 50atm to 100atm, and
Under conditions of temperature is 1800 DEG C to 2000 DEG C, sintering forms Si3N4Ceramic substrate.
In step s 2, as shown in figure 3, in forming coating 200 on the substrate 100, the coating 200 wraps up institute
It states substrate 100 and covers all surfaces of the substrate 100.
Under the first performance, for the integrated circuit technology based on SiC, in order to meet it for catch and control wafer
Demand, the coating 200 can be SiC layer.The SiC layer is covered in all surface of the substrate 100, and described
The thickness of SiC layer is between 600 μm to 800 μm.
It, can be with SiHCl in order to form the SiC layer3And C3H8It it is 1500 DEG C to 1700 in temperature as reaction gas
DEG C and under conditions of pressure is 600Torr to 900Torr, in forming SiC layer on the substrate 100.Wherein, preferably one
In embodiment, 760Torr can be selected as by forming the pressure of SiC layer.
Under second of performance, for the integrated circuit technology based on Si, in order to meet it for catch and control wafer
Demand, the coating 200 can be Si layers.The Si layers of all surface for being covered in the substrate 100, and it is Si layers described
Thickness between 300 μm to 600 μm.
It is Si layers described in order to be formed, it can be with SiHCl3It is 1000 DEG C to 1500 DEG C in temperature as reaction gas, and
Under conditions of pressure is 600Torr to 900Torr, in Si layers of formation on the substrate 100.Wherein, in a preferred embodiment,
760Torr can be selected as by forming Si layers of pressure.
Certainly, it should be noted that above-described embodiment is only exemplary embodiment, and the coating 200 can also be it
The coating of his material, to adapt to requirement of the manufacturing process based on different materials to catch and control wafer, such as based on GaN
Integrated circuit technology, the coating 200 can also select GaN layer etc..
By the description of above-described embodiment as it can be seen that a kind of chip can be used as catch and control wafer provided in an embodiment of the present invention
Preparation method, by providing substrate 100, the substrate 100 includes Si3N4Ceramic substrate；It is covered in being formed on the substrate 100
Layer 200, the coating 200 wraps up the substrate 100 and covers all surfaces of the substrate 100.The crystalline substance that the present invention is formed
Piece has the composite construction of substrate 100 and coating 200, ensure that the chip can be used as catch or chip to be applied to integrated electricity
In the technique of road；The substrate 100 has very high stability and intensity, has effectively improved the durability of chip；Moreover, passing through
Configure the coating 200 of different materials so that the chip can be widely used in a variety of integrated circuit technologies, have very high
Flexibility.
Corresponding with above-mentioned chip preparation method embodiment, the present invention also provides a kind of chips.
See also Fig. 3, chip provided in an embodiment of the present invention includes substrate 100 and coating 200.Wherein, the lining
Bottom 100 includes Si3N4Ceramic substrate；The coating 200 includes the substrate 100 and covers whole tables of the substrate 100
Face.
In order to ensure the Si3N4The intensity of ceramic substrate improves the durability of chip, under the first performance, institute
State Si3N4Ceramic substrate is using SiN as raw material, with Lu2O3As sinter additives, in nitrogen atmosphere, in pressure be 10atm
The substrate of formation is sintered under conditions of being 1700 DEG C to 2200 DEG C to 200atm and temperature；Wherein, it is preferably implemented as one
Example forms Si3N4The pressure of ceramic substrate can be 10atm, and temperature can be 2000 DEG C.Under second of performance, institute
State Si3N4Ceramic substrate is that SiN is raw material, with Lu2O3As sinter additives, in nitrogen atmosphere, in pressure be 50atm extremely
100atm and temperature are sintered the substrate of formation under conditions of being 1800 DEG C to 2000 DEG C.
In embodiments of the present invention, since semiconductor integrated circuit has different process processing procedure, for integrated based on SiC
Circuit technology processing procedure, the coating 200 can be SiC layer；For the integrated circuit technology processing procedure based on Si, the coating
200 can be Si layers.Moreover, in order to adapt to different semiconductor integrated circuit technique processing procedures, the coating 200 can also be
The coating 200 of any other material, such as the integrated circuit technology processing procedure based on GaN, the coating 200 can be with
For GaN layer etc..
The structure of the chip is described in detail so that coating 200 is SiC layer or Si layers as an example in the embodiment of the present invention.
When the coating 200 is SiC layer, the SiC layer can be with SiHCl3And C3H8As reaction gas,
Temperature be 1500 DEG C to 1700 DEG C and pressure be 600Torr to 900Torr under conditions of the SiC layer that is formed；Wherein, as
One preferred embodiment, the pressure for forming SiC layer can be 760Torr.Moreover, the thickness of the SiC layer is between 600 μm to 800 μ
m。
When the coating 200 is Si layers, described Si layers can be with SiHCl3As reaction gas, it is in temperature
The Si layers that 1000 DEG C to 1500 DEG C and pressure are formed under conditions of being 600Torr to 900Torr；Wherein, preferred real as one
Example is applied, it can be 760Torr to form Si layers of the pressure.Moreover, Si layers of the thickness is between 300 μm to 600 μm.
By the description of above-described embodiment as it can be seen that a kind of chip provided in an embodiment of the present invention, including substrate 100, and it is described
Substrate 100 includes Si3N4Ceramic substrate；Coating 200, the coating 200 wrap up the substrate 100 and cover the substrate
100 all surfaces.The chip of the embodiment of the present invention has the composite construction of substrate 100 and coating 200, ensure that the chip
Catch or chip can be used as to be applied in integrated circuit technology；The substrate 100 has very high stability and intensity, effectively
It has been increased to the durability of chip；Moreover, the coating 200 by configuring different materials so that the chip can be generally applicable
In a variety of integrated circuit technologies, there is very high flexibility.
In conclusion the present invention provides a kind of chip preparation method and chip can be used as catch or control wafer, base is formd
In Si3N4The composite construction of ceramic substrate and coating, takes full advantage of Si3N4The high stability of ceramic substrate and high intensity
Feature effectively increases the durability of chip；Moreover, the coating by configuring different materials so that the chip can be applicable in
In a variety of integrated circuit technology processing procedures.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial
Utility value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (17)
1. a kind of chip preparation method can be used as catch or control wafer, which is characterized in that the preparation method comprises the following steps：
Substrate is provided, the substrate includes Si3N4Ceramic substrate；
In forming coating on the substrate, the coating wraps up the substrate and covers all surfaces of the substrate.
2. the chip preparation method according to claim 1 that can be used as catch or control wafer, which is characterized in that the offer lining
Bottom includes：
Using SiN as raw material, with Lu2O3As sinter additives, it is sintered to form Si using high hydrostatic pressure method3N4Ceramic substrate.
3. the chip preparation method according to claim 2 that can be used as catch or control wafer, which is characterized in that described using high
Isostatic pressed method is sintered to form Si3N4Ceramic substrate includes：
In nitrogen atmosphere, under conditions of pressure is 10atm to 200atm and temperature is 1700 DEG C to 2200 DEG C, sintering
Form Si3N4Ceramic substrate.
4. the chip preparation method according to claim 2 that can be used as catch or control wafer, which is characterized in that described using high
Isostatic pressed method is sintered to form Si3N4Ceramic substrate, including：
In nitrogen atmosphere, under conditions of pressure is 50atm to 100atm and temperature is 1800 DEG C to 2000 DEG C, sintering
Form Si3N4Ceramic substrate.
5. the chip preparation method according to any one of claims 1 to 4 that can be used as catch or control wafer, which is characterized in that institute
It is SiC layer to state coating, includes in forming coating on the substrate：
With SiHCl3And C3H8As reaction gas, temperature be 1500 DEG C to 1700 DEG C and pressure be 600Torr extremely
Under conditions of 900Torr, in forming SiC layer on the substrate.
6. the chip preparation method according to claim 5 that can be used as catch or control wafer, which is characterized in that the SiC layer
Thickness between 600 μm to 800 μm.
7. the chip preparation method according to any one of claims 1 to 4 that can be used as catch or control wafer, which is characterized in that institute
It is Si layers to state coating, in forming coating on the substrate, including：
With SiHCl3As reaction gas, in the item that temperature is 1000 DEG C to 1500 DEG C and pressure is 600Torr to 900Torr
Under part, in Si layers of formation on the substrate.
8. the chip preparation method according to claim 7 that can be used as catch or control wafer, which is characterized in that described Si layers
Thickness is between 300 μm to 600 μm.
9. a kind of chip, which is characterized in that the chip includes：
Substrate, and the substrate includes Si3N4Ceramic substrate；
Coating, the coating wrap up the substrate and cover all surfaces of the substrate.
10. chip according to claim 9, which is characterized in that the Si3N4Ceramic substrate be using SiN as raw material, with
Lu2O3As sinter additives, in nitrogen atmosphere, in pressure be 10atm to 200atm and temperature is 1700 DEG C to 2200
The substrate of formation is sintered under conditions of DEG C.
11. chip according to claim 9, which is characterized in that the Si3N4Ceramic substrate is that SiN is raw material, with Lu2O3
As sinter additives, in nitrogen atmosphere, in pressure be 50atm to 100atm and temperature is 1800 DEG C to 2000 DEG C
Under the conditions of be sintered the substrate of formation.
12. according to any chip of claim 9 to 11, which is characterized in that the coating includes SiC layer.
13. chip according to claim 12, which is characterized in that the SiC layer is with SiHCl3And C3H8As reaction gas
Body, the SiC layer formed under conditions of temperature is 1500 DEG C to 1700 DEG C and pressure is 600Torr to 900Torr.
14. chip according to claim 12, which is characterized in that the thickness of the SiC layer is between 600 μm to 800 μm.
15. according to any chip of claim 9 to 11, which is characterized in that the coating includes Si layers.
16. chip according to claim 15, which is characterized in that described Si layers is with SiHCl3As reaction gas, in temperature
Degree be 1000 DEG C to 1500 DEG C and pressure be 600Torr to 900Torr under conditions of the Si layers that are formed.
17. chip according to claim 15, which is characterized in that Si layers of the thickness is between 300 μm to 600 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710208599.1A CN108666233B (en) | 2017-03-31 | 2017-03-31 | Wafer preparation method capable of being used as separation blade or control blade and wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710208599.1A CN108666233B (en) | 2017-03-31 | 2017-03-31 | Wafer preparation method capable of being used as separation blade or control blade and wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108666233A true CN108666233A (en) | 2018-10-16 |
| CN108666233B CN108666233B (en) | 2021-02-05 |
Family
ID=63783887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710208599.1A Active CN108666233B (en) | 2017-03-31 | 2017-03-31 | Wafer preparation method capable of being used as separation blade or control blade and wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108666233B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112466744A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | Novel crystal element and preparation method thereof |
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| EP0743677A2 (en) * | 1995-05-19 | 1996-11-20 | KABUSHIKI KAISHA KOBE SEIKO SHO also known as Kobe Steel Ltd. | Dummy Wafer |
| US5770324A (en) * | 1997-03-03 | 1998-06-23 | Saint-Gobain Industrial Ceramics, Inc. | Method of using a hot pressed silicon carbide dummy wafer |
| JP2000034184A (en) * | 1998-07-14 | 2000-02-02 | Toyo Tanso Kk | Part for oxidation treatment oven for soi substrate |
| JP2000119080A (en) * | 1998-10-12 | 2000-04-25 | Furukawa Co Ltd | Ceramic material and its production |
| US6322716B1 (en) * | 1999-08-30 | 2001-11-27 | Cypress Semiconductor Corp. | Method for conditioning a plasma etch chamber |
| CN1768414A (en) * | 2003-03-31 | 2006-05-03 | 新日本石油株式会社 | Dummy wafer |
| CN102484188A (en) * | 2009-07-31 | 2012-05-30 | 电气化学工业株式会社 | Led Equipment Purpose Wafer, Method For Manufacturing Same, And Led-equipped Structure Using Led Equipment Purpose Wafer |
| CN104098336A (en) * | 2013-04-15 | 2014-10-15 | 中国科学院上海硅酸盐研究所 | Method for preparing high-thermal-conductivity high-strength silicon nitride ceramic |
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2017
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0743677A2 (en) * | 1995-05-19 | 1996-11-20 | KABUSHIKI KAISHA KOBE SEIKO SHO also known as Kobe Steel Ltd. | Dummy Wafer |
| US5770324A (en) * | 1997-03-03 | 1998-06-23 | Saint-Gobain Industrial Ceramics, Inc. | Method of using a hot pressed silicon carbide dummy wafer |
| JP2000034184A (en) * | 1998-07-14 | 2000-02-02 | Toyo Tanso Kk | Part for oxidation treatment oven for soi substrate |
| JP2000119080A (en) * | 1998-10-12 | 2000-04-25 | Furukawa Co Ltd | Ceramic material and its production |
| US6322716B1 (en) * | 1999-08-30 | 2001-11-27 | Cypress Semiconductor Corp. | Method for conditioning a plasma etch chamber |
| CN1768414A (en) * | 2003-03-31 | 2006-05-03 | 新日本石油株式会社 | Dummy wafer |
| CN102484188A (en) * | 2009-07-31 | 2012-05-30 | 电气化学工业株式会社 | Led Equipment Purpose Wafer, Method For Manufacturing Same, And Led-equipped Structure Using Led Equipment Purpose Wafer |
| CN104098336A (en) * | 2013-04-15 | 2014-10-15 | 中国科学院上海硅酸盐研究所 | Method for preparing high-thermal-conductivity high-strength silicon nitride ceramic |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112466744A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | Novel crystal element and preparation method thereof |
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|---|---|
| CN108666233B (en) | 2021-02-05 |
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