CN108650204A - For the FBMC/OQAM modulating control systems and method of FPGA, modulator - Google Patents

For the FBMC/OQAM modulating control systems and method of FPGA, modulator Download PDF

Info

Publication number
CN108650204A
CN108650204A CN201810217449.1A CN201810217449A CN108650204A CN 108650204 A CN108650204 A CN 108650204A CN 201810217449 A CN201810217449 A CN 201810217449A CN 108650204 A CN108650204 A CN 108650204A
Authority
CN
China
Prior art keywords
fbmc
signal
oqam
data
fpga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810217449.1A
Other languages
Chinese (zh)
Other versions
CN108650204B (en
Inventor
尚磊
刘威
张恒伟
殷慧慧
韩兴忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN201810217449.1A priority Critical patent/CN108650204B/en
Publication of CN108650204A publication Critical patent/CN108650204A/en
Application granted granted Critical
Publication of CN108650204B publication Critical patent/CN108650204B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/264—Pulse-shaped multi-carrier, i.e. not using rectangular window
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2697—Multicarrier modulation systems in combination with other modulation techniques

Abstract

The invention belongs to multi-carrier communication technical field, disclose it is a kind of for the FBMC/OQAM modulating control systems and method of FPGA, modulator, including：OQAM preprocessing modules, the alternating mapping for completing QAM mappings and odd number even-numbered channels；Synthesis filter group (SFB) module, for being respectively molded odd-numbered channels symbol and even-numbered channels symbol-modulated；Data delay module, for the modulation symbol of even-numbered channels to be postponed 1/2 symbol time length；Adder Module completes the modulation of FBMC/OQAM signals for the modulation symbol of two path channels to be superimposed.The present invention is designed using full synchronised clock, using the continuous modulation of pipeline processes FBMC/OQAM signals, the modulator design of the transmitting terminal for the FBMC/OQAM systems that can be used on FPGA.

Description

For the FBMC/OQAM modulating control systems and method of FPGA, modulator
Technical field
The invention belongs to multi-carrier communication technical field more particularly to a kind of FBMC/OQAM modulation controls for FPGA System and method, modulator.
Background technology
Filter bank multi-carrier (FBMC) technology and orthogonal frequency division multiplexing (OFDM) technology belong to multi-carrier modulation skill Art.At present OFDM technology is a kind of most popular multi-carrier modulation technology, since its simple balancing technique, FFT are answered With and obtain extensive research the advantages that the extremely low complexity generated and the higher availability of frequency spectrum.FBMC technologies make With the filter group of one group of optimization to achieve the purpose that Out-of-band rejection, skill is transmitted using the FBMC of quadrature amplitude modulation (OQAM) One of the major candidate of art as future wireless system technology is the case where meeting efficiency of transmission identical with OFDM technology Under obtained more excellent Out-of-band rejection performance and reduce the orthogonality demand between subcarrier.Due to FBMC/OQAM technologies Realize complexity, studying the technology, succinctly quick realization method is necessary.
Currently, the prior art commonly used in the trade is such：
(1) using the realization method of frequency domain expansion, i.e. data are multiplied by the frequency domain form of ptototype filter after OQAM modulation, into IFFT transformation is carried out after row frequency domain expansion, and obtained data are finally subjected to serioparallel exchange and cycle is superimposed.It needs to carry out at this time The IFFT transformation of KM points, computation complexity are big compared with the IFFT transformation of M points, meanwhile, frequency domain expansion operation needs KM multiplier, in addition, The operation of cycle superposition is also required to expend a large amount of memory (RAM) resource；
(2) mode of time-domain windowed is used, i.e. data directly carry out IFFT transformation after OQAM modulation, and IFFT is converted to obtain Datacycle replicate after adding window be superimposed, it should be noted that IFFT transformation points be M, and window function length be KM, at this time plus Window operation at least needs M multiplier, the operation of superposition to also need to consume a large amount of RAM resources；
(3) mode of polyphase network is used, i.e. data directly carry out IFFT transformation after OQAM modulation, after IFFT is converted Data are by carrying out serioparallel exchange after polyphase network, this method is converted using M points IFFT, but polyphase network needs KM multiplication Device consumes a large amount of FPGA resource while accelerating data processing speed.
In conclusion problem of the existing technology is：
(1) in frequency domain expansion and time-domain windowed mode, cycle superposition can bring a large amount of RAM resource occupation and height Delay；
(2) in the case of low delay, polyphase network introduces excessive multiplier, consumes a large amount of FPGA resources；
(3) in the mode of time-domain windowed, due to the use of RAM, it can not ensure that the full flowing water of algorithm is realized, reduce data Operation efficiency.
SolutionThe certainly difficulty and meaning of above-mentioned technical problem：In order to solve the above-mentioned technical problem, it needs in module computation delay Balance is obtained between resource consumption, the portability of module can be improved by reducing FPGA resource consumption, and can greatly be reduced and be The addition difficulty of other function modules, in addition, certain computation delay can ensure the data throughout of system, and reduces in system The design difficulty of other complex data processing modules.
Invention content
In view of the problems of the existing technology, the present invention provides a kind of FBMC/OQAM modulation controls systems for FPGA System and method, modulator.
The invention is realized in this way a kind of FBMC/OQAM modulating control systems for FPGA, described for FPGA's FBMC/OQAM modulating control systems include：
OQAM preprocessing modules, the alternating mapping for completing QAM mappings and odd number even-numbered channels；
Synthesis filter group module, for being respectively molded odd-numbered channels symbol and even-numbered channels symbol-modulated；
Data delay module, for the modulation symbol of even-numbered channels to be postponed 1/2 symbol time length；
Adder Module completes the modulation of FBMC/OQAM signals for the modulation symbol of two path channels to be superimposed.
Further, the synthesis filter group module includes an IFFT module and a PPN module；
IFFT modules use stream treatment pattern, and input data and output data are continuous data, directly use FPGA Chip manufacturer provides the stream treatment pattern of IP kernel or voluntarily writes；
PPN modules complete the multiphase filtering network in FBMC modulators when overlap factor K takes 4；By controlling signal life The addresses ROM and output data useful signal are controlled at module.
Further, the PPN modules include 6 time delay modules, 8 multiplication modules, 2 adder Modules, 4 ROM The filter coefficient generation module and control signal generation module of completion；
Filter coefficient is determined that obtained filter coefficient is sampled by K and stored respectively to 4 by K and IFFT exponent numbers M In ROM, the filter coefficient that convolutional calculation uses is provided for PPN；
Time delay module extracts the data on K same subcarriers and send to multiplier progress operation, and delay depth is M；
The operation of real part imaginary part uses 4 multipliers and four input summers to complete convolution algorithm respectively.
Further, the data delay module is made of three time delay modules, and the FBMC symbols that even-numbered channels is modulated are prolonged When the half symbols period export, the delay depth of time delay module is M/2.
Further, the FBMC symbols of two path channels are superimposed by the adder Module, and 2 road complex signal of input exports 1 tunnel Complex signal, output data length are determined by symbol quantity N, IFFT order of modulation M and overlap factor K.
Another object of the present invention is to provide a kind of being used for for FBMC/OQAM modulating control systems for FPGA The FBMC/OQAM modulation control methods of FPGA, the FBMC/OQAM modulation control methods for FPGA include：
The alternating mapping of step 1, QAM mappings and odd number even-numbered channels；
Odd-numbered channels symbol and even-numbered channels symbol-modulated are molded by step 2；
The modulation symbol of step 3, even-numbered channels postpones 1/2 symbol time length；
Step 4, the modulation symbol superposition of two path channels, completes the modulation of FBMC/OQAM signals.
Further, the step 1 specifically includes：
(1) input signal is subjected to QAM modulation, obtains modulated complex signal；
(2) real and imaginary parts of modulated complex signal are detached；
(3) the actual situation mapping that enable signal controls a digit counter with control module output signal is inputted according to data；
(4) when Counter Value is 0, solid part signal is exported by dout_0_r, and imaginary signals are exported by dout_1_i；Counter When value is 1, solid part signal is exported by dout_0_i, and imaginary signals are exported by dout_1_r.
Further, the step 2 specifically includes：
(1) odd-numbered channels input signal is completed IFFT transformation, obtains serial complex signal and number by IFFT modules According to enable signal；
(2) the data enable signal input control signal generation module for exporting IFFT modules, by the enabled delay of the data (K-1) it M time spans and is taken with original signal or, generating addr signals, and the T that is delayed using obtained signal control counterpWhen Between length, obtain data_valid signals, TpIt is defined by following formula：
Tp=Tmul+Tadd
Wherein, TmulIndicate multiplier processing delay, TaddIndicate adder processing delay.
(3) the addr signals obtained in (2) are input in four ROM, the ports dout output filter coefficient signal；
(4) by the real part imaginary part of the serial complex signal obtained in (1) continue through respectively three delay depth it is identical Time delay module, wherein delay depth is M；
(5) by the real part imaginary part of three obtained complex signal in the complex signal obtained in (1) and (4) respectively with its The four filter coefficient signal multiplications obtained in corresponding (3), obtained result are input in two adders, are exported The real part dout_r and imaginary part dout_i of signal；
(6) even-numbered channels input signal repeats (1)~(5).
Further, the step 3 includes：
(1) data in even-numbered channels are enabled into data_valid and is input to time delay module, delay depth is M/2, is obtained Data after delay are enabled；
(2) the real part imaginary part of the complex signal in even-numbered channels is separately input into the identical time delay module of delay depth, Delay depth is M/2, the complex signal after being delayed；
Further, the step 4 includes：
(1) data of odd-numbered channels input the enabled din_1_en of data that din_0_en is inputted with even-numbered channels is enabled to take Or, obtaining output data enables data_valid；
(2) complex signal that odd-numbered channels inputs is added with the complex signal that even-numbered channels inputs, what is exported answers Number signal, real part dout_r, imaginary part dout_i.
Another object of the present invention is to provide the FBMC/OQAM modulating control systems that FPGA is used for described in a kind of application Modulator.
In conclusion advantages of the present invention and good effect are：The present invention can under FPGA environment design and compilation, the present invention IFFT, 4K multipliers of 2 M points, 5 adders and 8 ROM need to be used altogether, relative to the frequency that need to use 2KM multiplier Domain extended method and polyphase network method effectively control the use of FPGA resource, and may make using pipeline processes technology Modulation treatment is continuously rapidly completed in FBMC/OQAM signals.
Description of the drawings
Fig. 1 is the FBMC/OQAM modulating control system structural schematic diagrams provided in an embodiment of the present invention for FPGA；
In figure：1, OQAM preprocessing modules；2, synthesis filter group module；3, data delay module；4, adder Module.
Fig. 2 is the FBMC/OQAM modulation control method flow charts provided in an embodiment of the present invention for FPGA.
Fig. 3 is the structural schematic diagram of SFB modules provided in an embodiment of the present invention.
Fig. 4 is the structural schematic diagram of PPN modules provided in an embodiment of the present invention.
Fig. 5 is the time stimulatiom figure of the FBMC/OQAM modulating control systems provided in an embodiment of the present invention for FPGA.
Fig. 6 is the resource consumption figure of the FBMC/OQAM modulating control systems provided in an embodiment of the present invention for FPGA.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to embodiments, to the present invention It is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to Limit the present invention.
As shown in Figure 1, the FBMC/OQAM modulating control systems provided in an embodiment of the present invention for FPGA include：OQAM Preprocessing module 1, synthesis filter group module 2, data delay module 3, adder Module 4.
OQAM preprocessing modules 1 are used to complete QAM mappings and the alternating mapping of odd number even-numbered channels；
Synthesis filter group module 2 (SFB), for respectively by odd-numbered channels symbol and even-numbered channels symbol-modulated at Type；
Data delay module 3, for the modulation symbol of even-numbered channels to be postponed 1/2 symbol time length；
Adder Module 4 completes the modulation of FBMC/OQAM signals for the modulation symbol of two path channels to be superimposed.
As shown in Fig. 2, the FBMC/OQAM modulation control methods provided in an embodiment of the present invention for FPGA include following step Suddenly：
S201：QAM maps and the mapping of the alternating of odd number even-numbered channels；
S202：Odd-numbered channels symbol and even-numbered channels symbol-modulated are molded；
S203：The modulation symbol of even-numbered channels postpones 1/2 symbol time length；
S204：The modulation symbol of two path channels is superimposed, and completes the modulation of FBMC/OQAM signals.
The application principle of the present invention is further described below in conjunction with the accompanying drawings.
OQAM preprocessing modules 1 are stream treatment module, and basic thought is to carry out QAM signals with actual situation interval mode Modulation.Its working principle is that：(1) input signal is subjected to QAM modulation, obtains modulated complex signal；It (2) will be modulated The real and imaginary parts separation (3) of complex signal is inputted enable signal and control a digit counter and exported with control module according to data to be believed Number actual situation mapping；(4) when Counter Value is 0, solid part signal is exported by dout_0_r, and imaginary signals are exported by dout_1_i； When Counter Value is 1, solid part signal is exported by dout_0_i, and imaginary signals are exported by dout_1_r.
SFB modules 2 include an IFFT module and a PPN module, and it is as shown in Figure 3 that intermodule is connected with each other mode. Wherein, IFFT modules use stream treatment pattern, and input data and output data are continuous data, and FPGA cores can be used directly Piece manufacturer provides the stream treatment pattern of IP kernel or voluntarily writes, but should ensure that inputoutput data is continuous data.
PPN modules of the present invention complete the multiphase filtering network in FBMC modulators when overlap factor K takes 4, should Module includes that the filter coefficient completed of 6 time delay modules, 8 multiplication modules, 2 adder Modules, 4 ROM generates mould Block and control signal generation module, it is as shown in Figure 4 that intermodule is connected with each other mode.Wherein, filter uses PHYDYAS prototypes Filter, filter coefficient are determined by K and IFFT exponent numbers M, and obtained filter coefficient is sampled by K and is stored respectively to 4 In ROM, the filter coefficient that convolutional calculation uses is provided for PPN.6 time delay modules are divided into 2 groups and work at the same time, and extraction K is same Data on one subcarrier are sent to multiplier and carry out operation, and delay depth is M.The operation of real part imaginary part is multiplied using 4 respectively Musical instruments used in a Buddhist or Taoist mass and four input summers complete convolution algorithm.Entire PPN modules are by controlling signal generation module with controlling ROM Location and output data useful signal.
Data delay module 3 of the present invention is made of three time delay modules, the FBMC symbols that even-numbered channels is modulated Be delayed the output of half symbols period, wherein the delay depth of time delay module is M/2.
The FBMC symbols of two path channels are superimposed by adder Module 4, and 2 road complex signal of input exports 1 road complex signal, Output data length is determined by symbol quantity N, IFFT order of modulation M and overlap factor K.
In conclusion the present invention devises a kind of design method of the FBMC/OQAM modulators suitable for FPGA, this is used The FBMC/OQAM modulators of method design use 16 multipliers, 5 adders and 2 IFFT modules altogether, can be directly used for FPGA, and effectively reduce in the case where ensureing the continuous inputoutput data of modulator the use of mathematics operation module.
The application effect of the present invention is explained in detail with reference to emulation.
The time stimulatiom figure of embodiment of the present invention as shown in figure 5, clk is the unified clock signal that module uses, Din_r and din_i is respectively the real part and imaginary part of input signal, and din_en is enabled for input signal, dout_r and dout_i points The real part and imaginary part of signal after Biao Shi not modulating, dout_valid are that signal is enabled after modulating.After measured, output signal is input The signal that signal obtains after FBMC/OQAM is modulated, data processing are always delayed 219 clock lengths, and it is long to be less than 4 symbols Degree, illustrates that the modulation of FBMC/OQAM signals can be rapidly completed in the present embodiment.
The FPGA resource service condition of embodiment of the present invention is as shown in Figure 6, wherein RAM resource occupation 5, mainly Generation for ROM；DSP resource occupation 56 is mainly used for IFFT modules and multiplier；Fpga logic resource occupation 3158, It is mainly used for embodiment remainder module.As shown in fig. 6, it is only that resource is total that the FPGA resource of embodiment of the present invention, which occupies, The 1% of amount illustrates that the present embodiment can complete the design of modulator with a small amount of FPGA resource.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.

Claims (9)

1. a kind of FBMC/OQAM modulating control systems for FPGA, which is characterized in that the FBMC/OQAM for FPGA Modulating control system includes：
OQAM preprocessing modules, the alternating mapping for completing QAM mappings and odd number even-numbered channels；
Synthesis filter group module, for being respectively molded odd-numbered channels symbol and even-numbered channels symbol-modulated；
Data delay module, for the modulation symbol of even-numbered channels to be postponed 1/2 symbol time length；
Adder Module completes the modulation of FBMC/OQAM signals for the modulation symbol of two path channels to be superimposed.
2. being used for the FBMC/OQAM modulating control systems of FPGA as described in claim 1, which is characterized in that the comprehensive filter Wave device group module includes an IFFT module and a PPN module；
IFFT modules use stream treatment pattern, and input data and output data are continuous data, directly use fpga chip Manufacturer provides the stream treatment pattern of IP kernel or voluntarily writes；
PPN modules complete the multiphase filtering network in FBMC modulators when overlap factor K takes 4；Mould is generated by controlling signal Block controls the addresses ROM and output data useful signal.
3. being used for the FBMC/OQAM modulating control systems of FPGA as claimed in claim 2, which is characterized in that the PPN modules The filter coefficient generation module completed including 6 time delay modules, 8 multiplication modules, 2 adder Modules, 4 ROM with And control signal generation module；
Filter coefficient is determined that obtained filter coefficient is sampled by K and stored respectively into 4 ROM by K and IFFT exponent numbers M, The filter coefficient that convolutional calculation uses is provided for PPN；
Time delay module extracts the data on K same subcarriers and send to multiplier progress operation, and delay depth is M；
The operation of real part imaginary part uses 4 multipliers and four input summers to complete convolution algorithm respectively.
4. being used for the FBMC/OQAM modulating control systems of FPGA as described in claim 1, which is characterized in that the data are prolonged When module be made of three time delay modules, by even-numbered channels modulation FBMC symbols delay the half symbols period output, be delayed mould The delay depth of block is M/2.
5. being used for the FBMC/OQAM modulating control systems of FPGA as described in claim 1, which is characterized in that the adder The FBMC symbols of two path channels are superimposed by module, and 2 road complex signal of input exports 1 road complex signal, and output data length is by according with Number amount N, IFFT order of modulation M and overlap factor K are determined.
6. a kind of FBMC/OQAM for FPGA for the FBMC/OQAM modulating control systems of FPGA as described in claim 1 Modulation control method, which is characterized in that the FBMC/OQAM modulation control methods for FPGA include：
The alternating mapping of step 1, QAM mappings and odd number even-numbered channels；
Odd-numbered channels symbol and even-numbered channels symbol-modulated are molded by step 2；
The modulation symbol of step 3, even-numbered channels postpones 1/2 symbol time length；
Step 4, the modulation symbol superposition of two path channels, completes the modulation of FBMC/OQAM signals.
7. the FBMC/OQAM modulation control methods for FPGA as claimed in claim 6, which is characterized in that the step One specifically includes：
(1) input signal is subjected to QAM modulation, obtains modulated complex signal；
(2) real and imaginary parts of modulated complex signal are detached；
(3) the actual situation mapping that enable signal controls a digit counter with control module output signal is inputted according to data；
(4) when Counter Value is 0, solid part signal is exported by dout_0_r, and imaginary signals are exported by dout_1_i；Counter Value is When 1, solid part signal is exported by dout_0_i, and imaginary signals are exported by dout_1_r.
8. the FBMC/OQAM modulation control methods for FPGA as claimed in claim 6, which is characterized in that the step Two specifically include：
(1) odd-numbered channels input signal is completed into IFFT transformation, obtaining serial complex signal and data makes by IFFT modules It can signal；
(2) the data enable signal input control signal generation module for exporting IFFT modules, by the enabled delay (K-1) of the data M time spans are simultaneously taken with original signal or, generating addr signals, and the T that is delayed using obtained signal control counterpTime is long Degree, obtains data_valid signals, TpIt is defined by following formula：
Tp=Tmul+Tadd；
Wherein, TmulIndicate multiplier processing delay, TaddIndicate adder processing delay；
(3) the addr signals obtained in (2) are input in four ROM, the ports dout output filter coefficient signal；
(4) the real part imaginary part of the serial complex signal obtained in (1) is continued through into the identical delay of three delay depth respectively Module, wherein delay depth is M；
(5) the real part imaginary part difference of three obtained complex signal in the complex signal obtained in (1) and (4) is corresponding (3) in obtained four filter coefficient signal multiplications, obtained result is input in two adders, obtains output signal Real part dout_r and imaginary part dout_i；
(6) even-numbered channels input signal repeats (1)~(5)；
The step 3 includes：
(1) data in even-numbered channels are enabled into data_valid and is input to time delay module, delay depth is M/2, is delayed Data afterwards are enabled；
(2) the real part imaginary part of the complex signal in even-numbered channels is separately input into the identical time delay module of delay depth, delay Depth is M/2, the complex signal after being delayed；
The step 4 specifically includes：
(1) data of odd-numbered channels input are enabled the input of din_0_en and even-numbered channels data enable din_1_en take or, It obtains output data and enables data_valid；
(2) complex signal that odd-numbered channels inputs is added with the complex signal that even-numbered channels inputs, the plural number letter exported Number, real part dout_r, imaginary part dout_i.
9. a kind of modulation using the FBMC/OQAM modulating control systems for being used for FPGA described in Claims 1 to 5 any one Device.
CN201810217449.1A 2018-03-16 2018-03-16 FBMC/OQAM modulation control system and method for FPGA, and modulator Active CN108650204B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810217449.1A CN108650204B (en) 2018-03-16 2018-03-16 FBMC/OQAM modulation control system and method for FPGA, and modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810217449.1A CN108650204B (en) 2018-03-16 2018-03-16 FBMC/OQAM modulation control system and method for FPGA, and modulator

Publications (2)

Publication Number Publication Date
CN108650204A true CN108650204A (en) 2018-10-12
CN108650204B CN108650204B (en) 2021-10-12

Family

ID=63744256

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810217449.1A Active CN108650204B (en) 2018-03-16 2018-03-16 FBMC/OQAM modulation control system and method for FPGA, and modulator

Country Status (1)

Country Link
CN (1) CN108650204B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110191076A (en) * 2019-05-23 2019-08-30 武汉恒泰通技术有限公司 The transmission method of data in a kind of FBMC system
CN114826838A (en) * 2022-05-19 2022-07-29 南京信息工程大学 Channel estimation algorithm of FBMC (fiber Bragg Grating) radar communication integrated system based on leader sequence

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102810086A (en) * 2011-05-30 2012-12-05 中国科学院微电子研究所 Fast Fourier transform butterfly operation processing device and data processing method
CN106789828A (en) * 2016-12-26 2017-05-31 中南大学 A kind of method that FBMC OQAM system peak-to-average power ratios are reduced based on peak time tracking feedback
JP2018007056A (en) * 2016-07-04 2018-01-11 日本電信電話株式会社 Radio communication system, radio transmission device and radio reception device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102810086A (en) * 2011-05-30 2012-12-05 中国科学院微电子研究所 Fast Fourier transform butterfly operation processing device and data processing method
JP2018007056A (en) * 2016-07-04 2018-01-11 日本電信電話株式会社 Radio communication system, radio transmission device and radio reception device
CN106789828A (en) * 2016-12-26 2017-05-31 中南大学 A kind of method that FBMC OQAM system peak-to-average power ratios are reduced based on peak time tracking feedback

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
罗潇景: "基于滤波器组的多载波（FBMC）调制的优化算法设计及实现", 《中国优秀硕士论文电子期刊网，信息科技辑》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110191076A (en) * 2019-05-23 2019-08-30 武汉恒泰通技术有限公司 The transmission method of data in a kind of FBMC system
CN114826838A (en) * 2022-05-19 2022-07-29 南京信息工程大学 Channel estimation algorithm of FBMC (fiber Bragg Grating) radar communication integrated system based on leader sequence
CN114826838B (en) * 2022-05-19 2023-04-25 南京信息工程大学 Channel estimation algorithm of FBMC radar communication integrated system based on preamble sequence

Also Published As

Publication number Publication date
CN108650204B (en) 2021-10-12

Similar Documents

Publication Publication Date Title
CN105635022B (en) A kind of offset quadrature multicarrier baseband system
CN103297373B (en) Permanent envelope orthogonal frequency-division complex modulation method
KR100899747B1 (en) Method and apparatus for reducing peak-to-average power ratio in orthogonal frequency division multiplexing system
CN110891038B (en) Frequency domain multi-carrier modulation and demodulation method for elliptical spherical wave
CN106685887A (en) Frequency domain realizing method of UFMC transmitter for FPGA (field programmable gate array)
CN101937423B (en) Streamline FFT/IFFT processing system
CN101411153B (en) Method for mapping channel resource block and terminal equipment
CN102868459A (en) Mobile terminal simulator for a wireless telecommunications network and method to simulate a mobile terminal
CN101783781A (en) Information transmission method for lowering peak to average power ratio of OFDM system signal
CN102497350B (en) OFDM (Orthogonal Frequency Division Multiplexing) peak-to-average power ratio lowering method based on constellation linear expansion
CN102724761A (en) Dynamic resource allocation method for orthogonal frequency division multiple access (OFDMA) system
CN108650204A (en) For the FBMC/OQAM modulating control systems and method of FPGA, modulator
CN104917712A (en) Signal processing method and device
CN102835048A (en) OFDM modulator, OFDM transmission apparatus, and OFDM modulation method
CN108848047B (en) Method for realizing filter bank multicarrier transmitter
CN103458485B (en) Peak power optimization method and emission system thereof in ofdm system
CN104253782A (en) Residual carrier deviation and sampling deviation estimation method and compensation method
CN102076088B (en) Resource unit mapping method and device
Palekar et al. OFDM system using FFT and IFFT
Ganesh et al. FPGA implementation of OFDM transmitter using simulink and xilinx system generator
CN103188192B (en) It is applied to the base band processing device of video sensor
CN103488611A (en) FFT (Fast Fourier Transformation) processor based on IEEE802.11.ad protocol
Keerthana et al. FPGA implementation of FBMC baseband modular for 5G wireless communication
CN112995089A (en) Chaotic mapping-based low-complexity selective mapping method improvement method
Yan et al. Implementation of an OFDM underwater acoustic communication system on an underwater vehicle with multiprocessor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant