CN108650204B

CN108650204B - FBMC/OQAM modulation control system and method for FPGA, and modulator

Info

Publication number: CN108650204B
Application number: CN201810217449.1A
Authority: CN
Inventors: 尚磊; 刘威; 张恒伟; 殷慧慧; 韩兴忠
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2018-03-16
Filing date: 2018-03-16
Publication date: 2021-10-12
Anticipated expiration: 2038-03-16
Also published as: CN108650204A

Abstract

The invention belongs to the technical field of multi-carrier communication, and discloses an FBMC/OQAM modulation control system and method for FPGA, and a modulator, wherein the FBMC/OQAM modulation control system comprises: the OQAM preprocessing module is used for finishing QAM mapping and alternate mapping of odd and even channels; a comprehensive filter bank (SFB) module for modulating and molding the odd channel symbols and the even channel symbols respectively; a data delay module for delaying the modulation symbols of the even channels by 1/2 symbol time lengths; and the adder module is used for superposing the modulation symbols of the two channels to complete the modulation of the FBMC/OQAM signal. The invention uses the design of a fully synchronous clock, uses a production line to process the continuous modulation of the FBMC/OQAM signal, and can be used for the design of a modulator at the transmitting end of the FBMC/OQAM system on an FPGA.

Description

FBMC/OQAM modulation control system and method for FPGA, and modulator

Technical Field

The invention belongs to the technical field of multi-carrier communication, and particularly relates to an FBMC/OQAM modulation control system and method for an FPGA, and a modulator.

Background

Both the filter bank multi-carrier (FBMC) technique and the Orthogonal Frequency Division Multiplexing (OFDM) technique belong to the multi-carrier modulation technique. Currently, the OFDM technology is the most widely used multi-carrier modulation technology, and due to the advantages of its simple equalization technology, extremely low complexity caused by the application of FFT, and high spectrum utilization, etc., the OFDM technology has been widely researched. The FBMC technology uses a set of optimized filter banks to achieve the purpose of out-of-band rejection, and the FBMC transmission technology adopting quadrature amplitude modulation (OQAM) as one of the main candidate technologies of the future wireless communication technology obtains more excellent out-of-band rejection performance and reduces the requirement of orthogonality among subcarriers under the condition of meeting the same transmission efficiency as the OFDM technology. Due to the complex implementation of the FBMC/OQAM technology, it is necessary to research a compact and fast implementation manner of the technology.

Currently, the current state of the art commonly used in the industry is such that:

(1) and (3) using a frequency domain expansion implementation mode, namely multiplying the data modulated by OQAM by the frequency domain form of the prototype filter, performing IFFT (inverse fast Fourier transform) after frequency domain expansion, and finally performing serial-parallel conversion and cyclic superposition on the obtained data. At the moment, KM point IFFT transformation is needed, the calculation complexity is higher than that of M point IFFT transformation, KM multipliers are needed for frequency domain expansion operation, and in addition, a large amount of memory (RAM) resources are consumed for cyclic superposition operation;

(2) a time domain windowing mode is used, namely data after OQAM modulation is directly subjected to IFFT conversion, the data obtained by IFFT conversion is circularly copied and then subjected to windowing superposition, the number of IFFT conversion points is M, the length of a window function is KM, at least M multipliers are needed in windowing operation, and a large amount of RAM resources are consumed in superposition operation;

(3) the method uses M-point IFFT conversion, but the multiphase network needs KM multipliers, and consumes a large amount of FPGA resources while accelerating the data processing speed.

In summary, the problems of the prior art are as follows:

(1) in the frequency domain expansion and time domain windowing modes, the cyclic superposition operation can bring a large amount of RAM resource occupation and high time delay;

(2) under the condition of low time delay, the multiphase network introduces too many multipliers, and a large amount of FPGA resources are consumed;

(3) in the time domain windowing mode, due to the use of the RAM, the full-flow realization of the algorithm cannot be guaranteed, and the data operation efficiency is reduced.

Solution (II)The difficulty and significance for solving the technical problems are as follows: in order to solve the above technical problem, it is necessary to calculate the delay at the module Balance with resource consumption, reduce FPGA resource consumption, improve module portability, and greatly reduce system The adding difficulty of other functional modules in the system, and in addition, certain calculation delay can ensure the data throughput of the system and reduce The design difficulty of other complex data processing modules.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an FBMC/OQAM modulation control system and method for an FPGA, and a modulator.

The invention is realized in this way, an FBMC/OQAM modulation control system for FPGA, comprising:

the OQAM preprocessing module is used for finishing QAM mapping and alternate mapping of odd and even channels;

the comprehensive filter bank module is used for modulating and molding the odd channel symbols and the even channel symbols respectively;

a data delay module for delaying the modulation symbols of the even channels by 1/2 symbol time lengths;

and the adder module is used for superposing the modulation symbols of the two channels to complete the modulation of the FBMC/OQAM signal.

Further, the synthesis filter bank module comprises an IFFT module and a PPN module;

the IFFT module uses a flow processing mode, input data and output data are continuous data, and the flow processing mode of an IP core provided by an FPGA chip manufacturer is directly used or is written by self;

the PPN module is used for completing a multiphase filter network in the FBMC modulator when the overlap factor K is 4; the ROM address is controlled and the data valid signal is output by the control signal generation module.

Further, the PPN module includes 6 delay modules, 8 multiplier modules, 2 adder modules, 4 filter coefficient generation modules completed by the ROM, and a control signal generation module;

the filter coefficient is determined by K and IFFT order M, the obtained filter coefficient is sampled according to K and is respectively stored in 4 ROM, and the filter coefficient used by convolution calculation is provided for PPN;

the delay module extracts data on K same subcarriers and sends the data to the multiplier for operation, and the delay depth is M;

the operation of the real part and the imaginary part respectively uses 4 multipliers and a four-input adder to complete convolution operation.

Furthermore, the data delay module is composed of three delay modules, the FBMC symbol modulated by the even channel is delayed by half a symbol period and output, and the delay depth of the delay module is M/2.

Furthermore, the adder module superimposes the FBMC symbols of the two channels, inputs 2 channels of complex signals and outputs 1 channel of complex signals, and the output data length is determined by the symbol number N, IFFT modulation order M and the superposition factor K.

Another object of the present invention is to provide an FBMC/OQAM modulation control method for an FPGA of the FBMC/OQAM modulation control system for an FPGA, the FBMC/OQAM modulation control method for an FPGA comprising:

step one, QAM mapping and alternate mapping of odd and even channels;

step two, modulating and molding the odd channel symbols and the even channel symbols;

step three, the modulation symbol of the even channel is delayed by 1/2 symbol time lengths;

and step four, superposing the modulation symbols of the two channels to complete the modulation of the FBMC/OQAM signal.

Further, the first step specifically includes:

(1) carrying out QAM modulation on an input signal to obtain a modulated complex signal;

(2) separating real and imaginary parts of the modulated complex signal;

(3) controlling a one-bit counter according to the data input enable signal to control the virtual-real mapping of the module output signal;

(4) when the counter value is 0, the real part signal is output by dout _0_ r, and the imaginary part signal is output by dout _1_ i; when the counter value is 1, the real part signal is output by dout _0_ i, and the imaginary part signal is output by dout _1_ r.

Further, the second step specifically includes:

(1) the method comprises the steps that an odd channel input signal passes through an IFFT module to complete IFFT conversion, and a serial complex signal and a data enable signal are obtained;

(2) the data enable signal output by the IFFT module is input to the control signal generation module,delaying the data enable by (K-1) M time length and taking OR with the original signal, using the obtained signal to control a counter to generate an addr signal, and delaying by T_pTime length to obtain data _ valid signal, T_pDefined by the following equation:

T_p＝T_mul+T_add

wherein, T_mulRepresenting multiplier processing delay, T_addRepresenting adder processing delay.

(3) Inputting the addr signal obtained in the step (2) into four ROMs, and outputting a filter coefficient signal by a dout port;

(4) respectively and continuously passing the real part and the imaginary part of the serial complex signal obtained in the step (1) through three delay modules with the same delay depth, wherein the delay depth is M;

(5) multiplying the real parts and imaginary parts of the complex signals obtained in the step (1) and the three complex signals obtained in the step (4) with the four corresponding filter coefficient signals obtained in the step (3) respectively, and inputting the obtained results into two summers to obtain a real part dout _ r and an imaginary part dout _ i of an output signal;

(6) the even channel input signal repeats (1) to (5).

Further, the third step includes:

(1) inputting the data enable data _ valid in the even channel to a delay module, wherein the delay depth is M/2, and obtaining delayed data enable;

(2) respectively inputting real parts and imaginary parts of the complex signals in the even channels to delay modules with the same delay depth, wherein the delay depth is M/2, and obtaining delayed complex signals;

further, the fourth step includes:

(1) taking OR between data enable din _0_ en input by an odd channel and data enable din _1_ en input by an even channel to obtain output data enable data _ valid;

(2) and adding the complex signals input by the odd channels and the complex signals input by the even channels to obtain output complex signals, wherein the real part of the output complex signals is dout _ r, and the imaginary part of the output complex signals is dout _ i.

Another object of the present invention is to provide a modulator applying the FBMC/OQAM modulation control system for FPGA.

In summary, the advantages and positive effects of the invention are:the invention can be designed and compiled in an FPGA environment, needs 2M-point IFFT, 4K multipliers, 5 adders and 8 ROM, effectively controls the use of FPGA resources compared with a frequency domain expansion method and a multiphase network method which need 2KM multipliers, and can continuously and quickly complete the modulation processing of FBMC/OQAM signals by using a pipeline processing technology.

Drawings

Fig. 1 is a schematic structural diagram of an FBMC/OQAM modulation control system for FPGA according to an embodiment of the present invention;

in the figure: 1. an OQAM preprocessing module; 2. a synthesis filter bank module; 3. a data delay module; 4. and an adder module.

Fig. 2 is a flowchart of an FBMC/OQAM modulation control method for FPGA according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an SFB module according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a PPN module according to an embodiment of the present invention.

Fig. 5 is a timing simulation diagram of an FBMC/OQAM modulation control system for FPGA according to an embodiment of the present invention.

Fig. 6 is a resource consumption diagram of an FBMC/OQAM modulation control system for FPGA according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1, an FBMC/OQAM modulation control system for FPGA according to an embodiment of the present invention includes: the system comprises an OQAM preprocessing module 1, a comprehensive filter bank module 2, a data delay module 3 and an adder module 4.

The OQAM preprocessing module 1 is used for finishing QAM mapping and alternate mapping of odd and even channels;

a synthesis filter bank module 2(SFB) for modulating and molding the odd channel symbols and the even channel symbols respectively;

a data delay module 3, configured to delay modulation symbols of an even channel by 1/2 symbol time lengths;

and the adder module 4 is used for superposing the modulation symbols of the two channels to complete the modulation of the FBMC/OQAM signal.

As shown in fig. 2, the FBMC/OQAM modulation control method for FPGA according to the embodiment of the present invention includes the following steps:

s201: QAM mapping and alternate mapping of odd and even channels;

s202: modulating and molding the odd channel symbols and the even channel symbols;

s203: the modulation symbol delay for the even channel is 1/2 symbol time lengths;

s204: and the modulation symbols of the two channels are superposed to complete the modulation of the FBMC/OQAM signal.

The application of the principles of the present invention will now be described in further detail with reference to the accompanying drawings.

The OQAM preprocessing module 1 is a pipeline processing module, and the basic idea is to modulate QAM signals in a virtual and real interval mode. The working principle is as follows: (1) carrying out QAM modulation on an input signal to obtain a modulated complex signal; (2) separating (3) the real part and the imaginary part of the modulated complex signal to control a one-bit counter according to the data input enable signal so as to control the virtual-real mapping of the module output signal; (4) when the counter value is 0, the real part signal is output by dout _0_ r, and the imaginary part signal is output by dout _1_ i; when the counter value is 1, the real part signal is output by dout _0_ i, and the imaginary part signal is output by dout _1_ r.

The SFB module 2 includes an IFFT module and a PPN module, and the connection manner between the modules is shown in fig. 3. The IFFT module uses a pipeline processing mode, input data and output data are continuous data, the pipeline processing mode of an IP core provided by an FPGA chip manufacturer can be directly used or written by the FPGA chip manufacturer, and the input data and the output data are continuous data.

The PPN module of the invention completes the polyphase filter network in the FBMC modulator when the overlap factor K takes 4, the module comprises 6 time delay modules, 8 multiplier modules, 2 adder modules, 4 filter coefficient generating modules completed by ROM and a control signal generating module, and the mutual connection mode among the modules is shown in FIG. 4. The filter uses a PHYDYAS prototype filter, the filter coefficient is determined by K and an IFFT order M, the obtained filter coefficient is sampled according to K and is respectively stored in 4 ROMs, and the filter coefficient used for convolution calculation is provided for PPN. The 6 delay modules are divided into 2 groups to work simultaneously, and data on K same subcarriers are extracted and sent to a multiplier for operation, wherein the delay depth is M. The operation of the real part and the imaginary part respectively uses 4 multipliers and a four-input adder to complete convolution operation. The whole PPN module controls the ROM address and outputs a data effective signal through the control signal generation module.

The data delay module 3 of the present invention is composed of three delay modules, and delays the FBMC symbol modulated by the even channel by half a symbol period and outputs the delayed FBMC symbol, wherein the delay depth of the delay module is M/2.

The adder module 4 adds the FBMC symbols of the two channels, inputs 2 complex signals and outputs 1 complex signal, and the output data length is determined by the modulation order M of the symbol number N, IFFT and the overlap factor K.

In summary, the present invention designs a design method of an FBMC/OQAM modulator suitable for FPGA, where the FBMC/OQAM modulator designed by the method uses 16 multipliers, 5 adders and 2 IFFT modules in total, and can be directly used for FPGA, and effectively reduces the usage of mathematical operation modules under the condition of ensuring continuous input and output of data by the modulator.

The application effect of the present invention will be described in detail with reference to the simulation.

Fig. 5 shows a timing simulation diagram of an embodiment of the present invention, where clk is a unified clock signal used by a module, din _ r and din _ i are a real part and an imaginary part of an input signal, din _ en is an input signal enable, dout _ r and dout _ i represent a real part and an imaginary part of a modulated signal, and dout _ valid is a modulated signal enable. Through determination, the output signal is a signal obtained after the input signal is subjected to FBMC/OQAM modulation, and the total data processing delay is 219 clock lengths, which is less than 4 symbol lengths, which indicates that the embodiment can quickly complete the modulation of the FBMC/OQAM signal.

The FPGA resource usage of the embodiment of the invention is shown in FIG. 6, wherein RAM resources occupy 5 and are mainly used for ROM generation; DSP resource occupation 56, mainly used for IFFT module and multiplier; the FPGA logic resource occupation 3158 is mainly used for the rest of the modules of the embodiment. As shown in fig. 6, the occupation of the FPGA resources in the embodiment of the present invention is only 1% of the total amount of the resources, which indicates that the present embodiment can complete the design of the modulator with a small amount of FPGA resources.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. An FBMC/OQAM modulation control system for FPGA, comprising:

the adder module is used for superposing the modulation symbols of the two channels to complete the modulation of the FBMC/OQAM signals;

the comprehensive filter group module comprises an IFFT module and a PPN module;

the PPN module is used for completing a multiphase filter network in the FBMC modulator when the overlap factor K is 4; the ROM address is controlled and a data effective signal is output through a control signal generation module;

the PPN module comprises 6 time delay modules, 8 multiplier modules, 2 adder modules, a filter coefficient generation module completed by 4 ROMs and a control signal generation module;

2. The FBMC/OQAM modulation control system for FPGAs of claim 1, wherein the data delay module is composed of three delay modules, and delays the FBMC symbol modulated by the even channel by half a symbol period for output, and the delay depth of the delay module is M/2.

3. The FBMC/OQAM modulation control system for FPGAs of claim 1, wherein the adder module adds FBMC symbols of two channels, inputs 2 complex signals and outputs 1 complex signal, and the output data length is determined by the symbol number N, IFFT modulation order M and the overlap factor K.

4. The FBMC/OQAM modulation control method for FPGA of the FBMC/OQAM modulation control system for FPGA of claim 1, wherein the FBMC/OQAM modulation control method for FPGA comprises:

step one, QAM mapping and alternate mapping of odd and even channels;

5. The FBMC/OQAM modulation control method for FPGA of claim 4, wherein the step one specifically comprises:

(2) separating real and imaginary parts of the modulated complex signal;

6. The FBMC/OQAM modulation control method for FPGA of claim 4, wherein the second step specifically comprises:

(2) inputting the data enable signal output by the IFFT module into a control signal generation module, delaying the data enable by (K-1) M time length and taking or with the original signal, using the obtained signal to control a counter to generate an addr signal, and delaying by T_pTime length to obtain data _ valid signal, T_pDefined by the following equation:

T_p＝T_mul+T_add；

wherein, T_mulRepresenting multiplier processing delay, T_addRepresenting adder processing delays;

(6) repeating (1) - (5) for the even channel input signal;

the third step comprises:

the fourth step specifically comprises:

7. A modulator applying the FBMC/OQAM modulation control method for the FPGA according to any one of claims 1-6.