CN108649020A - The packaging method of stacked chips and the packaging body manufactured using this method - Google Patents
The packaging method of stacked chips and the packaging body manufactured using this method Download PDFInfo
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- CN108649020A CN108649020A CN201810477550.0A CN201810477550A CN108649020A CN 108649020 A CN108649020 A CN 108649020A CN 201810477550 A CN201810477550 A CN 201810477550A CN 108649020 A CN108649020 A CN 108649020A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention provides a kind of packaging method of stacked chips and the packaging body using this method manufacture, and described method includes following steps：One lead frame is provided；First layer chip is placed on the lead frame；A conductive chip arrays are provided, the conduction chip arrays include multiple conductive sheets；The conductive chip arrays are cut, keep at least one conductive sheet independent；At least one conductive sheet is arranged on the first layer chip.The invention has the advantages that avoiding the space waste in existing conductive sheet array frame layout, the density of conductive sheet array frame can be effectively improved, and then reduce the cost of conductive sheet array frame；The shape and size design of conductive sheet are no longer punched process capability and are limited, and design is more flexible, can meet greater demand；It does not need traditional rushing and has making demand, carry out cutter and can be completed, save the investment in terms of rushing tool, and conductive sheet array frame manufacturing speed is very fast, can fully meet the requirement of quick consumer Electronics Design research and development quick response.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to the packaging methods and use party legal system of a kind of stacked chips
The packaging body made.
Background technology
QFN/DFN products usually there will be the case where being packaged using stacked chips, can use and lead between upper and lower chip
Electric piece is attached.Fig. 1 is a kind of existing packaging body being packaged using dual chip stacking.Referring to Fig. 1, plastic packaging lead
Frame and the isostructural plastic-sealed body 14 of chip are painted using dotted line, in the package, are arranged on lead frame 10
There are four first layer chips 11, and multiple conductive sheets 12 are provided on first layer chip 11, and a second layer chip 13 is arranged in institute
The upper surface of conductive sheet 12 is stated, and then is connected to first layer chip 11 and second layer chip 13 by conductive sheet 12.
In the packaging body of this type, it will usually need to use many conductive sheets (clip), moreover, for miniaturization
Packaging body, it is required that conductive sheet is small-sized.Fig. 2 is the structural schematic diagram of existing conductive chip arrays, wherein using dotted line frame A
Schematic geosphere shows the corresponding conductive blade unit of a packaging body, is schematically painted two conductive blade units in fig. 2.
In the step of conductive sheet 20 is welded on first layer chip, have conductive chip arrays described in direct punching press using punching, after the completion of punching press,
Multiple conductive sheets 20 are directly moved by mobile tool, conductive sheet 20 is made to be welded with the first layer chip.
This kind of method has the disadvantage that：1, since to be directly moved to first layer chip enterprising for the conductive sheet 20 after punching press
Row welding, therefore, the arrangement needs of conductive sheet 20 are corresponding with the arrangement of first layer chip, for example, as shown in Fig. 2, adjacent two
Depending on the distance between a conductive sheet 20 needs the distribution according to first layer chip, between adjacent two conductive blade units away from
From will be depending on the distribution between two packaging bodies, this may result in the upper many space waves of conductive sheet array frame design
Take, influences the density of conductive sheet array frame, and then influence the cost of conductive sheet array frame；2, it is limited by existing punching tool
System, the size of each conductive sheet cannot be too small, for the product that more conductive sheets assemble simultaneously, between adjacent two conductive sheets
Distance cannot be too small, this results in the design idea for using the packaging body of this method formation to cannot achieve the packaging body, Wu Faman
The actual requirement of foot；3, in punching press, there are surpluses for the side needs of conductive sheet so that the side of conductive sheet has residual knot
Structure leads to the side out-of-flatness of conductive sheet；4, have punching press using punching, punching burr can be generated at punching press, influences properties of product.
Invention content
It is manufactured the technical problem to be solved by the invention is to provide a kind of packaging method of stacked chips and using this method
Packaging body, the cost of conductive sheet array frame can be reduced, meet greater demand.
To solve the above-mentioned problems, the present invention provides a kind of packaging method of stacked chips, include the following steps：It provides
One lead frame；First layer chip is placed on the lead frame；A conductive chip arrays are provided, the conduction chip arrays include
Multiple conductive sheets；The conductive chip arrays are cut, keep at least one conductive sheet independent；At least one conductive sheet is arranged described
On first layer chip.
In one embodiment, further include one on the conductive chip arrays before cutting the conductive sheet array step
The step of pasting a support membrane.
In one embodiment, a surface of the conductive sheet has the protrusion for being connect with first layer chip, then is inciting somebody to action
At least one conductive sheet is arranged in the step on the first layer chip, and conductive sheet is arranged described using the method for upside-down mounting
On first layer chip, the protrusion is connect with first layer chip.
In one embodiment, it after the step on the first layer chip is arranged at least one conductive sheet, also wraps
One is included the step of second layer chip is set on the conductive sheet.
In one embodiment, include the following steps：Before cutting the conductive sheet array step, by second layer chip with
One surface of corresponding conductive sheet connects；The conductive chip arrays are cut, keep the conductive sheet being connect with the second layer chip only
It is vertical；
By the conductive sheet being connect with the second layer chip be arranged on the first layer chip, the conductive sheet it is another
Surface is connect with the first layer chip.
In one embodiment, further include one on the conductive chip arrays before cutting the conductive sheet array step
The step of pasting a support membrane.
The present invention also provides a kind of packaging body of stacked chips, the packaging body includes a lead frame, first layer chip
And at least one conductive sheet, the first layer chip are arranged on the lead frame, the conductive sheet is arranged described first
On layer chip, the lower surface of the conductive sheet is connect with the first layer chip, and the conductive sheet is vertical with the lower surface
The surfacing of side wall.
In one embodiment, the packaging body further includes a second layer chip, and the second layer chip setting is led described
Electric on piece, and connect with the upper surface of the conductive sheet.
In one embodiment, the lower surface of the conductive sheet has at least one protrusion, the protrusion and the first layer core
Piece connects.
It is an advantage of the current invention that the space waste in existing conductive sheet array frame layout is avoided, it can be effective
The density of conductive sheet array frame is improved, and then reduces the cost of conductive sheet array frame；The shape and size design of conductive sheet
It is no longer punched process capability to be limited, without minimum punching pitch requirements, not extra punching stays side, is not punched burr
The problem of, there is no frame width design limitation, design is more flexible, can meet greater demand；Not needing traditional tool making of rushing needs
It asks, carries out cutter and can be completed, save the investment in terms of rushing tool, and conductive sheet array frame manufacturing speed is very fast, can fill
Divide the requirement for meeting quick consumer Electronics Design research and development quick response.
Description of the drawings
Fig. 1 is a kind of existing packaging body being packaged using dual chip stacking；
Fig. 2 is the structural schematic diagram of existing conductive chip arrays；
Fig. 3 is the first embodiment step schematic diagram of the packaging method of stacked chips of the present invention；
Fig. 4 A~Fig. 4 H are the process flow charts of the first embodiment of the packaging method of stacked chips of the present invention；
Fig. 5 A~Fig. 5 H are the process flow charts of the second embodiment of the packaging method of stacked chips of the present invention；
Fig. 6 is the 3rd embodiment step schematic diagram of the packaging method of stacked chips of the present invention；
Fig. 7 A~Fig. 7 H are the process flow charts of the second embodiment of the packaging method of stacked chips of the present invention；
Fig. 8 is the structural schematic diagram of one embodiment of the packaging body of stacked chips of the present invention；
Fig. 9 is the structural schematic diagram of conductive sheet.
Specific implementation mode
Packaging method to stacked chips provided by the invention and the packaging body using this method manufacture below in conjunction with the accompanying drawings
Specific implementation mode elaborate.
Fig. 3 is the first embodiment step schematic diagram of the packaging method of stacked chips of the present invention, referring to Fig. 3, this
In one embodiment, the packaging method includes the following steps：Step S30, one lead frame is provided；Step S31, in the lead
First layer chip is placed on frame；Step S32, a conductive chip arrays are provided, the conduction chip arrays include multiple conductive sheets；Step
Rapid S33, the cutting conductive chip arrays, keep at least one conductive sheet independent；Step S34, at least one conductive sheet is arranged
On the first layer chip；Second layer chip is arranged in step S35 on the conductive sheet.
Fig. 4 A~Fig. 4 H are the process flow charts of the first embodiment of the packaging method of stacked chips of the present invention.
Step S30 and Fig. 4 A is please referred to, a lead frame 400 is provided.The lead frame 400 includes multiple base islands 401,
Each Ji Dao can place an at least chip.The structure of the lead frame 400 is the conventional structure of existing stacked chips encapsulation.
Step S31 and Fig. 4 B is please referred to, first layer chip 410 is placed on the lead frame 400, in the present embodiment
In, it places a chip respectively on the base island 401, forms first layer chip 410.The first layer chip 410 can be used
Conventional chip is pasted method on the lead frames and is pasted.
Step S32 and Fig. 4 C is please referred to, provides a conductive chip arrays 420, the conduction chip arrays 420 include multiple conductions
Piece 421.In the conductive chip arrays 420, multiple conductive sheets 421 are arranged in order and are connected to each other by even muscle 422.
Step S33, Fig. 4 D and Fig. 4 E is please referred to, the conductive chip arrays 420 is cut using cutting tool 425, makes at least
One conductive sheet 421 is independent.In this step, the conductive chip arrays 420 are cut using conventional tools such as cutter,
So that the conductive sheet 421 is detached from the conductive chip arrays 420, for example, the cutting even muscle 422, so that the conductive sheet
421 detach from the conductive chip arrays 420.Fig. 4 E are the structural schematic diagram of single conductive sheet 421 after cutting
Before the cutting stage, further include the steps that one pasting a support membrane 423 at conductive 420 back side of chip arrays.Such as
Shown in Fig. 4 C, the support membrane 423 is pasted at 420 back side of the conductive chip arrays, is scattered to avoid conductive sheet 421 when cutting.
The support membrane 423 is the membrane structure of routine, for example, common indigo plant film in semiconductor packages.When carrying out step S34, then will
The single conductive sheet 421 is removed from the support membrane 423.
Step S34 and Fig. 4 F is please referred to, at least one conductive sheet 421 is arranged on the first layer chip 410.It is described
The mode that conventional chip formal dress can be used in conductive sheet 421 is mounted.In the present embodiment, first layer chip 410 is adjacent
Two chips connected using conductive sheet 421.
Step S35 and Fig. 4 G is please referred to, second layer chip 430 is set on the conductive sheet 421.The second layer chip
430 may include multiple chips, also can be only a chip, and in the present embodiment, only there are one cores for the second layer chip 430
Piece, the chip are connect with two conductive sheets 421, and then realize the connection of first layer chip 410 and second layer chip 430.
If needing the connection of progress third layer chip, then led in attachment conductive sheet 421 on second layer chip 430
Electric on piece mounts third layer chip, and so on, form the structure that multilayer chiop stacks.
After step S35, such as Fig. 4 H, chip is connect by routing by metal wire 440 with lead frame.Subsequently also need
Plastic packaging is carried out, the packaging body of stacked chips is formed.
Conductive sheet segmentation is independent after individual and is mounted again with chip by the packaging method of stacked chips of the present invention, leads
The arrangement of electric piece will not be influenced by chip distribution, and in conductive chip arrays, conductive sheet can closely arrange, and effectively improve conduction
The density of chip arrays reduces the cost of conductive sheet array frame.
The packaging method of stacked chips of the present invention also provides second embodiment.The second embodiment and first embodiment
Difference lies in a second embodiment, second layer chip is welded with first layer chip again after first being welded with conductive sheet.It illustrates
It is as follows.
Fig. 5 A~Fig. 5 H are the process flow charts of the second embodiment of the packaging method of stacked chips of the present invention.
Fig. 5 A are please referred to, a lead frame 500 is provided.The lead frame 500 includes multiple base islands 501, each Ji Dao
An at least chip can be placed.The structure of the lead frame 500 is the conventional structure of existing stacked chips encapsulation.
Fig. 5 B are please referred to, first layer chip 510 are placed on the lead frame 500, in the present embodiment, in the base
A chip is placed on island 501 respectively, forms first layer chip 510.It is glutinous that conventional chip can be used in the first layer chip 510
The method of patch on the lead frames is pasted.
Fig. 5 C are please referred to, provide a conductive chip arrays 520, the conduction chip arrays 520 include multiple conductive sheets 521.
In the conduction chip arrays 520, multiple conductive sheets 521 are arranged in order and are connected to each other by even muscle 522.
Fig. 5 D are please referred to, second layer chip 530 is connected with a surface of corresponding conductive sheet 521.In the present embodiment,
The second layer chip 530 includes a chip, which connect with two conductive sheets 521.
Fig. 5 E and Fig. 5 F are please referred to, the conductive chip arrays 520 is cut using cutting tool 525, makes and the second layer
The conductive sheet 521 that chip 530 connects is independent, forms the structure that second layer chip 530 is connect with conductive sheet 521.Fig. 5 F are cuttings
The structural schematic diagram that second layer chip 530 is connect with conductive sheet 521 afterwards
Before being cut, further include the steps that one pasting a support membrane 523 at conductive 520 back side of chip arrays.Such as Fig. 5 C
Shown, the support membrane 523 is pasted at 520 back side of the conductive chip arrays, is scattered to avoid conductive sheet 521 when cutting.It is described
Support membrane 523 is the membrane structure of routine, for example, common indigo plant film in semiconductor packages.
Fig. 5 G are please referred to, the conductive sheet 521 being connect with the second layer chip 530 is arranged in the first layer chip
On 510, another surface of the conductive sheet 521 is connect with the first layer chip 510.Routine can be used in the conductive sheet 521
The mode of chip formal dress mounted.In the present embodiment, the second layer chip 530 is only there are one chip, the chip with
Two conductive sheets 521 connect, and then realize the connection of first layer chip 510 and second layer chip 530.
If needing the connection of progress third layer chip, then led in attachment conductive sheet 521 on second layer chip 530
Electric on piece mounts third layer chip, and so on, form the structure that multilayer chiop stacks.
Such as Fig. 5 H, chip is connect by routing by metal wire 540 with lead frame.It is follow-up to also need to carry out plastic packaging, it is formed
The packaging body of stacked chips.
First embodiment of the invention is the packaging method for the flat conductive sheet in surface, and is had " pressure is deep " for surface
The conductive sheet of structure, the present invention also provides a kind of packaging methods.
Fig. 6 is the 3rd embodiment step schematic diagram of the packaging method of stacked chips of the present invention, referring to Fig. 6, this
In three embodiments, the packaging method includes the following steps：Step S60, one lead frame is provided；Step S61, in the lead
First layer chip is placed on frame；Step S62, a conductive chip arrays are provided, the conduction chip arrays include multiple conductive sheets, institute
A surface of conductive sheet is stated with the protrusion for being connect with first layer chip；Step S63, the conductive chip arrays are cut, are made
At least one conductive sheet is independent；Step S64, conductive sheet is arranged on the first layer chip using the method for upside-down mounting, it is described
It is raised to be connect with the first layer chip；Second layer chip is arranged in step S65 on the conductive sheet.
Fig. 7 A~Fig. 7 H are the process flow charts of the second embodiment of the packaging method of stacked chips of the present invention.
Step S60 and Fig. 7 A is please referred to, a lead frame 700 is provided.The lead frame 700 includes multiple base islands 701,
Each Ji Dao can place an at least chip.The structure of the lead frame 700 is the conventional structure of existing stacked chips encapsulation.
Step S61 and Fig. 7 B is please referred to, first layer chip 710 is placed on the lead frame 700, in the present embodiment
In, it places a chip respectively on the base island 701, forms first layer chip 710.The first layer chip 710 can be used
Conventional chip is pasted method on the lead frames and is pasted.
Step S62 and Fig. 7 C is please referred to, provides a conductive chip arrays 720, the conduction chip arrays 720 include multiple conductions
Piece 721.In the conductive chip arrays 720, multiple conductive sheets 721 are arranged in order and are connected to each other by even muscle 722.It is described to lead
One surface of electric piece 721 has the protrusion 724 for being connect with first layer chip 710, and described raised 724 be described above
" pressure is deep " structure, in the present embodiment, there are two the protrusions 724 being oppositely arranged for the surface tool of the conductive sheet 721.
Step S63, Fig. 7 D and 7E are please referred to, the conductive chip arrays 720 is cut using cutting tool 725, makes at least one
A conductive sheet 721 is independent.In this step, the conductive chip arrays 720 are cut using conventional tools such as cutter, with
The conductive sheet 721 is set to be detached from the conductive chip arrays 720, for example, the cutting even muscle 722, so that the conductive sheet 721
It is detached from the conductive chip arrays 420.Fig. 7 E are the structural schematic diagrams of single conductive sheet 721 after cutting.
Before the cutting stage, further include the steps that one pasting a support membrane 723 at conductive 720 back side of chip arrays.Such as
Shown in Fig. 7 C, the support membrane 723 is pasted at conductive 720 back side of chip arrays, i.e., the support membrane 723 is pasted leads described
Electric piece 721 is scattered without the one side of protrusion 724 to avoid conductive sheet 721 when cutting.The support membrane 723 is the film knot of routine
Structure, for example, common indigo plant film in semiconductor packages.When carrying out step S34, then by the single conductive sheet 721 from described
It is removed on support membrane 723.
Step S64 and Fig. 7 F is please referred to, conductive sheet 721 is arranged in the first layer chip 710 using the method for upside-down mounting
On, described raised 724 connect with the first layer chip 710.In the present embodiment, adjacent two of first layer chip 710
Chip is connected using a conductive sheet 721.The method of the upside-down mounting refers to overturning conductive sheet 721, and conductive sheet 721 is made to have
The one of protrusion 724 is facing towards first layer chip 710.
Step S65 and Fig. 7 G is please referred to, second layer chip 730 is set on the conductive sheet 721.The second layer chip
730 may include multiple chips, also can be only a chip, and in the present embodiment, only there are one cores for the second layer chip 730
Piece, the chip are connect with two conductive sheets 721, and then realize the connection of first layer chip 710 and second layer chip 730.
If needing the connection of progress third layer chip, then led in attachment conductive sheet 721 on second layer chip 730
Electric on piece mounts third layer chip, and so on, form the structure that multilayer chiop stacks.
After step S65, such as Fig. 7 H, chip is connect by routing by metal wire 740 with lead frame.Subsequently also need
Plastic packaging is carried out, the packaging body of stacked chips is formed.
The present invention also provides a kind of packaging body of stacked chips, the packaging body is sealed using above-mentioned packaging method
Dress.Fig. 8 is the structural schematic diagram of one embodiment of the packaging body of stacked chips of the present invention.Referring to Fig. 8, the packaging body packet
Include a lead frame 400, first layer chip 410 and at least one conductive sheet 421.The first layer chip 410 is arranged described
On lead frame 400, the conductive sheet 421 be arranged on the first layer chip 410, the lower surface of the conductive sheet 421 with
The first layer chip 410 connects.
Further, the packaging body further includes a second layer chip 430, and the setting of second layer chip 430 is led described
On electric piece 421, and it is connect with the upper surface of the conductive sheet 421.If the also connection of third layer chip, then in second layer core
Conductive sheet is mounted on piece 730, third layer chip is mounted on conductive sheet, and so on, form the structure that multilayer chiop stacks.It is logical
Metal wire 440 is crossed to connect chip with lead frame.Wherein, packaging body of the present invention further includes a plastic-sealed body 800, the plastic-sealed body
800 plastic package chips, metal wire and lead frame form the packaging body of stacked chips.
Wherein, the surfacing of the side wall vertical with the lower surface of the conductive sheet 421.In order to clearly illustrate conductive sheet
421 structure separates the conductive sheet 421, and Fig. 9 is the structural schematic diagram of conductive sheet 421.Referring to Fig. 9, described lead
The sidewall surfaces of electric piece 421 are without protrusion, surfacing.And existing this kind of packaging body, after sidewall surfaces have punching press
The residual structural left leads to the side out-of-flatness of conductive sheet, influences properties of product.In another embodiment, the conductive sheet
There is at least one raised (protrusion 724 in such as Fig. 7 C), the protrusion to be connect with the first layer chip 410 for 421 lower surface.
The surfacing of the side wall of the conductive sheet of the packaging body of stacked chips of the present invention, there is no the residual knots after punching press
Structure, and generated without punching burr, improve the performance of product.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (9)
1. a kind of packaging method of stacked chips, which is characterized in that include the following steps：
One lead frame is provided；
First layer chip is placed on the lead frame；
A conductive chip arrays are provided, the conduction chip arrays include multiple conductive sheets；
The conductive chip arrays are cut, keep at least one conductive sheet independent；
At least one conductive sheet is arranged on the first layer chip.
2. the packaging method of stacked chips according to claim 1, which is characterized in that cutting the conductive chip arrays step
Further include the steps that one pasting a support membrane on the conductive chip arrays before rapid.
3. the packaging method of stacked chips according to claim 1, which is characterized in that a surface of the conductive sheet has
Then the step on the first layer chip is being arranged at least one conductive sheet by the protrusion for being connect with first layer chip
In, conductive sheet is arranged on the first layer chip using the method for upside-down mounting, the protrusion is connect with first layer chip.
4. the packaging method of stacked chips according to claim 1, which is characterized in that be arranged by least one conductive sheet
After step on the first layer chip, further include the steps that one on the conductive sheet be arranged second layer chip.
5. the packaging method of stacked chips according to claim 1, which is characterized in that include the following steps：
Before cutting the conductive sheet array step, second layer chip is connected with a surface of corresponding conductive sheet；
The conductive chip arrays are cut, keep the conductive sheet being connect with the second layer chip independent；
The conductive sheet being connect with the second layer chip is arranged on the first layer chip, another surface of the conductive sheet
It is connect with the first layer chip.
6. the packaging method of stacked chips according to claim 5, which is characterized in that cutting the conductive chip arrays step
Further include the steps that one pasting a support membrane on the conductive chip arrays before rapid.
7. a kind of packaging body of stacked chips, which is characterized in that the packaging body includes a lead frame, first layer chip and extremely
A few conductive sheet, the first layer chip are arranged on the lead frame, and the conductive sheet is arranged in the first layer core
On piece, the lower surface of the conductive sheet are connect with the first layer chip, the conductive sheet side wall vertical with the lower surface
Surfacing.
8. the packaging body of stacked chips according to claim 7, which is characterized in that the packaging body further includes a second layer
Chip, the second layer chip setting are connect on the conductive sheet, and with the upper surface of the conductive sheet.
9. the packaging body of stacked chips according to claim 7, which is characterized in that the lower surface of the conductive sheet has extremely
A few protrusion, the protrusion are connect with the first layer chip.
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| CN201810477550.0A CN108649020A (en) | 2018-05-18 | 2018-05-18 | The packaging method of stacked chips and the packaging body manufactured using this method |
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| CN201810477550.0A CN108649020A (en) | 2018-05-18 | 2018-05-18 | The packaging method of stacked chips and the packaging body manufactured using this method |
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Application publication date: 20181012 |