CN108632142B

CN108632142B - Routing management method and device of node controller

Info

Publication number: CN108632142B
Application number: CN201810262549.6A
Authority: CN
Inventors: 陈旭灿; 刘钢
Original assignee: Huawei Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2018-03-28
Filing date: 2018-03-28
Publication date: 2021-02-12
Anticipated expiration: 2038-03-28
Also published as: CN108632142A

Abstract

The embodiment of the application provides a routing management method and a device of a node controller, wherein the method comprises the following steps: judging whether each link where the target NC is located has a fault according to the state information of the target NC connected with the substrate controller; if a fault link exists, sending first routing configuration information to a target NC, and sending second routing configuration information to a to-be-configured NC corresponding to the fault link, wherein the first routing configuration information is used for the target NC to obtain first routing information to the to-be-configured NC, the second routing configuration information is used for the to-be-configured NC to obtain second routing information to the target NC, and the first routing information and the second routing information indicate different jump NC. According to the embodiment of the application, the jump NC indicated by the first routing information and the second routing information are different, so that the phenomenon of node deadlock caused by resource competition when the CPU connected with the target NC and the CPU connected with the NC to be configured visit each other is avoided, and the probability of system downtime is reduced.

Description

Routing management method and device of node controller

Technical Field

The present application relates to the field of computers, and in particular, to a method and an apparatus for routing management of a node controller.

Background

With the development of science and technology, the expansion capability of a Central Processing Unit (CPU) can be improved to more than 8P (that is, interconnection of more than 8 CPUs) by an external Node Controller (NC), for example, a CPU system connected by an NC can be adopted in a current mainstream 16P and 32P high performance server and a subsequent 64P product of a higher specification that can be supported.

At present, at least one NC group including 4 NCs is generally adopted to realize interconnection of a plurality of CPUs, the NCs in the NC group are connected in pairs, each NC is connected with at least one group of CPUs, and one group of CPUs is called a Quick-Path Interconnect (QPI) domain, so that cross-domain access of the CPUs can be realized.

Under the interconnection architecture, if an NC link corresponding to the shortest path where CPUs in different QPI domains perform mutual access is abnormal, forwarding needs to be performed through other NCs, that is, multiple jump NCs can be selected, which is easy to cause resource contention to cause node deadlock and cause major risk of system downtime.

Disclosure of Invention

The embodiment of the application provides a routing management method and a routing management device for a node controller, which are used for realizing that CPUs in different QPI domains can still perform mutual access and simultaneously reducing the probability of system downtime when an NC link corresponding to the shortest path for performing mutual access by CPUs in different QPI domains is abnormal.

In a first aspect, an embodiment of the present application provides a method for managing a route of a node controller, where a node controller NC group includes multiple NCs, the NCs in the same NC group are connected in pairs, each CPU group includes multiple CPUs, and each NC in the NC group is connected to at least one CPU group, and the method includes:

the method comprises the steps that a substrate controller judges whether each link where a target NC is located fails according to state information of the target NC connected with the substrate controller; the state information is used for indicating the working state of each link where the target NC is located;

if a fault link which cannot work normally exists, the substrate controller sends first routing configuration information to the target NC and a to-be-configured NC corresponding to the fault link, the first routing configuration information is used for the target NC to obtain first routing information from the NC to the to-be-configured NC, the second routing configuration information is used for the to-be-configured NC to obtain second routing information from the to-be-configured NC to the target NC, and jump NCs indicated by the first routing information and the second routing information are different.

In the scheme, the target NC corresponding to the fault link and the NC to be configured are respectively configured with the routing information reaching the other side, so that the CPU connected with the target NC and the CPU connected with the NC to be configured can still carry out mutual access; the target NC corresponding to the fault link is controlled to achieve that the jump NC corresponding to the NC to be configured is different from the jump NC corresponding to the target NC to be configured, so that the phenomenon that the CPU connected with the target NC and the CPU connected with the NC to be configured are in resource competition during mutual access to cause node deadlock is avoided, and the probability of system downtime is reduced.

In one possible design, before the target NC and the NC to be configured corresponding to the failed link, the substrate controller sends first routing configuration information to the target NC and sends second routing configuration information to the NC to be configured, the method further includes:

and the substrate controller determines the first routing configuration information and the second routing configuration information according to a dimension order routing algorithm.

In one possible design, when the target NC and the NC group in which the NCs to be configured are located include 4 NCs, the 4 NCs constitute a virtual rectangle, and the 4 NCs are four vertices of the virtual rectangle;

the dimension order routing algorithm is based on a preset condition, the preset condition is that after a first message reaches the target NC, the target NC sends the first message to a first jump NC along the edge of the virtual rectangle in the horizontal direction, and the first jump NC sends the first message to the NC to be configured along the edge of the virtual rectangle in the vertical direction;

after a second message reaches the NC to be configured, the NC to be configured can send the second message to a second jump NC along the edge of the virtual rectangle in the horizontal direction, and the second jump NC sends the second message to the target NC along the edge of the virtual rectangle in the vertical direction;

and connecting the target NC with the NC to be configured as a diagonal line of the virtual rectangle.

the dimension order routing algorithm is based on a preset condition, wherein the preset condition is that after a first message reaches the target NC, the target NC can send the first message to a first jump NC along the edge of the virtual rectangle in the vertical direction, and the first jump NC sends the first message to the NC to be configured along the edge of the virtual rectangle in the horizontal direction;

after a second message reaches the NC to be configured, the NC to be configured can send the second message to a second jump NC along the edge of the virtual rectangle in the vertical direction, and the second jump NC sends the second message to the target NC along the edge of the virtual rectangle in the horizontal direction;

In a possible design, when the target NC and the NC group in which the NC to be configured is located include 4 NCs, if the jump NC indicated by the first routing information is the first NC, the jump NC indicated by the second routing information is the second NC, and if the jump NC indicated by the first routing information is the second NC, the jump NC indicated by the second routing information is the first NC;

the first NC is any one of the 4 NCs except the target NC and the NC to be configured, and the second NC is any one of the 4 NCs except the target NC and the NC to be configured.

In a possible design, the determining, according to the state information of the NC, whether each link where the target NC is located has a fault includes:

for each associated NC connected with the target NC, if the identifier used for indicating the working state of the link formed by the target NC and the associated NC in the state information of the target NC is a first identifier, determining that the link between the target NC and the associated NC can work normally, and if the identifier used for indicating the working state of the link formed by the target NC and the associated NC is a second identifier, determining that the link between the target NC and the associated NC has a fault.

In one possible design, the first routing information and the second routing information each include a routing enable identifier, an identifier of a hop NC, and an identifier of a destination NC;

the destination NC indicated by the first routing information is the NC to be configured, and the destination NC indicated by the second routing information is the target NC.

In one possible design, the CPUs within the same group are connected two by two or in a ring.

In a second aspect, an embodiment of the present application provides a method for routing management of a node controller, where a node controller NC group includes multiple NCs, the multiple NCs in the NC group are connected in pairs, each CPU group includes multiple CPUs, and each NC in the NC group is connected with at least one CPU group, and the method includes:

the method comprises the steps that a target NC sends state information to a first substrate controller BMC, wherein the state information is used for indicating the working state of each link where the target NC is located;

if a first link in a plurality of links where the target NC is located fails, receiving first routing configuration information sent by the BMC, and obtaining first routing information from the target NC to another NC corresponding to the first link according to the first routing configuration information; and the second routing information is obtained by the other NC according to second routing configuration information sent by a second BMC.

the destination NC indicated by the first routing information is the other NC, and the destination NC indicated by the second routing information is the target NC.

In a third aspect, an embodiment of the present application further provides a routing management apparatus for a node controller, where a node controller NC group includes multiple NCs, the NCs in the same NC group are connected in pairs, each CPU group includes multiple CPUs, and each NC in the NC group is connected with at least one CPU group, and the apparatus includes:

the judging module is used for judging whether each link where the target NC is located has a fault according to the state information of the target NC connected with the substrate controller; the state information is used for indicating the working state of each link where the target NC is located;

and the sending module is used for sending first routing configuration information to the target NC and a to-be-configured NC corresponding to the fault link if the fault link incapable of working normally exists, the first routing configuration information is used for the target NC to acquire first routing information from the NC to the to-be-configured NC, the second routing configuration information is used for the to-be-configured NC to acquire second routing information from the to-be-configured NC to the target NC, and the first routing information and the second routing information respectively indicate different jump NCs.

In one possible design, the apparatus further includes a determination module to:

and determining the first routing configuration information and the second routing configuration information according to a dimension order routing algorithm.

In one possible design, when the target NC and the NC group in which the NCs to be configured are located include 4 NCs, the 4 NCs form a virtual rectangle, and the 4 NCs are four vertices of the virtual rectangle, the dimension order routing algorithm is based on a preset condition;

the preset condition is that after a first message reaches the target NC, the target NC can send the first message to a first jump NC along the edge of the virtual rectangle in the horizontal direction, and the first jump NC sends the first message to the NC to be configured along the edge of the virtual rectangle in the vertical direction;

In a possible design, the determining module is specifically configured to:

In a fourth aspect, an embodiment of the present application further provides a routing management apparatus for a node controller, where an NC group of the node controller includes multiple NCs, the multiple NCs in the NC group are connected in pairs, each CPU group includes multiple CPUs, and each NC in the NC group is connected with at least one CPU group, where the apparatus includes:

the system comprises a sending module, a first substrate controller BMC and a second substrate controller BMC, wherein the sending module is used for sending state information to the first substrate controller BMC, and the state information is used for indicating the working state of each link where a target NC is located;

a routing information obtaining module, configured to receive, if a first link of multiple links where the target NC is located fails, first routing configuration information sent by the BMC, and obtain, according to the first routing configuration information, first routing information from the target NC to another NC corresponding to the first link; and the second routing information is obtained by the other NC according to second routing configuration information sent by a second BMC.

In a fifth aspect, the present application further provides a computer-readable storage medium, which stores a computer program, where the computer program causes a processor to execute the method described in the first aspect and any possible design of the first aspect.

In a sixth aspect, an embodiment of the present application further provides a substrate controller, including: a memory and a processor;

the memory to store program instructions;

the processor is configured to invoke the program instructions stored in the memory to implement the method of the first aspect and any possible design of the first aspect.

In a seventh aspect, this application further provides a computer-readable storage medium, where a computer program is stored, and the computer program causes a processor to execute the method described in the second aspect and any possible design of the second aspect.

In an eighth aspect, an embodiment of the present application further provides a node controller, including: a memory and a processor;

the memory to store program instructions;

the processor is configured to invoke the program instructions stored in the memory to implement the method of the second aspect and any possible design of the second aspect.

According to the routing management method of the node controller, the target NC corresponding to the fault link and the NC to be configured are respectively configured with the routing information reaching the other side, so that the CPU connected with the target NC and the CPU connected with the NC to be configured can still perform mutual access; the target NC corresponding to the fault link is controlled to achieve that the jump NC corresponding to the NC to be configured is different from the jump NC corresponding to the target NC to be configured, so that the phenomenon that the CPU connected with the target NC and the CPU connected with the NC to be configured are in resource competition during mutual access to cause node deadlock is avoided, and the probability of system downtime is reduced.

Drawings

FIG. 1 is a first schematic diagram illustrating the connection of CPUs in the same group in the embodiment of the present application;

FIG. 2 is a second schematic diagram illustrating connection between CPUs in the same group in the embodiment of the present application;

fig. 3 is a first schematic diagram of a CPU interconnect architecture according to an embodiment of the present application;

fig. 4 is a schematic diagram of a CPU interconnect architecture according to an embodiment of the present application;

fig. 5 is a schematic diagram of a CPU interconnect architecture provided in the embodiment of the present application;

fig. 6 is a first signaling interaction diagram of a routing management method for a node controller according to an embodiment of the present application;

fig. 7 is a schematic diagram of a virtual rectangle formed by NCs provided in the embodiment of the present application;

FIG. 8 is a schematic diagram of a transformed virtual rectangle after a failure of the link consisting of A and B in FIG. 8;

FIG. 9 is a schematic diagram of a transformed virtual rectangle after failure of the link consisting of A and C in FIG. 8;

fig. 10 is a first schematic structural diagram of a routing management apparatus of a node controller according to an embodiment of the present application;

fig. 11 is a second schematic structural diagram of a routing management apparatus of a node controller according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a substrate controller according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a node controller according to an embodiment of the present application.

Detailed Description

First, an application scenario corresponding to NC in this embodiment will be described.

In a Non-Uniform Memory Access Architecture (NUMA) system, Central Processing Units (CPUs) may be interconnected via an interconnection bus to form a multi-CPU system. One common Interconnect bus is the Quick-Path Interconnect (QPI), and thus, a group of CPUs interconnected by QPI may be referred to as a QPI domain. A CPU group or a QPI domain generally has 4 CPUs, and may also have other numbers of CPUs, such as 8 CPUs, which is not limited in the embodiment of the present application; wherein, the CPUs in the same group are connected in pairs or in a ring shape.

In addition, the CPUs may be connected to each other via a Hyper-Transport (HT) bus.

Fig. 1 is a first connection diagram of CPUs in the same group in the embodiment of the present application, and fig. 2 is a second connection diagram of CPUs in the same group in the embodiment of the present application.

Referring to fig. 1, the CPUs 0, 1, 2 and 3 are connected two by two, that is, any two CPUs in a group are connected with each other.

Referring to fig. 2, the CPUs 0, 1, 2 and 3 are connected in a ring shape, that is, the CPUs 0, 1, 2 and 3 are connected in sequence, and the CPUs 0 and 3 are also connected.

The following describes an interconnection architecture between groups of CPUs according to an embodiment of the present application.

Fig. 3 is a first CPU interconnect architecture diagram provided in the embodiment of the present application, fig. 4 is a second CPU interconnect architecture diagram provided in the embodiment of the present application, and fig. 5 is a third CPU interconnect architecture diagram provided in the embodiment of the present application.

Referring to fig. 3, in the CPU interconnect architecture shown in fig. 3, NC0, NC1, NC2, and NC3 form an NC group, and each two of NC0, NC1, NC2, and NC3 are connected, which may also be referred to as full interconnect (full mesh) between NCs.

The NC0 is connected to the first CPU group 11, the NC1 is connected to the second CPU group 12, the NC2 is connected to the third CPU group 13, and the NC3 is connected to the fourth CPU group 14. The connection mode of the CPUs in the CPU group can be the connection mode in fig. 1 or fig. 2.

The interconnection architecture shown in fig. 3 can realize interconnection of 16 CPUs.

When CPU-a in the first CPU group 11 needs to access CPU-b in the second CPU group 12, the path for CPU-a to access CPU-b may be: CPU-a-NC 0-NC 1-CPU-b (Path 1), which realizes the cross-domain access of CPU, and the path is the shortest path for CPU-a to access CPU-b.

The path for CPU-a to access CPU-b can also be: CPU-a-NC 0-NC2-NC 1-CPU-b (Path 2) or CPU-a-NC 0-NC3-NC 1-CPU-b (Path 3); NC2 in Path 2 is called jump NC, NC3 in Path 3 is called jump NC; the jump NC means an NC that is not directly connected to any of two CPUs of different groups, for the two CPUs.

When the link formed by NC0 and NC1 is normal, CPU-a accessing CPU-b does not select these two paths, but selects only the shortest path described above.

The link in this embodiment refers to a link formed by two NCs connected to each other, and includes two NCs connected to each other and a connection cable between the two NCs.

Referring to fig. 4, in the CPU interconnect architecture shown in fig. 4, NC0, NC1, NC2, and NC3 form an NC group, and NC0, NC1, NC2, and NC3 are connected in pairs.

The NC0 is connected to the first CPU group 11 and the second CPU group 12, the NC1 is connected to the third CPU group 13 and the fourth CPU group 14, the NC2 is connected to the fifth CPU group 15 and the sixth CPU group 16, and the NC3 is connected to the seventh CPU group 17 and the eighth CPU group 18. The connection mode of the CPUs in the CPU group can be the connection mode in fig. 1 or fig. 2.

The interconnection architecture shown in fig. 4 can realize interconnection of 32 CPUs.

When CPU-a in the first CPU group 11 needs to access CPU-b in the second CPU group 12, the path for CPU-a to access CPU-b may be: CPU-a-NC 0-CPU-b, which realizes the cross-domain access of CPU.

When the CPU-a in the first CPU group 11 needs to access the CPU-c in the third CPU group 13, the path for the CPU-a to access the CPU-c is as follows: CPU-a-NC 0-NC 1-CPU-c, the path is the shortest path for CPU-a to access CPU-c.

The non-shortest path for CPU-a to access CPU-c is referred to the above description and will not be described herein.

Referring to fig. 5, in the CPU interconnect architecture shown in fig. 5, NC0, NC1, NC2, and NC3 form an NC group, which is referred to as a first NC group herein, and NC0, NC1, NC2, and NC3 are connected in pairs, that is, fully interconnected; NC4, NC5, NC6 and NC7 form an NC group, which is called a second NC group, and NC4, NC5, NC6 and NC7 are connected in pairs, namely, are fully interconnected.

The CPU interconnect architecture shown in fig. 5 is a dual NC full interconnect architecture, which can improve the reliability of the CPU interconnect architecture shown in fig. 4.

When the CPU-a in the first CPU group 11 needs to access the CPU-d in the fourth CPU group 14, the path for the CPU-a to access the CPU-d may be: CPU-a-NC 0-NC 1-CPU-d (Path 1), and may also be CPU-a-NC 4-NC 5-CPU-d (Path 2), with Path 1 and Path 2 both being the shortest paths. That is, if the link consisting of NC0-NC1 fails, the path for CPU-a to access CPU-d may be shortest path 2, and if the link consisting of NC4-NC5 fails, the path for CPU-a to access CPU-d may be shortest path 1.

The non-shortest path for CPU-a to access CPU-d is referred to the above description and will not be described herein.

From the above, the CPU interconnect architecture shown in fig. 5 improves the reliability of the system by adopting a redundancy design.

Based on the above description of the CPU interconnection architecture, the following describes a routing management method of the node controller provided in the present application.

Fig. 6 is a signaling interaction diagram of a routing management method of a node controller according to an embodiment of the present application, referring to fig. 6, the method of this embodiment may include:

step S101, the target NC sends state information to a substrate Controller (BMC for short), wherein the state information is used for indicating the working state of each link where the target NC is located;

step S102, the BMC judges whether each link where the target NC is located has a fault according to the state information sent by the target NC;

step S103, if a fault link which can not work normally exists in all links where the target NC is located, sending first routing configuration information to the target NC corresponding to the fault link, and sending second routing configuration information to the NC to be configured corresponding to the fault link;

step S104, the target NC obtains first routing information from the target NC to the NC to be configured according to the first routing configuration information;

s105, the NC to be configured obtains second routing information from the NC to be configured to the target NC according to the second routing configuration information; the hop NC indicated in the first routing information and the second routing information are different.

Specifically, the target NC in this embodiment is any NC in the CPU interconnect architecture.

The BMC is completely independent of a CPU, a BIOS, an operating system and a power-on/power-off state of a server, and is a completely independent running system. The BMC is generally integrated on a server mainboard, and provides an out-of-band management function for the server through the BMC and corresponding firmware. Each NC is connected to a BMC.

In this embodiment, each link where the target NC is located refers to a link including the target NC, for example, the CPU interconnect architecture shown in fig. 5, and each link where the NC0 is located includes: a link formed by NC0 and NC1, a link formed by NC0 and NC2, and a link formed by NC0 and NC 3; each link in which NC1 resides includes: a link formed by NC1 and NC0, a link formed by NC1 and NC2, and a link formed by NC1 and NC 4; each link in which NC2 resides includes: a link formed by NC2 and NC0, a link formed by NC2 and NC1, and a link formed by NC2 and NC 3; each link in which NC3 resides includes: a link formed by NC3 and NC0, a link formed by NC3 and NC1, and a link formed by NC3 and NC 2.

For a link consisting of any two NCs, a link failure may be a failure of a port through which one of the two NCs is connected to the other NC, or a failure of a cable connecting the two NCs.

Such as: for a link formed by NC0 and NC1, a cable connecting NC0 and NC1 has one end connected to port 0 of NC0 and the other end connected to port 0 of NC1, and if the link formed by NC0 and NC1 fails, it is possible that port 0 of NC0 fails, it is possible that port 0 of NC1 fails, and it is also possible that a cable connecting NC0 and NC1 fails.

Each NC sends a state detection message to the NC connected with the NC, if response messages of other NCs are received within a preset time length, a link formed by the NC and the NC sending the response message is normal, otherwise, the link formed by the NC and the NC not sending the response message is in failure.

Such as: the NC0 in fig. 5 periodically sends state detection messages to the NC1, the NC2, and the NC3, respectively, and if a response message of the NC1 is received within a preset time duration, it indicates that a link formed by the NC0 and the NC1 is normal; if the response message of the NC2 is not received within the preset time length, the link fault formed by the NC0 and the NC2 is indicated; if the response message of the NC3 is received within the preset time length, the link formed by the NC0 and the NC3 is normal.

The status register of each NC stores therein instruction information of the status between the NC and each other NC. For any NC in the NC group, for each associated NC connected with the NC, if the identifier used for indicating the working state of the link formed by the NC and the associated NC in the state information of the NC is a first identifier, the link between the NC and the associated NC is determined to be capable of working normally, and if the identifier used for indicating the working state of the link formed by the NC and the associated NC is a second identifier, the link between the NC and the associated NC is determined to be in failure.

For example, for NC0 in fig. 5, the corresponding target NCs are NC1, NC2, and NC 3.

Three bits may be used to indicate the working state of the link consisting of NC0 and NC1, the working state of the link consisting of NC0 and NC2, and the working state of the link consisting of NC0 and NC3, respectively, and the state information may be 000 if all three links are working normally, 100 if a failure occurs in the link consisting of NC1, 001 if a failure occurs in the link consisting of NC3, and 111 if each link where NC0 is located has a failure. At this time, the first flag is 0 and the second flag is 1.

As can be understood by those skilled in the art, if a first CPU connected to a target NC needs to access a second CPU connected to an NC to be configured, and there is no shortest path for forwarding a message, after the target NC receives a message sent by the first CPU, the first NC sends the message to the second CPU according to a path indicated by the first routing information.

And if the second CPU connected with the NC to be configured needs to access the first CPU connected with the target NC and the shortest path for forwarding the message does not exist, after receiving the message sent by the second CPU, the NC to be configured sends the message to the first CPU according to the path indicated by the second routing information.

The following describes steps S101 to S105 with reference to several specific examples.

The first example corresponds to one link in fig. 5 failing and the remaining links are normal, with the target NC being NC 0.

The NC0 may send the status information to the BMC upon receiving a command from the BMC to read the status information.

The BMC receives the state information sent by the NC0, and judges whether each link where the NC0 is located has a fault according to the state information sent by the NC 0.

Specifically, for example, the status information sent by the NC0 received by the BMC is 010, and under the architecture shown in fig. 5, a first bit of three bits is used to indicate the working status of the link 1 composed of the NC0 and the NC1, a second bit is used to indicate the working status of the link 2 composed of the NC0 and the NC2, and a third bit is used to indicate the working status of the link 3 composed of the NC0 and the NC 3. From the status information 010, the first bit is 0, which indicates that the status of the link 1 composed of NC0 and NC1 is a normal operating status, the second bit is 1, which indicates that the status of the link 2 composed of NC0 and NC2 is a failure, and the third bit is 0, which indicates that the status of the link 3 composed of NC0 and NC3 is a normal operating status.

In summary, when a link 2 formed by NC0 and NC2 fails, that is, a link 2 where NC0 is located fails, the second NC to be configured (i.e., the third NC) is NC 2.

The BMC sends the first configuration command to the first NC-NC 0 to be configured corresponding to the failed link 2, and sends the second configuration command to the second NC-NC 2 to be configured corresponding to the failed link 2.

After receiving the first configuration command, the NC0 obtains first routing information from the NC0 to the NC2 according to the first configuration command; after receiving the second configuration command, the NC2 obtains second routing information from the NC2 to the NC0 according to the second configuration command;

wherein, the routing information may include: a routing enabling identifier, an identifier of a jump NC and an identifier of a destination NC; the routing information is stored in a routing register of the corresponding NC.

According to the architecture shown in fig. 5, when a link formed by NC0 and NC2 fails, NC0 can reach NC2 through NC1 or NC3, so that CPUs in a CPU group connected with NC0 can access CPUs in a CPU group connected with NC2 through paths NC0-NC1-NC2 or NC0-NC3-NC 2. At this time, NC1 and NC3 are called jump NCs.

Similarly, NC2 may reach NC0 through NC1 or NC3, so that CPUs within a group of CPUs connected to NC2 may access CPUs within a group of CPUs connected to NC0 through paths NC2-NC1-NC0 or NC2-NC3-NC 0.

If a CPU-a in a CPU group connected with NC0 accesses a CPU-b in a CPU group connected with NC2 through a path NC0-NC1-NC2, and a CPU-b in a CPU group connected with NC2 accesses a CPU-a in a CPU group connected with NC0 through a path NC2-NC1-NC0, if the occupied cache resources of NC1 are not released when the CPU-a sends a message to the CPU-b (namely, the CPU-a accesses the CPU-b), when the CPU-b replies the message to the CPU-a (namely, the CPU-b accesses the CPU-a), the NC1 does not have enough cache resources to use, so that resource competition occurs, node deadlock is easily caused, and the serious risk of system downtime is caused.

Therefore, in order to solve the above technical problem, the skip NC included in the first routing information and the second routing information in the present application is different. If the hop NC indicated by the first routing information is NC1, the hop NC indicated by the second routing information is NC3, and if the hop NC indicated by the second routing information is NC3, the hop NC indicated by the second routing information is NC 1.

Since the first routing information is routing information from NC0 to NC2, the destination NC indicated in the first routing information is NC 2; since the second routing information indicates the routing information from NC2 to NC0, the destination NC indicated in the second routing information is NC 0.

To sum up, in this example, the path indicated by the first routing information corresponding to NC0 is: when the NC0 is the NC1 is the NC2, the path indicated by the second routing information corresponding to the NC2 is as follows: the NC2-NC3-NC0, the path indicated by the first routing information corresponding to the NC0 is as follows: and when the route is NC0-NC3-NC2, the route indicated by the second routing information corresponding to the NC0 is NC0-NC1-NC 2.

For the route enabling identifier in the route information, after the route information is obtained, the route enabling identifier of the route information is a third identifier, that is, the route information is valid, where the third identifier may be 1.

Further, since the CPU interconnect architecture shown in fig. 5 includes two NC groups, that is, there is a redundant design, as described above, the CPUs in the CPU group connected to NC0 can also access the CPUs in the CPU group connected to NC2 through paths NC4-NC6, that is, cross-domain access of the CPUs is achieved through paths NC4-NC6, and the paths are shorter, that is, the shortest paths; CPUs in the CPU group connected with the NC2 can also access CPUs in the CPU group connected with the NC0 through a path NC6-NC4, namely, the cross-domain access of the CPUs is realized through a path NC6-NC4, and the path is shorter, namely, the shortest path.

Then, when the link 2 composed of the NC0 and the NC2 fails, if the link between the NC4 and the NC6 fails, the CPU-a in the CPU group connected to the NC0 accesses the CPU-b in the CPU group connected to the NC2 through the path NC4-NC6 according to the shortest path principle. That is, when there is the shortest path, although the first routing information that the NC0 reaches the NC2 is configured in the routing register of the NC0, in the actual access process, the CPU in the CPU group connected to the NC0 (also, the CPU group connected to the NC 4) does not access the CPU in the CPU group connected to the NC2 (also, the CPU group connected to the NC 6) by the route that the NC0 indicated by the first routing information reaches the NC2, but accesses the CPU in the CPU group connected to the NC2 by the shortest path NC4-NC 6; similarly, when there is the shortest path, although the second routing information from the NC2 to the NC0 is arranged in the routing register of the NC2, the CPU in the CPU group connected to the NC2 (also, the CPU group connected to the NC 6) does not access the CPU in the CPU group connected to the NC0 (also, the CPU group connected to the NC 4) by the path from the NC2 indicated by the second routing information to the NC0, but accesses the CPU in the CPU group connected to the NC2 by the shortest path NC6 to NC 4.

That is, if a first CPU in the first CPU group 11 connected to the NC0 needs to access a second CPU in the fifth CPU group 15 connected to the NC2 and there is a shortest path for packet forwarding, the first CPU sends a packet to the NC4 in the second NC group connected to the first CPU group 11, and reaches the second CPU in the fifth CPU group 15 through the NC6 in the second NC group, that is, the packet is forwarded to the destination CPU through the shortest path.

If the second CPU in the fifth CPU group 15 connected to the NC2 needs to access the first CPU in the first CPU group 11 connected to the NC0 and there is a shortest path for packet forwarding, the second CPU sends the packet to the NC6 in the second NC group connected to the fifth CPU group 15, and reaches the first CPU in the first CPU group 11 through the NC4 in the second NC group, that is, the packet is forwarded to the destination CPU through the shortest path.

Then, when the link 2 composed of the NC0 and the NC2 fails, if the link between the NC4 and the NC6 also fails, that is, there is no shortest path for forwarding packets, the CPU in the CPU group connected to the NC0 accesses the CPU in the CPU group connected to the NC2 through the NC0 indicated by the first routing information and the NC2 path; similarly, the CPUs in the CPU group connected to the NC2 access the CPUs in the CPU group connected to the NC0 through the path indicated by the second routing information, which reaches the NC0, from the NC 2.

That is to say, when the hop NC indicated by the first routing information is NC1 and the hop NC indicated by the second routing information is NC3, if the first CPU in the first CPU group 11 connected to NC0 needs to access the second CPU in the fifth CPU group 15 connected to NC2 and there is no shortest path for forwarding a packet, the first CPU sends the packet to NC0, and then reaches the target NC-NC 2 via the hop NC1 indicated by the first routing information, and forwards the packet to the second CPU via NC2, that is, after the packet reaches NC0, the packet reaches the target CPU according to the path indicated by the first routing information configured in the routing register of NC 0.

If the second CPU in the fifth CPU group 15 connected to the NC2 needs to access the first CPU in the first CPU group 11 connected to the NC0 and there is no shortest path for forwarding a packet, the second CPU sends the packet to the NC2, and then reaches the target NC-NC 0 through the hop NC-NC 3 indicated by the second routing information, and forwards the packet to the second CPU through the NC0, that is, after the packet reaches the NC2, the packet reaches the target CPU according to the path indicated by the second routing information configured in the routing register of the NC 2.

Similarly, when the hop NC indicated by the first routing information is NC3, and the hop NC indicated by the second routing information is NC1, if the first CPU in the first CPU group 11 connected to NC0 needs to access the second CPU in the fifth CPU group 15 connected to NC2, and there is no shortest path for packet forwarding, the first CPU sends the packet to NC0, and then reaches the target NC-NC 2 via the hop NC-NC 3 indicated by the first routing information, and forwards the packet to the second CPU via NC2, that is, after reaching NC0, the packet reaches the target CPU according to the path indicated by the first routing information configured in the routing register of NC 0.

If the second CPU in the fifth CPU group 15 connected to the NC2 needs to access the first CPU in the first CPU group 11 connected to the NC0 and there is no shortest path for forwarding a packet, the second CPU sends the packet to the NC2, and then reaches the target NC-NC 0 through the hop NC-NC 1 indicated by the second routing information, and forwards the packet to the first CPU through the NC0, that is, after the packet reaches the NC2, the packet reaches the target CPU according to the path indicated by the second routing information configured in the routing register of the NC 2.

The above explanation is a specific implementation of step S101 to step S107 corresponding to "when the target NC is NC0 and the link between NC0 and NC2 fails in the CPU interconnect architecture shown in fig. 5" as an example.

The second example corresponds to a failure of one of the links in fig. 4, with the target NC being NC 3.

The NC3 may send the status information to the BMC upon receiving a command from the BMC to read the status information.

The BMC receives the state information sent by the NC3, and judges whether each link where the NC3 is located has a fault according to the state information sent by the NC 3.

Specifically, for example, the status information sent by the NC3 received by the BMC is 100, and in the architecture shown in fig. 4, a first bit of three bits is used to indicate an operating status of a link 1 composed of NC3 and NC0, a second bit is used to indicate an operating status of a link 2 composed of NC3 and NC1, and a third bit is used to indicate an operating status of a link 3 composed of NC3 and NC 2. As can be seen from the state information of 100, the first bit is 1, which indicates that the state of the link 1 composed of NC3 and NC0 is a failure, the second bit is 1, which indicates that the state of the link 2 composed of NC3 and NC1 is a normal operation, and the third bit is 0, which indicates that the state of the link 3 composed of NC3 and NC2 is a normal operation.

As can be seen, the link 1 formed by the NC3 and the NC0 fails, that is, the link 1 in which the NC3 is located fails.

The BMC sends a first configuration command to the first NC-NC 3 to be configured corresponding to the failed link 1, and sends a second configuration command to the second NC-NC 0 to be configured corresponding to the failed link 1.

After receiving the first configuration command, the NC3 obtains first routing information from the NC3 to the NC0 according to the first configuration command; after receiving the second configuration command, the NC0 obtains second routing information from the NC0 to the NC3 according to the second configuration command;

According to the architecture shown in fig. 4, when a link formed by NC3 and NC0 fails, NC3 can reach NC0 through NC1 or NC2, so that CPUs in a CPU group connected with NC3 can access CPUs in a CPU group connected with NC0 through paths NC3-NC1-NC0 or NC3-NC2-NC 0. At this time, NC1 and NC2 are called jump NCs.

Similarly, NC0 may reach NC3 through NC1 or NC2, so that CPUs within a group of CPUs connected to NC0 may access CPUs within a group of CPUs connected to NC3 through paths NC0-NC1-NC3 or NC0-NC2-NC 3.

In order to avoid the occurrence of the phenomenon of deadlock of nodes due to resource contention in the previous example, the first routing information and the second routing information in the present example include different jump NCs. If the hop NC indicated by the first routing information is NC1, the hop NC indicated by the second routing information is NC2, and if the hop NC indicated by the second routing information is NC2, the hop NC indicated by the second routing information is NC 1.

Since the first routing information is routing information from NC3 to NC0, the destination NC indicated in the first routing information is NC 0; since the second routing information indicates the routing information from NC0 to NC3, the destination NC indicated in the second routing information is NC 3.

To sum up, in this example, the path indicated by the first routing information corresponding to NC3 is: when the NC3 is the NC1 is the NC0, the path indicated by the second routing information corresponding to the NC0 is as follows: the NC0-NC2-NC3, the path indicated by the first routing information corresponding to the NC3 is as follows: and when the route is NC3-NC2-NC0, the route indicated by the second routing information corresponding to the NC0 is NC3-NC1-NC 0.

Further, since the CPU interconnect architecture shown in fig. 4 includes one NC group, there is no redundancy design, and when a link 1 composed of NC3 and NC0 fails, the shortest path between the CPU in the CPU group connected to NC3 and the CPU in the CPU group connected to NC0 no longer exists, and the shortest path between the CPU in the CPU group connected to NC0 and the CPU in the CPU group connected to NC3 does not exist.

Then, when the link 1 formed by the NC0 and the NC3 fails, that is, when there is no shortest path for packet forwarding, the CPU in the CPU group connected to the NC0 accesses the CPU in the CPU group connected to the NC3 through the path indicated by the second routing information, where the NC0 reaches the NC 3; similarly, the CPUs in the CPU group connected to the NC3 access the CPUs in the CPU group connected to the NC0 through the path indicated by the second routing information, which reaches the NC0, from the NC 3.

That is, when the hop NC indicated by the first routing information is NC1 and the hop NC indicated by the second routing information is NC2, if the first CPU in the seventh CPU group 17 connected to NC3 needs to access the second CPU in the first CPU group 11 connected to NC0, the first CPU sends the packet to NC3, and then reaches the target NC-NC 0 via the hop NC-NC 1 indicated by the first routing information, and forwards the packet to the second CPU via NC0, that is, after the packet reaches NC3, the packet reaches the target CPU according to the path indicated by the first routing information configured in the routing register of NC 3.

If the second CPU in the first CPU group 11 connected to the NC0 needs to access the first CPU in the seventh CPU group 17 connected to the NC3, the second CPU sends the packet to the NC0, then the packet will reach the destination NC-NC 3 through the jump NC-NC 2 indicated by the second routing information, and then the packet is forwarded to the first CPU through the NC3, that is, after reaching the NC0, the packet will reach the destination CPU according to the path indicated by the second routing information configured in the routing register of the NC 0.

Similarly, when the hop NC indicated by the first routing information is NC2 and the hop NC indicated by the second routing information is NC1, if the first CPU in the seventh CPU group 17 connected to NC3 needs to access the second CPU in the first CPU group 11 connected to NC0, the first CPU sends the packet to NC3, and then reaches the target NC-NC 0 via the hop NC-NC 2 indicated by the first routing information, and forwards the packet to the second CPU via NC0, that is, after the packet reaches NC3, the packet reaches the target CPU according to the path indicated by the first routing information configured in the routing register of NC 3.

If the second CPU in the first CPU group 11 connected to the NC0 needs to access the first CPU in the seventh CPU group 17 connected to the NC3, the second CPU sends the packet to the NC0, then the packet will reach the destination NC-NC 3 through the jump NC-NC 1 indicated by the second routing information, and then the packet is forwarded to the first CPU through the NC3, that is, after reaching the NC0, the packet will reach the destination CPU according to the path indicated by the second routing information configured in the routing register of the NC 0.

The above explanation is a specific implementation of step S101 to step S107 corresponding to "when the target NC is NC3 and the link between NC3 and NC0 fails in the CPU interconnect architecture shown in fig. 4" as an example.

As can be understood by those skilled in the art, since each NC corresponds to one BMC, the interaction between each BMC and its connected NC is performed in steps S101 to S102, and steps S103 to S107 are the interaction process existing between the NC corresponding to the failed link and the corresponding BMC, that is, if only one link fails, the interaction process in steps S101 to S107 is performed between only one NC and the corresponding BMC.

In the above two examples, the following describes a routing management method of a node controller when two links fail in a CPU interconnection architecture.

If the link where the first target NC is located fails, the link where the second target NC is located also fails, the link where the first target NC is located is different from the link where the second target NC is located, and the first target NC and the second target NC are not the same NC, the following interaction process exists:

for the first target NC and the first BMC:

a1, the first target NC sending first state information to the first substrate controller, the first state information being used for indicating the working state of each link where the first target NC is located;

b1, the first BMC judges whether each link where the first target NC is located has a fault according to the first state information;

c1, if a first fault link which can not work normally exists in each link where the first target NC is located, for the first fault link, sending first target routing configuration information to the first target NC corresponding to the first fault link, and sending second target routing configuration information to the NC to be configured corresponding to the first fault link; the NC to be configured corresponding to the first fault link is called a third target NC;

d1, the first target NC obtaining first target routing information from the first target NC to a second NC to be configured corresponding to the first fault link according to the first target routing configuration information;

e1, the third target NC obtains second target routing information from the third target NC to the first target NC according to the second target routing configuration information; the hop NC indicated in the first target routing information and the second target routing information are different.

As can be understood by those skilled in the art, if a first CPU connected to a first target NC needs to access a second CPU connected to a third target NC, and there is no shortest path for forwarding a message, after the first target NC receives a message sent by the first CPU, the first NC sends the message to the second CPU according to first target routing information; and if the second CPU connected with the third target NC needs to access the first CPU connected with the first target NC and the shortest path for message forwarding does not exist, the third target NC sends the message to the first CPU according to the second target routing information after receiving the message sent by the second CPU.

For a second target NC and a second BMC:

a2, the second target NC sending second state information to the second substrate controller, the second state information being used for indicating the working state of each link where the second target NC is located;

b2, the second BMC judges whether each link where the second target NC is located has a fault according to the second state information;

c2, if a second fault link which can not work normally exists in each link where the second target NC is located, for the second fault link, sending third target routing configuration information to the second target NC corresponding to the second fault link, and sending fourth target routing configuration information to the NC to be configured corresponding to the second fault link; the NC to be configured corresponding to the second fault link is called a fourth target NC;

d2, the second target NC obtains third target routing information from the second target NC to the fourth target NC according to the third target routing configuration information;

e2, the fourth target NC obtains fourth target routing information from the fourth target NC to the second target NC according to the third target routing configuration information; the indicated jump NC in the third target routing information and the fourth target routing information is different;

as can be understood by those skilled in the art, if a third CPU connected to a second target NC needs to access a fourth CPU connected to a fourth target NC, and there is no shortest path for forwarding a message, after the second target NC receives a message sent by the third CPU, the second target NC sends the message to the fourth CPU according to third target routing information; and if the fourth CPU connected with the fourth target NC needs to access the third CPU connected with the second target NC and the shortest path for message forwarding does not exist, the fourth target NC sends the message to the third CPU according to the fourth target routing information after receiving the message sent by the fourth CPU.

Specifically, in this embodiment, the first target NC is any one of the CPUs interconnection architecture, the second target NC is any one of the CPUs interconnection architecture, and the first target NC and the second target NC are not the same NC.

In this embodiment, each link in which the first target NC is located refers to a link including the first target NC, for example, the links in which the NC0 is located include: a link formed by NC0 and NC1, a link formed by NC0 and NC2, and a link formed by NC0 and NC 3; each link in which NC1 resides includes: a link formed by NC1 and NC0, a link formed by NC1 and NC2, and a link formed by NC1 and NC 4; each link in which NC2 resides includes: a link formed by NC2 and NC0, a link formed by NC2 and NC1, and a link formed by NC2 and NC 3; each link in which NC3 resides includes: a link formed by NC3 and NC0, a link formed by NC3 and NC1, and a link formed by NC3 and NC 2. Similarly, each link in which the second target NC is located in this embodiment refers to a link including the second target NC.

The above two interaction processes are described below with reference to specific examples.

This example corresponds to fig. 5 where two links belonging to the same NC group fail, the first target NC being NC0 and the second target NC being NC 3.

The NC0 may send its first status information to the BMC after receiving a command from the BMC to read the status information.

Specifically, for example, the status information sent by the NC0 received by the BMC is 100, and in the architecture shown in fig. 5, a first bit of three bits is used to indicate an operating status of a link 1 composed of NC0 and NC1, a second bit is used to indicate an operating status of a link 2 composed of NC0 and NC2, and a third bit is used to indicate an operating status of a link 3 composed of NC0 and NC 3. As can be seen from the state information of 100, the first bit is 1, which indicates that the state of the link 1 composed of NC0 and NC1 is a failure, the second bit is 0, which indicates that the state of the link 2 composed of NC0 and NC2 is a normal operating state, and the third bit is 0, which indicates that the state of the link 3 composed of NC0 and NC3 is a normal operating state.

As can be known from the above, when a link 1 formed by NC0 and NC1 fails, that is, a link 1 where NC0 is located fails, the link 1 formed by NC0 and NC1 is referred to as a first failed link, and at this time, an NC (that is, a third target NC) to be configured corresponding to the first failed link is NC 1.

Similarly, the NC3 may send its own second status information to the BMC after receiving a command from the BMC to read the status information.

Specifically, for example, the status information sent by the NC3 received by the BMC is 001, and in the architecture shown in fig. 5, a first bit of three bits is used to indicate an operating status of a link 1 composed of NC3 and NC0, a second bit is used to indicate an operating status of a link 2 composed of NC3 and NC1, and a third bit is used to indicate an operating status of a link 3 composed of NC3 and NC 2. As can be seen from the state information of 001, the first bit is 0, which indicates that the state of the link 1 composed of NC3 and NC0 is a normal operating state, the second bit is 0, which indicates that the state of the link 2 composed of NC3 and NC1 is a normal operating state, and the third bit is 1, which indicates that the state of the link 3 composed of NC3 and NC2 is a normal operating state.

As can be seen from the above, when a link 3 formed by NC3 and NC2 fails, that is, a link 3 where NC3 is located fails, the link 3 formed by NC3 and NC2 is referred to as a second failed link, and at this time, an NC to be configured (that is, a fourth target NC) corresponding to the second failed link is NC 2.

The BMC sends the first target routing configuration information to a first NC-NC 0 to be configured corresponding to the first failed link, and sends the second target routing configuration information to a second NC (third NC) -NC1 to be configured corresponding to the first failed link.

After receiving the first target routing configuration information, the NC0 obtains first target routing information from the NC0 to the NC1 according to the first target routing configuration information; after receiving the second target routing configuration information, the NC1 obtains second routing target routing information from the NC1 to the NC0 according to the second target routing configuration information;

The hop NC included in the first target routing information and the second target routing information are not the same (see the explanation of the above implementation for a specific reason). If the hop NC indicated by the first target routing information is NC2, the hop NC indicated by the second target routing information is NC3, and if the hop NC indicated by the second target routing information is NC3, the hop NC indicated by the second target routing information is NC 2. Since the first target routing information is the routing information of NC0 to NC1, the destination NC indicated in the first target routing information is NC 1; since the second target routing information indicates routing information of NC1 to NC0, the destination NC indicated in the second target routing information is NC 0.

That is, when a link formed by NC0 and NC1 fails, NC0 can reach NC1 through NC3 or NC2, so that CPUs in a CPU group connected with NC0 can access CPUs in a CPU group connected with NC1 through a path NC0-NC2-NC1 or NC0-NC3-NC 1; NC1 may reach NC0 through NC3 or NC2, so that CPUs within a group of CPUs connected to NC1 may access CPUs within a group of CPUs connected to NC0 through paths NC1-NC2-NC0 or NC1-NC3-NC 0. At this time, NC2 and NC3 are called jump NCs.

Similarly, the BMC sends the third target routing configuration information to the first NC-NC 3 to be configured corresponding to the second failed link, and sends the fourth target routing configuration information to the second NC (fourth NC) -NC2 to be configured corresponding to the second failed link.

After receiving the third target routing configuration information, the NC3 obtains third target routing information from the NC3 to the NC2 according to the third target routing configuration information; and after receiving the fourth target routing configuration information, the NC2 obtains fourth target routing information from the NC2 to the NC3 according to the fourth target routing configuration information.

The hop NC included in the third target routing information and the fourth target routing information are not the same (for the reasons explained in the above embodiment). If the hop NC indicated by the third target routing information is NC0, the hop NC indicated by the fourth target routing information is NC1, and if the hop NC indicated by the fourth target routing information is NC1, the hop NC indicated by the fourth target routing information is NC 0. Since the third target routing information is the routing information of NC3 to NC2, the destination NC indicated in the first target routing information is NC 2; since the fourth target routing information indicates routing information of NC2 to NC3, the destination NC indicated in the fourth target routing information is NC 3.

That is, when a link formed by NC3 and NC2 fails, NC3 can reach NC2 through NC0 or NC1, so that CPUs in a CPU group connected with NC3 can access CPUs in a CPU group connected with NC2 through a path NC3-NC0-NC2 or NC3-NC1-NC 2; NC2 may reach NC3 through NC0 or NC1, so that CPUs within a group of CPUs connected to NC2 may access CPUs within a group of CPUs connected to NC3 through paths NC2-NC0-NC3 or NC2-NC1-NC 3. At this time, NC0 and NC1 are called jump NCs.

For the first failed link consisting of NC0 and NC 1:

since the CPU interconnect architecture in fig. 5 includes two NC groups, the CPU group connected to NC0 is also connected to NC4, and the CPU group connected to NC1 is also connected to NC5, the CPUs in the CPU group thus connected to NC0 can also access the CPUs in the CPU group connected to NC1 through paths NC4 to NC 5. It can be seen that the cross-domain access of the CPU is realized by the path NC4-NC5, and the path is short, that is, the shortest path. CPUs within the CPU group connected to NC1 may also access CPUs within the CPU group connected to NC0 via paths NC5-NC 4. It can be seen that the cross-domain access of the CPU is realized by the path NC5-NC4, and the path is short, that is, the shortest path.

Then, when the link between NC0 and NC1 fails, if the link between NC4 and NC5 fails, CPU-a in the CPU group connected to NC0 accesses CPU-b in the CPU group connected to NC1 through path NC4-NC5, according to the shortest path principle. That is, when there is the shortest path, although the first destination routing information that the NC0 reaches the NC1 is configured in the routing register of the NC0, in the actual access process, the CPU in the CPU group connected to the NC0 (also, the CPU group connected to the NC 4) does not access the CPU in the CPU group connected to the NC1 (also, the CPU group connected to the NC 5) by the route that the NC0 indicated by the first destination routing information reaches the NC1, but accesses the CPU in the CPU group connected to the NC1 by the shortest path NC4-NC 5; similarly, when there is the shortest path, although the second destination routing information from the NC1 to the NC0 is arranged in the routing register of the NC1, the CPU in the CPU group connected to the NC1 (also, the CPU group connected to the NC 5) does not access the CPU in the CPU group connected to the NC0 (also, the CPU group connected to the NC 4) through the path from the NC1 indicated by the second destination routing information to the NC0, but accesses the CPU in the CPU group connected to the NC0 through the shortest path NC5 to the NC 4.

That is, if a first CPU in the first CPU group 11 connected to the NC0 needs to access a second CPU in the fourth CPU group 14 connected to the NC1 and there is a shortest path for packet forwarding, the first CPU sends a packet to the NC4 in the second destination NC group connected to the first CPU group 11, and reaches a second CPU in the fourth CPU group 14 through the NC5 in the second destination NC group, that is, the packet is forwarded to the shortest path destination CPU.

If the second CPU in the fourth CPU group 14 connected to the NC1 needs to access the first CPU in the first CPU group 11 connected to the NC0 and there is a shortest path for packet forwarding, the second CPU sends the packet to the NC5 in the second destination NC group connected to the fourth CPU group 14, and reaches the first CPU in the first CPU group 11 through the NC4 in the second destination NC group, that is, the packet is forwarded to the destination CPU through the shortest path.

Then, when the link 2 composed of the NC0 and the NC1 fails, if the link between the NC4 and the NC5 also fails, that is, there is no shortest path for packet forwarding, the CPU in the CPU group connected to the NC0 accesses the CPU in the CPU group connected to the NC1 through the NC0 indicated by the first destination routing information and the NC1 path; similarly, the CPUs in the CPU group connected to the NC1 access the CPUs in the CPU group connected to the NC0 through the NC 1-to-NC 0 path indicated by the second target routing information.

That is, when the hop NC indicated by the first target routing information is NC2 and the hop NC indicated by the second target routing information is NC3, if the first CPU in the first CPU group 11 connected to NC0 needs to access the second CPU in the fourth CPU group 14 connected to NC1 and there is no shortest path for forwarding a packet, the first CPU sends the packet to NC0, and then reaches the target NC-NC 1 through the hop NC-NC 3578 indicated by the first target routing information, and forwards the packet to the second CPU through NC 45, that is, after the packet reaches NC0, the packet reaches the target CPU according to the path indicated by the first target routing information configured in the routing register of NC 0.

If the second CPU in the fourth CPU group 14 connected to the NC1 needs to access the first CPU in the first CPU group 11 connected to the NC0 and there is no shortest path for forwarding a packet, the second CPU sends the packet to the NC1, and then reaches the target NC-NC 0 through the hop NC-NC 3 indicated by the second target routing information, and forwards the packet to the second CPU through the NC0, that is, after the packet reaches the NC1, the packet reaches the target CPU according to the path indicated by the second target routing information configured in the routing register of the NC 1.

Similarly, when the hop NC indicated by the first target routing information is NC3 and the hop NC indicated by the second target routing information is NC2, if the first CPU in the first CPU group 11 connected to NC0 needs to access the second CPU in the fourth CPU group 14 connected to NC1 and there is no shortest path for forwarding a packet, the first CPU sends the packet to NC0, and then reaches the target NC-NC 1 through the hop NC-NC 3 indicated by the first target routing information, and forwards the packet to the second CPU through NC1, that is, after the packet reaches NC0, the packet reaches the target CPU according to the path indicated by the first target routing information configured in the routing register of NC 0.

If the second CPU in the fourth CPU group 14 connected to the NC1 needs to access the first CPU in the first CPU group 11 connected to the NC0 and there is no shortest path for forwarding a packet, the second CPU sends the packet to the NC1, and then reaches the target NC-NC 0 through the hop NC-NC 2 indicated by the second target routing information, and forwards the packet to the second CPU through the NC0, that is, after the packet reaches the NC1, the packet reaches the target CPU according to the path indicated by the second target routing information configured in the routing register of the NC 1.

For the second failed link consisting of NC3 and NC 2:

since the CPU interconnect architecture in fig. 5 includes two NC groups, the CPU group connected to NC3 is also connected to NC7, and the CPU group connected to NC2 is also connected to NC6, the CPU in the CPU group connected to NC3 can also access the CPU in the CPU group connected to NC2 through paths NC7 to NC6, and it can be known that the path is shorter, that is, the shortest path, through paths NC7 to NC6, the cross-domain access of the above-mentioned CPU is realized. The CPUs in the CPU group connected to NC2 can also access the CPUs in the CPU group connected to NC3 through paths NC6-NC7, and it is known that the path is shorter, that is, the shortest path, through paths NC6-NC7, the above-mentioned cross-domain access of the CPUs is realized.

Then, when the link between NC3 and NC2 fails, if the link between NC7 and NC6 fails, the CPU in the CPU group connected to NC3 accesses the CPU in the CPU group connected to NC2 through paths NC7 to NC6 in accordance with the shortest path principle. That is, when there is the shortest path, although the first destination routing information that the NC3 reaches the NC2 is configured in the routing register of the NC3, in the actual access process, the CPU in the CPU group connected to the NC3 (also, the CPU group connected to the NC 7) does not access the CPU in the CPU group connected to the NC2 (also, the CPU group connected to the NC 6) by the route that the NC3 indicated by the first destination routing information reaches the NC2, but accesses the CPU in the CPU group connected to the NC2 by the shortest path NC7-NC 6; similarly, when there is the shortest path, although the second destination routing information from the NC2 to the NC3 is arranged in the routing register of the NC2, the CPU in the CPU group connected to the NC2 (also, the CPU group connected to the NC 6) does not access the CPU in the CPU group connected to the NC3 (also, the CPU group connected to the NC 7) through the path from the NC2 indicated by the second destination routing information to the NC3, but accesses the CPU in the CPU group connected to the NC3 through the shortest path NC6 to the NC 7.

That is, if the first CPU in the eighth CPU group 18 connected to the NC3 needs to access the second CPU in the sixth CPU group 16 connected to the NC2 and there is a shortest path for packet forwarding, the first CPU sends the packet to the NC7 in the second destination NC group connected to the eighth CPU group 18, and reaches the second CPU in the sixth CPU group 16 through the NC6 in the second destination NC group, that is, the packet is forwarded to the shortest path destination CPU.

If the second CPU in the sixth CPU group 16 connected to the NC2 needs to access the first CPU in the eighth CPU group 18 connected to the NC3 and there is a shortest path for packet forwarding, the second CPU sends the packet to the NC6 in the second destination NC group connected to the sixth CPU group 16, and reaches the first CPU in the first CPU group 11 through the NC7 in the second destination NC group, that is, the packet is forwarded to the destination CPU through the shortest path.

Then, when the link 2 composed of the NC3 and the NC2 fails, if the link between the NC6 and the NC7 also fails, that is, there is no shortest path for packet forwarding, the CPU in the CPU group connected to the NC3 accesses the CPU in the CPU group connected to the NC2 through the NC3 indicated by the first destination routing information and the NC2 path; similarly, the CPUs in the CPU group connected to the NC2 access the CPUs in the CPU group connected to the NC3 through the NC 3-to-NC 2 path indicated by the second target routing information.

That is, when the hop NC indicated by the third target routing information is NC0 and the hop NC indicated by the fourth target routing information is NC1, if the first CPU in the eighth CPU group 18 connected to NC3 needs to access the second CPU in the sixth CPU group 16 connected to NC2 and there is no shortest path for forwarding a packet, the first CPU sends the packet to NC3, and then reaches the target NC-NC 2 through the hop NC-NC 3578 indicated by the third target routing information, and forwards the packet to the second CPU through NC 45, that is, after the packet reaches NC3, the packet reaches the target CPU according to the path indicated by the third target routing information configured in the routing register of NC 3.

If the second CPU in the sixth CPU group 16 connected to the NC2 needs to access the first CPU in the eighth CPU group 18 connected to the NC3 and there is no shortest path for forwarding a packet, the second CPU sends the packet to the NC2, and then reaches the target NC-NC 3 through the hop NC-NC 1 indicated by the fourth target routing information, and forwards the packet to the second CPU through the NC3, that is, after the packet reaches the NC2, the packet reaches the target CPU according to the path indicated by the fourth target routing information configured in the routing register of the NC 2.

Similarly, when the hop NC indicated by the third target routing information is NC1 and the hop NC indicated by the fourth target routing information is NC0, if the first CPU in the eighth CPU group 18 connected to NC3 needs to access the second CPU in the sixth CPU group 16 connected to NC2 and there is no shortest path for forwarding a packet, the first CPU sends the packet to NC3, and then reaches the target NC-NC 2 through the hop NC-NC 1 indicated by the third target routing information, and forwards the packet to the second CPU through NC2, that is, after the packet reaches NC3, the packet reaches the target CPU according to the path indicated by the third target routing information configured in the routing register of NC 3.

If the second CPU in the sixth CPU group 16 connected to the NC2 needs to access the first CPU in the eighth CPU group 18 connected to the NC3 and there is no shortest path for forwarding a packet, the second CPU sends the packet to the NC2, and then reaches the target NC-NC 3 through the hop NC-NC 0 indicated by the fourth target routing information, and forwards the packet to the second CPU through the NC3, that is, after the packet reaches the NC2, the packet reaches the target CPU according to the path indicated by the fourth target routing information configured in the routing register of the NC 2.

The above explanation is a specific implementation of corresponding steps S201 to S213 "when the first target NC is NC0, the second target NC is NC3, and the link between NC0 and NC1 and the link between NC3 and NC2 fail in the CPU interconnect architecture shown in fig. 5.

In this embodiment, the BMC configures, for the two NCs corresponding to the failed link, the routing information of the CPU connected to the two NCs, respectively, and the skip NCs of the routing information of the two NCs corresponding to the same failed link are different, so that when the link fails, resource competition cannot occur while the corresponding CPU is still accessible, a phenomenon of node deadlock is avoided, and a probability of system downtime is reduced.

Further, in the above embodiment, the BMC determines the first routing configuration information and the second routing configuration information according to a dimension order routing algorithm, and may specifically be implemented based on the following method: and constructing a virtual framework of a plurality of NCs belonging to the same NC group, wherein the virtual framework is a virtual polygon formed by the plurality of NCs and the position relation of each NC in the virtual polygon. Such as: if one NC group comprises 4 NCs, the virtual frameworks of the multiple NCs of the same NC group are a virtual quadrangle and the positions of the 4 NCs in the virtual quadrangle; that is, if one NC group includes N NCs, the virtual structure of the NCs of the same NC group is a virtual N-polygon and the positions of the N NCs in the virtual polygon.

The virtual quadrangle can be a virtual rectangle or a virtual parallelogram.

If one NC group comprises 4 NCs, the dimension order routing algorithm is based on a preset condition, wherein the preset condition is that after a first message reaches a first to-be-configured NC corresponding to a fault link, the first to-be-configured NC can send the first message to a first jump NC along the side of a target virtual rectangle in the horizontal direction, the first jump NC sends the first message to a second to-be-configured NC (another NC corresponding to the fault link) along the side of the target virtual rectangle in the vertical direction, and after a second message reaches the second to-be-configured NC, the second to-be-configured NC can send the second message to the second jump NC along the side of the target virtual rectangle in the horizontal direction, and the second jump NC sends the second message to the first to-be-configured NC along the side of the target virtual rectangle in the vertical direction;

or the preset condition is that when the first message reaches the first to-be-configured NC corresponding to the fault link, the first to-be-configured NC can send the message to the first jump NC along the edge in the vertical direction of the target virtual rectangle, the first jump NC sends the first message to the second to-be-configured NC along the edge in the horizontal direction of the target virtual rectangle, and when the second message reaches the second to-be-configured NC, the second to-be-configured NC can send the second message to the second jump NC along the edge in the vertical direction of the target virtual rectangle, and the second jump NC can send the second message to the first to-be-configured NC along the edge in the horizontal direction of the target virtual rectangle;

and connecting the first NC to be configured and the second NC to be configured as a diagonal line of the target virtual rectangle.

Fig. 7 is a schematic diagram of a virtual rectangle formed by an NC according to an embodiment of the present application, fig. 8 is a virtual rectangle formed by a link formed by a and B in fig. 7 after a failure occurs, and fig. 9 is a virtual rectangle formed by a link formed by a and C in fig. 7 after a failure occurs.

Referring to fig. 7, A, B, C, D in fig. 7 are four NCs constituting a virtual rectangle. When a link composed of two NCs not on the diagonal line in the virtual rectangle fails, for example, the link between a and B fails, B is moved to the position of the diagonal line of a, and is converted into a new rectangle, i.e., the target virtual rectangle, as shown in fig. 8. At this time, a path indicated by first routing information corresponding to the first routing configuration information obtained based on the dimension order routing algorithm may be a-B to a-D-B, and a path indicated by second routing information corresponding to the second routing configuration information obtained based on the dimension order routing algorithm to a-B to a-C-a; or, the path indicated by the first routing information corresponding to the first routing configuration information obtained based on the dimensional sequence routing algorithm may be a-C-B, and the path indicated by the second routing information corresponding to the second routing configuration information obtained based on the dimensional sequence routing algorithm may be B-D-a.

When a failure occurs in the link formed by a and D in fig. 7, since a and D are originally at diagonal positions, it is not necessary to convert the quadrangle, and the rectangle shown in fig. 7 is the target virtual rectangle. A path indicated by first routing information corresponding to first routing configuration information obtained based on the dimension order routing algorithm may be a-B-D, and a path indicated by second routing information corresponding to second routing configuration information obtained based on the dimension order routing algorithm may be D-C-a; or, a path indicated by the first routing information corresponding to the first routing configuration information obtained based on the dimension order routing algorithm may be a-C-D, and a path indicated by the second routing information corresponding to the second routing configuration information obtained based on the dimension order routing algorithm may be D-B-a.

If a link composed of a and C in fig. 7 fails, C is moved to a diagonal position of a, and is transformed into a new rectangle, that is, a target virtual rectangle, as shown in fig. 9, a path indicated by first routing information corresponding to the first routing configuration information obtained based on the dimension order routing algorithm may be a-B-C, and a path indicated by second routing information corresponding to the second routing configuration information obtained based on the dimension order routing algorithm may be C-D-a; or, the path indicated by the first routing information corresponding to the first routing configuration information obtained based on the dimensional sequence routing algorithm may be a-C, and the path indicated by the second routing information corresponding to the second routing configuration information obtained based on the dimensional sequence routing algorithm may be C-B-a.

For the case that each link where other NCs except a fails, refer to the above method, and are not described in detail here.

That is to say: for a target virtual quadrangle, two NCs corresponding to a fault link in the target virtual quadrangle are located at diagonal positions, routing information configured for the two NCs of the fault link needs to enable a message to reach one of the NCs and be forwarded to the other NC, and in the process that the message reaches the other NC and is forwarded to the one NC, transmission rules on the transformed virtual quadrangle are the same, that is, a skip NC based on dimension sequence routing enables skip NCs corresponding to paths visited by CPUs connected with the two NCs corresponding to the fault link to be different. Therefore, the purposes of avoiding resource competition and node deadlock in the embodiment are achieved.

In the foregoing embodiments, a CPU interconnect architecture in which one NC group includes 4 NCs is taken as an example for explanation, and of course, the embodiments of the present application do not limit the number of NCs included in one NC group, for example: one NC group can comprise 5 NCs, and only the condition that the jump NCs corresponding to the paths visited by the CPUs respectively connected with the two NCs corresponding to the fault link are different is required.

Fig. 10 is a schematic structural diagram of a first routing management device of a node controller according to an embodiment of the present application, and referring to fig. 10, the device according to the embodiment includes: judging module 21, sending module 22 and determining module 23

The node controller NC group comprises a plurality of NCs, each NC in the same NC group is connected in pairs, each CPU group comprises a plurality of CPUs, each NC in the NC group is at least connected with one CPU group, and each CPU in the same group is connected in pairs or in an annular shape.

The judging module 21 is configured to judge whether each link where the target NC is located fails according to state information of the target NC connected to the substrate controller; the state information is used for indicating the working state of each link where the target NC is located;

a sending module 22, configured to send, if there is a faulty link that cannot work normally, first routing configuration information to the target NC and the to-be-configured NC corresponding to the faulty link, where the first routing configuration information is used by the target NC to obtain first routing information from the NC to the to-be-configured NC, the second routing configuration information is used by the to-be-configured NC to obtain second routing information from the to-be-configured NC to the target NC, and the first routing information and the second routing information respectively indicate different NC hops.

The first routing information and the second routing information comprise routing enabling identification, jump NC identification and destination NC identification; the destination NC indicated by the first routing information is the NC to be configured, and the destination NC indicated by the second routing information is the target NC.

A determining module 23 configured to: and determining the first routing configuration information and the second routing configuration information according to a dimension order routing algorithm.

The apparatus provided in the embodiment of the present application may perform the corresponding method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.

the preset condition is that after a first message reaches the target NC, the target NC can send the first message to a first jump NC along the edge of the virtual rectangle in the vertical direction, and the first jump NC sends the first message to the NC to be configured along the edge of the virtual rectangle in the horizontal direction;

In a possible design, the determining module 21 is specifically configured to:

Fig. 11 is a schematic structural diagram of a second routing management device of a node controller according to an embodiment of the present application, and referring to fig. 11, the device according to the embodiment includes: a sending module 31 and a routing information obtaining module 32.

The node controller NC group comprises a plurality of NCs, the plurality of NCs in the NC group are connected in pairs, each CPU group comprises a plurality of CPUs, each NC in the NC group is at least connected with one CPU group, and the CPUs in the same group are connected in pairs or in an annular shape.

A sending module 31, configured to send status information to the first substrate controller BMC, where the status information is used to indicate a working state of each link where the target NC is located;

a routing information obtaining module 32, configured to receive, if a first link of multiple links where the target NC is located fails, first routing configuration information sent by the BMC, and obtain, according to the first routing configuration information, first routing information from the target NC to another NC corresponding to the first link; and the second routing information is obtained by the other NC according to second routing configuration information sent by a second BMC.

The first routing information and the second routing information comprise routing enabling identification, jump NC identification and destination NC identification; the destination NC indicated by the first routing information is the other NC, and the destination NC indicated by the second routing information is the target NC.

An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and the computer program enables a processor to execute the method executed by the BMC in the foregoing method embodiment.

Fig. 12 is a schematic structural diagram of a substrate controller according to an embodiment of the present application, including: memory 41, processor 42 and communication bus 43; the communication bus 43 is used for connection between the components.

The memory 41 for storing program instructions;

the processor 42 is configured to call the program instruction stored in the memory to implement the method executed by the BMC in the foregoing method embodiment.

The substrate controller provided in the embodiments of the present application may implement the corresponding method embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.

An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and the computer program enables a processor to execute the method performed by the NC in the above method embodiment.

Fig. 13 is a schematic structural diagram of a node controller according to an embodiment of the present application, including: a memory 51, a processor 52 and a communication bus 53; the communication bus 53 is used to realize connection between the components.

The memory 51 for storing program instructions;

the processor 52 is configured to call the program instructions stored in the memory to implement the method executed by the NC in the above method embodiment.

The node controller provided in the embodiment of the present application may implement the corresponding method embodiment, and its implementation principle and technical effect are similar, which are not described herein again.

Claims

1. A routing management method of a Node Controller (NC) group comprises a plurality of NCs, and the NCs in the same NC group are connected in pairs, and the method is characterized by comprising the following steps:

if a fault link which cannot work normally exists, the substrate controller sends first routing configuration information to the target NC and a to-be-configured NC corresponding to the fault link, the first routing configuration information is used for the target NC to obtain first routing information from the target NC to the to-be-configured NC, the second routing configuration information is used for the to-be-configured NC to obtain second routing information from the to-be-configured NC to the target NC, and the jumping NC indicated by the first routing information and the second routing information are different.

2. The method according to claim 1, wherein before the target NC and the NC to be configured corresponding to the failed link, the substrate controller sends first routing configuration information to the target NC and sends second routing configuration information to the NC to be configured, the method further comprises:

3. The method according to claim 2, wherein when the target NC and the NC group in which the NCs to be configured are located include 4 NCs, the 4 NCs constitute a virtual rectangle, and the 4 NCs are four vertices of the virtual rectangle;

the dimension order routing algorithm is based on a preset condition, wherein the preset condition is that after a first message reaches the target NC, the target NC can send the first message to a first jump NC along the edge of the virtual rectangle in the horizontal direction, and the first jump NC sends the first message to the NC to be configured along the edge of the virtual rectangle in the vertical direction;

4. The method according to claim 2, wherein when the target NC and the NC group in which the NCs to be configured are located include 4 NCs, the 4 NCs constitute a virtual rectangle, and the 4 NCs are four vertices of the virtual rectangle;

5. The method according to any one of claims 1 to 4, wherein when the target NC and the NC group in which the NC to be configured is located include 4 NCs, if the jump NC indicated by the first routing information is the first NC, the jump NC indicated by the second routing information is the second NC, and if the jump NC indicated by the first routing information is the second NC, the jump NC indicated by the second routing information is the first NC;

6. The method according to any one of claims 1 to 4, wherein the determining whether each link where the target NC is located has a fault according to the state information of the NC comprises:

7. The method according to any one of claims 1 to 4, wherein the first routing information and the second routing information each include a routing enable identifier, an identifier of a hop NC and an identifier of a destination NC;

8. A routing management method of a Node Controller (NC) group comprises a plurality of NCs, and the plurality of NCs in the NC group are connected pairwise, and the method is characterized by comprising the following steps:

9. The method of claim 8, wherein the first routing information and the second routing information each comprise a routing enable identifier, an identifier of a hop NC, and an identifier of a destination NC;

10. A node controller's route management device, node controller NC group include a plurality of NC, two liang of NC in the same NC group connect, its characterized in that includes:

11. The apparatus of claim 10, further comprising a determination module configured to:

12. The apparatus according to claim 11, wherein when the target NC and the NC group in which the NCs to be configured are located include 4 NCs, the 4 NCs constitute a virtual rectangle, and the 4 NCs are four vertices of the virtual rectangle, the dimension order routing algorithm is based on a preset condition;

13. The apparatus according to claim 11, wherein when the target NC and the NC group in which the NCs to be configured are located include 4 NCs, the 4 NCs constitute a virtual rectangle, and the 4 NCs are four vertices of the virtual rectangle, the dimension order routing algorithm is based on a preset condition;

the preset condition is that after a first message reaches the target NC, the target NC can send the first message to a first jump NC along the edge of the virtual rectangle in the vertical direction, and the first jump NC can send the first message to the NC to be configured along the edge of the virtual rectangle in the horizontal direction;

14. The apparatus according to any one of claims 10 to 13, wherein when the target NC and the NC group in which the NC to be configured is located include 4 NCs, if the jump NC indicated by the first routing information is a first NC, the jump NC indicated by the second routing information is a second NC, and if the jump NC indicated by the first routing information is a second NC, the jump NC indicated by the second routing information is the first NC;

15. The apparatus according to any one of claims 10 to 13, wherein the determining module is specifically configured to:

16. The apparatus according to any one of claims 10 to 13, wherein the first routing information and the second routing information each include a routing enable identifier, an identifier of a hop NC, and an identifier of a destination NC;

17. A node controller's route management device, node controller NC group include a plurality of NC, two liang of connections of a plurality of NC in the NC group, its characterized in that includes:

18. The apparatus of claim 17, wherein the first routing information and the second routing information each comprise a routing enable identifier, an identifier of a hop NC, and an identifier of a destination NC;

19. A computer-readable storage medium, characterized in that it stores a computer program which causes a processor to execute the method of any of claims 1 to 7.

20. A substrate controller, comprising: a memory and a processor;

the memory to store program instructions;

the processor for invoking the program instructions stored in the memory to implement the method of any of claims 1-7.

21. A computer-readable storage medium, characterized in that it stores a computer program which causes a processor to execute the method of claim 8 or 9.

22. A node controller, comprising: a memory and a processor;

the memory to store program instructions;

the processor for invoking the program instructions stored in the memory to implement the method of claim 8 or 9.