CN108631898B - A kind of fiber optic serial data communications method - Google Patents
A kind of fiber optic serial data communications method Download PDFInfo
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- 239000000835 fiber Substances 0.000 title claims abstract description 16
- 238000005070 sampling Methods 0.000 claims abstract description 70
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- H—ELECTRICITY
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- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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Abstract
The embodiment of the present invention provides a kind of fiber optic serial data communications method, by adding standard tranmitting data register signal in a data frame, the standard tranmitting data register signal includes preset quantity high level signal and/or low level signal, when data receiver receives the data frame, data receiver determines sampling clock cycle according to the standard tranmitting data register signal received, thus generates corresponding sampled clock signal；It is sampled using data portion of the sampled clock signal to data frame, to obtain corresponding data packet in data frame.Due to including standard tranmitting data register signal in data frame, no matter data sending terminal is with which kind of traffic rate transmission data frame, data receiver adaptively can generate reception of the corresponding sampled clock signal realization to data frame according to standard tranmitting data register signal, to data sending terminal can flexibly adjustment data frame traffic rate, the data frame for the reception different communication rate that data receiver can be adaptive.
Description
Technical field
The present embodiments relate to fields of communication technology, more particularly, to a kind of fiber optic serial data communications method.
Background technique
With deepening constantly for power electronic system intelligent Process, interconnecting for more equipment rooms is just gradually reinforced, right
The data communication mode of high performance-price ratio produces great demand.Consideration power electronic equipment inside strong electromagnetic interference environment is simultaneously most
It may be decreased the complexity of interconnection line, industry generallys use fiber optic communication to realize the reliable data transmission of equipment room.In conjunction with electricity
Constant switching frequency control model used by power electronic system, the data communication of equipment room need to also be passed with constant switching frequency
Defeated, i.e., data communication need to have high real-time.In general, the switching frequency of power electronic equipment changes from several hundred Hz to tens kHz,
Level change period minimum is only tens μ s in data communication, proposes challenge to traffic rate.
Currently, the rate of the conventional communication modes such as UART, CAN, SPI for being developed based on control panel grade is also lower, nothing
Method meets short switch periods, massive dataflow transmission；For the novel high speeds communication mode such as PROFIBUS, optical fiber ring network,
Since it realizes that difficulty is larger, hardware and software cost is high, do not have advantage for extensive commercial power electronic equipment.Therefore, it ties
Software and hardware feature in power electronic control system is closed, exploitation is relatively single with function, it is simple to realize, the reliable optical fiber of high speed leads to
Letter becomes feasible technology path.
The characteristics of power electronic control system software and hardware is can be by being adjusted flexibly the volume of data frame in data sending terminal
The frequency of code tranmitting data register signal, to meet the requirement of different communication rate, the period of the coding tranmitting data register signal corresponds to number
According to the duration of a code symbols in frame；And in data receiver, it needs by all with code symbols each in data frame
Phase corresponding sampled clock signal, which is just able to achieve, is properly received data frame.In current data communications method, data are connect
Receiving end receives data frame with the sampled clock signal made an appointment, and the sampled clock signal made an appointment has specific
Sampling clock cycle, when the code period of data frame changes or receiving-transmitting sides clock frequency difference is larger, data receiver without
The complete paired data frame of method is properly received.
Summary of the invention
In order to overcome the above problem or at least be partially solved the above problem, the embodiment of the present invention provides a kind of optical fiber string
Row data communications method.
The embodiment of the present invention provides a kind of fiber optic serial data communications method, and this method is data sending terminal method, comprising:
Data frame is generated according to customized frame format, data frame includes standard tranmitting data register signal, and standard tranmitting data register signal includes pre-
If quantity high level signal and/or low level signal, and each high level signal and/or the lasting when appearance of low level signal
Deng standard tranmitting data register signal is located at after the frame head of data frame, and standard tranmitting data register signal is located at the data portion of data frame
/ preceding；Data receiver is sent a dataframe to, for when data receiver is determined according to standard tranmitting data register signal to be sampled
The clock period, and sampled clock signal is generated according to sampling clock cycle, then by sampled clock signal to the data portion of data frame
Divide and is sampled, the corresponding data packet of the data portion to obtain data frame.
The embodiment of the present invention provides a kind of fiber optic serial data communications method, and this method is data receiver method, comprising:
The data frame that data sending terminal is sent is received, sampling clock cycle, standard are determined according to the standard tranmitting data register signal of data frame
Tranmitting data register signal includes preset quantity high level signal and/or low level signal, and each high level signal and/or low electricity
The lasting duration of ordinary mail number is equal；Sampled clock signal is generated according to sampling clock cycle, by sampled clock signal to data
The data portion of frame is sampled, and decodes the corresponding data packet of data portion obtained in data frame.
A kind of fiber optic serial data communications method provided in an embodiment of the present invention is sent by adding standard in a data frame
Clock signal, which includes preset quantity high level signal and/or low level signal, in data receiver
For termination when receiving the data frame, data receiver determines sampling clock cycle according to standard tranmitting data register signal, thus generates pair
The sampled clock signal answered；It is sampled using data portion of the sampled clock signal to data frame, to obtain in data frame
The corresponding data packet of data portion.Due to including standard tranmitting data register signal in data frame, no matter data sending terminal is with what
Kind of traffic rate sends data frame, and what data receiver can be adaptive generates corresponding sampling according to standard tranmitting data register signal
Clock signal realizes reception to data frame, thus data sending terminal can flexibly adjustment data frame traffic rate, data connect
Receiving end can be adaptive reception different communication rate data frame.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the flow chart according to the data sending terminal method of the fiber optic serial data communications method of the embodiment of the present invention；
Fig. 2 is the schematic diagram according to the frame format of the embodiment of the present invention；
Fig. 3 is the flow chart according to the data receiver method of the fiber optic serial data communications method of the embodiment of the present invention；
Fig. 4 is the schematic diagram according to the generation sampled clock signal of the embodiment of the present invention；
Fig. 5 is the schematic diagram being adjusted to sampled clock signal according to the embodiment of the present invention；
Fig. 6 is the schematic diagram sampled to level in data frame according to the embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of fiber optic serial data communications method, and with reference to Fig. 1, this method is data sending terminal side
Method, comprising: S11 generates data frame according to customized frame format, and data frame includes standard tranmitting data register signal, when standard is sent
Clock signal includes preset quantity high level signal and/or low level signal, and each high level signal and/or low level signal
Lasting duration is equal, and standard tranmitting data register signal is located at after the frame head of data frame, and standard tranmitting data register signal is located at number
Before the data portion of frame；S12 sends a dataframe to data receiver, when being sent for data receiver according to standard
Clock signal determines sampling clock cycle, and generates sampled clock signal according to sampling clock cycle, then pass through sampled clock signal
The data portion of data frame is sampled, the corresponding data packet of the data portion to obtain data frame.
It should be noted that the executing subject of the embodiment of the present invention is data sending terminal.
Specifically, in the present embodiment, the required standard tranmitting data register signal area in customized frame format, as shown in Fig. 2,
The standard tranmitting data register signal area is located at after frame head region, and is located at before data portion region.Based on the customized frame
Format generates data frame, to include standard tranmitting data register signal in data frame, the standard tranmitting data register signal is by preset quantity
A high level signal and/or low level signal composition.The standard tranmitting data register signal is identified for the ease of data receiver, it can root
According to frame head level the characteristics of the level of the standard tranmitting data register signal is set, for example, the frame head of data frame is the height of 8bit
Level then sets low level, i.e. the last one level and standard of frame head for first level of standard tranmitting data register signal
The low and high level of first level of tranmitting data register signal, can quickly really on the contrary, in this way, after data receiver recognizes frame head
Calibrate the starting position of quasi- tranmitting data register signal.
In the present embodiment, data frame may include frame head, standard tranmitting data register signal, address signal, data amount check signal, number
According to word, check word and postamble, as shown in Figure 2.
Frame head is the high level signal and/or low level signal in the period of default headnum coding tranmitting data register signal,
To indicate the beginning of a data frame.
Standard tranmitting data register signal is clknum preset high level signals and/or low level signal, and each high electricity
Ordinary mail number and/or low level signal it is lasting duration it is equal, in order to data receiver standard tranmitting data register signal is carried out it is quasi-
It really counts, wherein the last one level of frame head is opposite with the low and high level of first level of standard tranmitting data register signal；With
Sampling clock cycle, synthesis sampled clock signal are determined for data receiver.
Address information includes transmission source address and reception destination address two parts, the bit wide phase of source address and destination address
It together, is addbus.Source address characterizes the address identifier code of communication system locating for data sending terminal, and destination address characterize data connects
The address identifier code of system locating for receiving end.The addition of address bit section to distinguish multi-pass letter node system in specific node between
Data transmission.
Data amount check information is the data word number num that data frame is actually sent every time, obtains number to data receiver
According to the number of word, to control the reception to data word.The bit wide numbus of data amount check can send number according to system single maximum
It is determined according to word number num, and by receiving-transmitting sides are unified, value should be greater than zero.
Data word is the valid data of data communication, is transmitted using 16bit word as basic unit, the data communicated every time
Word number is num.
Check word is that address, data amount check and each data word in serial data format are raw using 16 CRC check criterion
At 16 bit check data words, to receiving end to data transmission and received correctness test.Address and data amount check
Bit wide it is 16 discontented when, high-order zero-adding processing.
Postamble is the high level signal and/or low level signal in the period of default tailnum coding tranmitting data register signal,
To indicate the end of a data frame.
Data sending terminal is by the frame head of data frame, standard tranmitting data register signal, address signal, data amount check signal, data
Word, check word and postamble are sent on optical fiber link by turn according to defined data format.Data receiver is from optical fiber link
On when receiving data frame, sampling clock cycle is determined according to standard tranmitting data register signal, such as calculate standard tranmitting data register letter
Number section duration, sampling clock cycle can be obtained by the duration and preset quantity.According to sampling clock
Period generates sampled clock signal, then is sampled by data portion of the sampled clock signal to data frame, by the knot of sampling
Fruit is converted into binary code, the corresponding data packet of the data portion to obtain data frame.
In the communication transmission process of the present embodiment, low level is set by the level of idle state, frame head may be configured as pre-
If the high level of bit, in order to which data receiver identifies frame head.High level, frame head can also be set by the level of idle state
It is set as the low level of default bit, the present embodiment is without limitation.
The present embodiment includes default by adding standard tranmitting data register signal, the standard tranmitting data register signal in a data frame
Quantity high level signal and/or low level signal, when data receiver receives the data frame, data receiver is according to mark
Quasi- tranmitting data register signal determines sampling clock cycle, thus generates corresponding sampled clock signal；Utilize the sampled clock signal
The data portion of data frame is sampled, to obtain the corresponding data packet of the data portion in data frame.Due in data frame
It include standard tranmitting data register signal, no matter data sending terminal is with which kind of traffic rate transmission data frame, the equal energy of data receiver
Adaptive generates reception of the corresponding sampled clock signal realization to data frame according to standard tranmitting data register signal, thus data
Transmitting terminal can flexibly adjustment data frame traffic rate, the data for the reception different communication rate that data receiver can be adaptive
Frame.
Based on above embodiments, data frame is generated according to customized frame format, comprising: raw according to local system clock signal
It include periodically encoding hopping edge at coding tranmitting data register Signal coding tranmitting data register signal；It is obtained according to customized frame format
Serial symbol sequence, serial symbol sequence include that the frame head of data frame, standard tranmitting data register signal and data portion respectively correspond
Binary code；According to serial symbol sequence, each coding hopping edge in coding tranmitting data register signal generates corresponding
High level or low level, and it is sent to optical fiber link, to generate data frame.
Wherein, coding tranmitting data register signal is generated according to local system clock signal, comprising: obtain the pre- communication of data frame
Rate；Local system clock signal is subjected to frequency dividing and/or process of frequency multiplication, encodes tranmitting data register signal to obtain, and make to encode
It is corresponding with the holding of pre- traffic rate consistent that the corresponding frequency in hopping edge is encoded in tranmitting data register signal.
Specifically, the present embodiment can be determined according to the demand of traffic rate compiles in the coding tranmitting data register signal for coding
The frequency of code hopping edge, recycles local system clock signal to generate the coding tranmitting data register signal with the frequency.
Meanwhile the corresponding binary code of data frame is obtained according to customized frame format, then be based on pre-arranged code rule for two
Each coding hopping edge of the ary codes in coding tranmitting data register signal generates corresponding low and high level, and is sent to optical fiber chain
Road.For example, using NRZ code coding rule, when binary code is " 1 ", generate high level at the coding hopping edge moment, two into
When code processed is " 0 ", low level is generated at the coding hopping edge moment.
In the present embodiment, the above method is realized based on FPGA programming, is programmed using programmable logic device FPGA and realizes number
According to frame format definition, data frame is sent and data frame receipt, does not need additional transmitting-receiving special chip, hardware knot on hardware view
Structure is simple, at low cost.The modification of data frame format and traffic rate can be realized by modifying program in software view, and communication is matched
Set flexibly, exploitation it is succinct efficient.And data communication function is realized using FPGA programming, there is no " run and fly " is existing for communication system
As.It can also realize the above method otherwise, this implementation is herein with no restrictions.
The present embodiment generates the periodic signal for coding by local system clock signal, so as to realize in real time
The purpose of traffic rate is adjusted flexibly.
The embodiment of the present invention also provides a kind of fiber optic serial data communications method, and with reference to Fig. 3, this method is data receiver
Method, comprising: S31 receives the data frame that data sending terminal is sent, determined and sampled according to the standard tranmitting data register signal of data frame
Clock cycle, standard tranmitting data register signal include preset quantity high level signal and/or low level signal, and each high level
Signal and/or low level signal it is lasting duration it is equal；S32 generates sampled clock signal according to sampling clock cycle, by adopting
Sample clock signal samples the data portion of data frame, and decodes the corresponding data of data portion obtained in data frame
Packet.
It should be noted that the executing subject of the embodiment of the present invention is data receiver；The fiber optic serial number of the present embodiment
It has been had a detailed description in the above-described embodiments according to communication means, details are not described herein.
The present embodiment includes default by adding standard tranmitting data register signal, the standard tranmitting data register signal in a data frame
Quantity high level signal and/or low level signal, when data receiver receives the data frame, data receiver is according to mark
Quasi- tranmitting data register signal determines sampling clock cycle, thus generates corresponding sampled clock signal；Utilize the sampled clock signal
The data portion of data frame is sampled, to obtain the corresponding data packet of the data portion in data frame.Due in data frame
It include standard tranmitting data register signal, no matter data sending terminal is with which kind of traffic rate transmission data frame, the equal energy of data receiver
Adaptive generates reception of the corresponding sampled clock signal realization to data frame according to standard tranmitting data register signal, thus data
Transmitting terminal can flexibly adjustment data frame traffic rate, the data for the reception different communication rate that data receiver can be adaptive
Frame.
Based on above embodiments, sampling clock cycle is determined according to the standard tranmitting data register signal of data frame, comprising: pass through
Local system clock signal carries out sample count to the section of standard tranmitting data register signal, obtains the area of standard tranmitting data register signal
Between include local system clock signal count value；The local system clock that the section of acquisition standard tranmitting data register signal includes
Ratio value between the count value and preset quantity of signal；It is determined and is sampled according to the period of local system clock signal and ratio value
Clock cycle.
Specifically, as shown in figure 4, data receiver recognizes the frame head of data frame, the finish time of frame head is determined as
Frame head distinguishing mark, since where frame head distinguishing mark at the time of, start to send standard using local system clock signal
Clock signal carries out sample count, until the section of standard tranmitting data register signal terminates, obtains count value, which is to mark
The quantity for the local system clock signal that the section of quasi- tranmitting data register signal includes.Thus to obtain the area of standard tranmitting data register signal
Between include local system clock signal quantity and preset quantity between ratio value, pass through the week of local system clock signal
Phase and ratio value determine the sampling clock cycle of received data frame.In order to improve having for sampling clock cycle obtained
Effect property is rounded numerical value as final ratio value with the ratio of preset quantity for after count value plus 1.
By the above method, can guarantee the sampled clock signal of data receiver period and data sending terminal for compiling
The period of the periodic signal of code is consistent, to guarantee the correct sampling to serial data level in data frame.
For example, the frequency of local system clock signal is 100MHz, the periodic signal for coding of data sending terminal
Frequency is 20MHz, and preset quantity 4, then theoretic count value should be 20, and ratio value (count value) is 5, finally calculates and obtains
The frequency of the sampled clock signal of the data receiver obtained is 20MHz, when sending with the coding for coding of data sending terminal
The frequency of clock signal is identical (i.e. the period is identical).
Based on above embodiments, sampled clock signal is generated according to sampling clock cycle, comprising: in each sampling clock week
Preceding first preset period of time of phase generates and keeps high level, generates and protects in rear second preset period of time of each sampling clock cycle
Bottom level is held, to generate the period 1 signal in each sampling clock cycle with level jump edge；Alternatively, being adopted each
The preceding third preset period of time of sample clock cycle generates and keeps low level, in rear 4th preset period of time of each sampling clock cycle
High level is generated and keeps, to generate the second round signal in each sampling clock cycle with level jump edge；By
One periodic signal or second round signal are as sampled clock signal.
Specifically, local system clock signal has the characteristics that frequency is high, in each sampling clock cycle, comprising multiple
Local system clock signal, such as the frequency of local system clock signal is 100MHz, and the frequency of sampled clock signal is
20MHz, then each sampling clock cycle may include 5 local system clock signals.It is available for each sampling clock cycle
The period of sampling clock cycle is divided into two parts by local system clock signal, and front portion includes the first quantity local system
Clock signal, rear portion include the second quantity local system clock signal；When it is implemented, local in preceding first quantity
Low level or high level are generated and kept in the period of clock signal of system, are believed in rear second quantity local system clock
Number period in generate and keep corresponding high level or low level, so as to be produced in the section of each sampling clock cycle
A raw hopping edge, using the periodic signal in the section of each sampling clock cycle with a level jump edge as sampling
Clock signal.The data receiver sampling to level in data frame in real time will pass through one for sampled clock signal and data frame
The process of middle low and high level alignment, if level jump in each sampling clock cycle along at the edge of sampling clock cycle,
The edge moment just when data frame in low and high level jumping moment, lead to not accurate sampled data, adopted each
The level jump of sample clock cycle is along being set in the section of sampling clock cycle, preferably by the electricity of each sampling clock cycle
Flat hopping edge is set to the intermediate time of sampling clock cycle, can avoid such case.
The present embodiment is by generating the period letter with a level jump edge in the section of each sampling clock cycle
Number be used as sampled clock signal, thus using level jump along data frame is sampled when, be avoided that level jump along exist
May cause when the edge of each sampling clock cycle can not accurate sampled data the case where.
Based on above embodiments, after sampling clock cycle generation sampled clock signal, further includes: extract data portion
The level jump divided is along signal；According to the level jump of data portion along signal, sampled clock signal is adjusted, to eliminate to sampling
Frequency difference cumulative errors caused by clock signal and/or interference cumulative errors.
Specifically, due to not including timing information in data frame, in the case where that can not synchronize, as shown in figure 5, due to number
According to frequency error intrinsic between transmitting terminal and the system clock of data receiver or fiber links mushing error, with serial number
According to the progress of transmitting-receiving, frequency difference accumulated error or interference accumulated error are gradually increased, and may cause data receiver when error is excessive
End can not correctly sample.
In the present embodiment, the hopping edge of data portion level signal in data frame can extract, in a data frame level signal
The hopping edge moment, synchronized sampling clock signal will be corresponding in sampled clock signal in the case where there are negative cumulative errors
Sampling clock cycle Forward, will be after sampling clock cycle corresponding in sampled clock signal in the case where there are positive cumulative errors
It moves, above procedure can synthesize clock counter by asynchronous reset to complete.
The present embodiment adjusts sampled clock signal by the hopping edge of level signal in data frame, ensure that data receiver
The correct sampling to level in data frame is held, and then improves the reliability of communication.
Based on above embodiments, as shown in fig. 6, sampled by data portion of the sampled clock signal to data frame,
It include: level of the level jump in sampled clock signal in each sampling clock cycle along instance sample data portion.
Based on the above embodiment, the present embodiment further includes the correctness verification to data communication, is divided into two steps progress: 1, number
16 CRC check algorithms are used according to address signal, data amount check signal and all data words that receiving end obtains sampling reduction,
Check value is calculated.2, data receiver is by the check value being calculated and the check word directly sampled from data frame
It is compared, if the two is identical, data communication and reception are correct, update output data；If the two is unequal, data transmission
Or occur error code mistake in receive process, give up this data received.In addition, when the destination address and this node that receive
When address mismatches, similarly give up the data received.The CRC check algorithm of receiving-transmitting sides is multinomial using identical verification
Formula.
The embodiment of the present invention also provides a kind of non-transient computer readable storage medium, the non-transient computer readable storage
Medium storing computer program, the computer program provide the above-mentioned each data sending terminal embodiment of the method for computer execution
Method, for example, data frame is generated according to customized frame format, data frame includes standard tranmitting data register signal, standard hair
Sending clock signal includes preset quantity high level signal and/or low level signal, and standard tranmitting data register signal is located at data frame
Frame head after, and standard tranmitting data register signal is located at before the data portion of data frame；Send a dataframe to data receiver
End, so that data receiver determines sampling clock cycle according to standard tranmitting data register signal, and generates according to sampling clock cycle
Sampled clock signal, then sampled by data portion of the sampled clock signal to data frame, to obtain the data of data frame
The corresponding data packet in part.
The embodiment of the present invention also provides a kind of non-transient computer readable storage medium, the non-transient computer readable storage
Medium storing computer program, the computer program provide the above-mentioned each data receiver embodiment of the method for computer execution
Method, for example, receive data sending terminal send data frame, according to the standard tranmitting data register signal of data frame determination adopt
Sample clock cycle, standard tranmitting data register signal include preset quantity high level signal and/or low level signal；When according to sampling
The clock period generates sampled clock signal, is sampled by data portion of the sampled clock signal to data frame, and decode acquisition
The corresponding data packet of data portion in data frame.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
Computer program instructions relevant hardware is completed, and computer program above-mentioned can store to be situated between in a computer-readable storage
In matter, which when being executed, executes step including the steps of the foregoing method embodiments；And storage medium above-mentioned includes:
The various media that can store program code such as ROM, RAM, magnetic or disk.
Through the above description of the embodiments, those skilled in the art can be understood that each embodiment can
It realizes by means of software and necessary general hardware platform, naturally it is also possible to pass through hardware.Based on this understanding, on
Stating technical solution, substantially the part that contributes to existing technology can be embodied in the form of software products in other words, should
Computer software product may be stored in a computer readable storage medium, such as ROM/RAM, magnetic disk, CD, including several fingers
It enables and using so that a computer equipment (can be personal computer, server or the network equipment etc.) executes each implementation
Method described in certain parts of example or embodiment.
Finally, it is stated that: the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although ginseng
According to previous embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be with
It modifies the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit and model of technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (6)
1. a kind of fiber optic serial data communications method characterized by comprising
Data frame is generated according to customized frame format, the data frame includes standard tranmitting data register signal, when the standard is sent
Clock signal includes preset quantity high level signal and/or low level signal, and each high level signal and/or low level signal
Lasting duration is equal, and the standard tranmitting data register signal is located at after the frame head of the data frame, and when standard transmission
Clock signal is located at before the data portion of the data frame；
The data frame is sent to data receiver, so that the data receiver is true according to the standard tranmitting data register signal
Determine sampling clock cycle, and sampled clock signal is generated according to the sampling clock cycle, then pass through the sampled clock signal
The data portion of the data frame is sampled, the corresponding data packet of the data portion to obtain the data frame；
It is wherein, described that data frame is generated according to customized frame format, comprising:
Coding tranmitting data register signal is generated according to local system clock signal, the coding tranmitting data register signal includes periodic
Encode hopping edge；
Serial symbol sequence is obtained according to the customized frame format, the serial symbol sequence includes the frame of the data frame
Head, standard tranmitting data register signal and the corresponding binary code of data portion；
According to the serial symbol sequence, each coding hopping edge in the coding tranmitting data register signal generates corresponding
High level or low level, and it is sent to optical fiber link, to generate the data frame.
2. the method according to claim 1, wherein described generate coding transmission according to local system clock signal
Clock signal, comprising:
Obtain the pre- traffic rate of the data frame；
The local system clock signal is subjected to frequency dividing and/or process of frequency multiplication, to obtain the coding tranmitting data register signal, and
Keep the corresponding frequency in coding hopping edge in the coding tranmitting data register signal corresponding with the pre- traffic rate holding consistent.
3. a kind of fiber optic serial data communications method characterized by comprising
The data frame that data sending terminal is sent is received, sampling clock week is determined according to the standard tranmitting data register signal of the data frame
Phase, the standard tranmitting data register signal includes preset quantity high level signal and/or low level signal, and each high level is believed
Number and/or low level signal it is lasting duration it is equal；
Sampled clock signal is generated according to the sampling clock cycle, by the sampled clock signal to the number of the data frame
According to partially being sampled, and decode the corresponding data packet of data portion obtained in the data frame；
It is wherein, described that sampled clock signal is generated according to the sampling clock cycle, comprising:
The first preset period of time generates and keeps high level before each sampling clock cycle, after each sampling clock cycle
Second preset period of time generates and keeps low level, to generate first week in each sampling clock cycle with level jump edge
Phase signal；Alternatively, the preceding third preset period of time in each sampling clock cycle generates and keeps low level, in each sampling clock
Rear 4th preset period of time in period generates and keeps high level, has level jump edge in each sampling clock cycle to generate
Second round signal；
Using the period 1 signal or the second round signal as the sampled clock signal.
4. according to the method described in claim 3, it is characterized in that, the standard tranmitting data register signal according to the data frame
Determine sampling clock cycle, comprising:
Sample count is carried out by section of the local system clock signal to the standard tranmitting data register signal, obtains the standard
The count value for the local system clock signal that the section of tranmitting data register signal includes；
Obtain the count value of the local system clock signal that the section of the standard tranmitting data register signal includes with it is described pre-
If the ratio value between quantity；
The sampling clock cycle is determined according to the period of the local system clock signal and the ratio value.
5. according to the method described in claim 3, it is characterized in that, described generate sampling clock according to the sampling clock cycle
After signal, further includes:
The level jump of the data portion is extracted along signal；
According to the level jump of the data portion along signal, the sampled clock signal is adjusted, when eliminating to the sampling
Frequency difference cumulative errors caused by clock signal and/or interference cumulative errors.
6. according to the method described in claim 3, it is characterized in that, it is described by the sampled clock signal to the data frame
Data portion sampled, comprising:
Level jump in the sampled clock signal in each sampling clock cycle is along data portion described in instance sample
Level.
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| CN109905204B (en) * | 2019-03-29 | 2021-12-03 | 京东方科技集团股份有限公司 | Data sending and receiving method, corresponding device and storage medium |
| CN112765073A (en) * | 2019-11-04 | 2021-05-07 | 中车株洲电力机车研究所有限公司 | Data sampling method, system, storage medium and computer equipment |
| CN111159091B (en) * | 2019-12-31 | 2022-09-16 | 中国电子科技集团公司第二十八研究所 | High-speed serial port implementation method based on internal clock |
| CN112019318B (en) * | 2020-08-20 | 2021-08-20 | 珠海格力电器股份有限公司 | Method for improving communication reliability of equipment |
| CN113886300B (en) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
| CN114124283B (en) * | 2021-12-01 | 2023-11-03 | 岱昆半导体(上海)有限公司 | Single-wire communication method based on frequency coding |
| CN115664622B (en) * | 2022-10-18 | 2023-07-04 | 安徽共芯光子科技有限公司 | Manchester decoding method |
| CN115665062A (en) * | 2022-10-18 | 2023-01-31 | 苏州金橙子激光技术有限公司 | Single-wire communication method between laser marking card and galvanometer |
| CN115421928B (en) * | 2022-11-04 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | Device and method for reducing electromagnetic interference generated by chip and electronic equipment |
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