CN108630546A - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN108630546A CN108630546A CN201710161180.5A CN201710161180A CN108630546A CN 108630546 A CN108630546 A CN 108630546A CN 201710161180 A CN201710161180 A CN 201710161180A CN 108630546 A CN108630546 A CN 108630546A
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- semiconductor substrate
- well region
- executed
- pouch
- ion implanting
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 64
- 238000005516 engineering process Methods 0.000 claims abstract description 37
- 238000005468 ion implantation Methods 0.000 claims abstract description 34
- 150000002500 ions Chemical class 0.000 claims description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 24
- -1 LDD ion Chemical class 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 description 24
- 239000000463 material Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000001259 photo etching Methods 0.000 description 8
- 238000005040 ion trap Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000012546 transfer Methods 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, the method includes：Semiconductor substrate is provided, is formed with gate structure on the semiconductor substrate；Well region ion implanting step is executed, to form well region in the semiconductor substrate；Pouch-type area and/or LDD ion implanting steps are executed, to form pouch-type area and/or source drain extension area in the semiconductor substrate.The manufacturing method of semiconductor device according to the invention, well region ion implantation technology is executed after grid is formed, is sequentially carried out under same mask conditions with pouch-type ion implanting and/or LDD ion implantation technologies, on the one hand, reduce the use to mask, to reduce production cost；On the other hand, the processing step for effectively reducing semiconductor manufacturing increases the stability of technique.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of manufacturing method of semiconductor devices.
Background technology
In large scale integrated circuit process industry, how to greatest extent reduced cost is that semiconductor manufacturer faces always
Problem.In integrated circuit fabrication, the high-tech node of generally use small size reduces chip size, in the crystalline substance of identical size
More chips are obtained on circle, to reduce one single chip cost.And in semiconductor processing, frequently with reduction mask layer and gold
The use for belonging to layer, to reduce single-wafer production cost.For example, in the mistake for the well region for forming core devices and I/O devices
Cheng Zhong, frequently with identical mask layer to reduce the use of mask.For another example, it is used newly by the logical operation of some masks
Mask is to replace original two or more layers mask, to reduce the use of mask.
Here there is provided a kind of manufacturing methods of semiconductor devices, and the use of mask can be reduced using new technique.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
The present invention provides a kind of manufacturing method of semiconductor devices, the method includes：
Semiconductor substrate is provided, is formed with gate structure on the semiconductor substrate；
Well region ion implanting step is executed, to form well region in the semiconductor substrate；
Pouch-type and/or LDD ion implanting steps are executed, to form pouch-type area and/or source/drain in the semiconductor substrate
Extension area.
Illustratively, the well region ion implanting step includes：
Mask layer is formed on the semiconductor substrate；
The mask layer is patterned to form area to be implanted；
Well region ion implantation technology is executed, to form well region in the semiconductor substrate.
Illustratively, the pouch-type and/or LDD ion implanting steps include, after the well region ion implantation technology,
Pouch-type and/or LDD ion implantation technologies are executed in the area to be implanted.
Illustratively, the gate structure is the laminated construction of gate oxide and polysilicon layer.
Illustratively, the method further includes reoxidizing the polysilicon layer before executing well region ion implanting step
Step.
Illustratively, the method further includes the source/drain executed after executing pouch-type and/or LDD ion implanting steps
Ion implanting step, to form source/drain in the semiconductor substrate.
Illustratively, further include forming the step of clearance wall in the gate structure both sides before forming the source/drain
Suddenly.
Illustratively, the semiconductor devices includes NMOS or PMOS.
The manufacturing method of semiconductor device according to the invention executes well region ion implantation technology after grid is formed,
It is sequentially carried out under same mask conditions with pouch-type ion implanting and/or LDD ion implantation technologies, to complete well region forming process
With the forming process in pouch-type area and/or source drain extension area, on the one hand, reduce the use to mask, be produced into reduce
This；On the other hand, the processing step for effectively reducing semiconductor manufacturing increases the stability of technique.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A~1B is the schematic flow chart of method, semi-conductor device manufacturing method in the prior art；
Fig. 2A~2E cuts open for the structure for the device that correlation step in the manufacturing method of semiconductor devices in the prior art is formed
View；
Fig. 3 is the schematic flow chart of the manufacturing method for the semiconductor devices that one embodiment of the present of invention proposes；
Correlation step is formed in the manufacturing method for the semiconductor devices that Fig. 4 A~4E propose for one embodiment of the present of invention
Device structure sectional view；
Fig. 5 A~5B are the semiconductor device that the manufacturing method for the semiconductor devices that one embodiment of the present of invention proposes is formed
The performance comparison figure of part and the semiconductor devices formed in the prior art.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present inventionization
Learn mechanical grinding method.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.
Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have other realities
Apply mode.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or combination thereof.
Now, exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
To be below embodiment using source/drain region formation process in NMOS device forming process to principle according to the present invention
It is specifically described, it is to be understood that the present invention is carried out with the embodiment that is formed as of source/drain region in NMOS device forming process
Explanation is only exemplary, and any manufacturing process for forming semiconductor device structure according to the present invention is suitable for this hair
It is bright.
It is generally used in existing NMOS device forming process and forms polysilicon gate in the semiconductor substrate after well region is formed
Pole, then source/drain region is formed on the basis of polysilicon gate is formed, a typical technological process is as shown in Figure 1A, first, holds
Row step S101：Semiconductor substrate is provided, executes well region ion implanting step to form ion trap in the semiconductor substrate；
Then, step S102 is executed：Gate structure is formed on the semiconductor substrate；Then, step S103 is executed：Execute it is light-duty from
Sub- injection step forms source/drain extension area in the gate structure both sides；Then, step S104 is executed：In the polysilicon
Gate structure both sides form clearance wall；Then, step S105 is executed：Source/drain region ion implanting step is executed, to form source/drain
Area.
In the technological process, the ion implanting step being related to all refers to the covering of mask, the photoetching of injection region with
And ion implantation technology is completed, the concrete technology arrived as involved in being shown in ion implanting step Figure 1B is being related to
In the technique of ion implanting step, first, step S1011 is executed：Mask film covering layer on a semiconductor substrate；Then, step is executed
Rapid S1012：The mask is patterned, to form area to be implanted；Then, step S1013 is executed：Ion implanting is executed, in this work
The different ions injection region formed as needed in skill executes different ion implantation technologies；Finally, step S1014 is executed：It goes
Except the mask layer；So far a complete ion implanting step is completed.
As Fig. 2A~2E shows the section view of the semiconductor devices formed in a typical semiconductor device technology flow
Figure.First, S101 shown in figure 1A is executed：Semiconductor substrate is provided, executes well region ion implanting in the semiconductor substrate
Upper formation ion trap；As shown in Figure 2 A, semiconductor substrate 200 is provided, well region ion implanting step is executed, is served as a contrast in the semiconductor
Ion trap 202 is formed on bottom 200, in this step, mask film covering layer 201 on a semiconductor substrate first；Then institute is patterned
Mask layer 201 is stated to form area to be implanted；Then well region ion implantation technology is executed, ion trap 202 as shown in Figure 2 A is formed,
Finally, the mask layer 201 is removed to enter next processing step S102 shown in Figure 1A.Then, as shown in Figure 2 B, execute
S102：Gate structure 203 is formed in the semiconductor substrate 200, illustratively, the gate structure includes the grid stacked
Dielectric layer 204 and polycrystalline silicon gate layer 205, illustratively, before forming the gate structure, in the semiconductor substrate
Isolation structure 206 is also formed in 200.Then, as shown in Figure 2 C, S103 is executed：It is executed in the semiconductor substrate 200
LDD ion implantings step forms source drain extension area 207 with the both sides of the gate structure 204 in well region 202, in this step again
It is related to formation, the photoetching of mask layer 207, the removal of ion implantation technology and mask layer 207 is similar with S101, herein not
It repeats again.Then, as shown in Figure 2 D, S104 is executed：Clearance wall 208 is formed in the both sides of gate structure 203.Finally, such as Fig. 2 E
It is shown, execute S105：Source/drain region ion implanting step is executed, source/drain region 210 is formed in semiconductor substrate 200, walks herein
Formation, the photoetching of mask layer 211, the removal of ion implantation technology and mask layer 211, with class in S101 are again related in rapid
Seemingly, details are not described herein.
From the foregoing, it will be observed that in the manufacturing process of existing semiconductor devices, formation, the source drain extension of well region are necessarily undergone
The formation in area and source/drain region, the ion implanting step being related to necessarily refer to the formation, photoetching and removal of mask layer three times.It is more
On the one hand secondary photoetching brings the complexity of technological process, processing step to increase the unstability for causing technique, on the other hand bring as
The waste of mask layer covering process and removal technique, is unfavorable for the reduction of production cost.
For this purpose, the present invention provides a kind of manufacturing methods of semiconductor devices, including：
Semiconductor substrate is provided, is formed with gate structure on the semiconductor substrate；
Well region ion implanting step is executed, to form well region in the semiconductor substrate；
Execute pouch-type area and/or LDD ion implanting steps, with formed in the semiconductor substrate pouch-type area and/or source/
Drain extension region.
The manufacturing method of semiconductor device according to the invention executes well region ion implantation technology after grid is formed,
It is sequentially carried out under same mask conditions with pouch-type ion implanting and/or LDD ion implantation technologies, to complete well region forming process
With the forming process in pouch-type area and/or source drain extension area, on the one hand, reduce the use to mask, be produced into reduce
This；On the other hand, the processing step for effectively reducing semiconductor manufacturing increases the stability of technique.
A kind of manufacturer of semiconductor devices of one embodiment of the present of invention proposition is described with reference to figure 3 and Fig. 4 A~4E
Method, wherein figure be one embodiment of the present of invention propose semiconductor devices manufacturing method schematic flow chart, Fig. 4 A~
The semiconductor devices that correlation step is related in the manufacturing method for the semiconductor devices that 4E proposes for one embodiment of the present of invention
Structure sectional view.
First, step S301 is executed：Semiconductor substrate is provided, gate structure is formed in the semiconductor substrate.
As shown in Figure 4 A, semiconductor substrate 400 is provided, gate structure 401 is formed in the semiconductor substrate 400.Half
The constituent material of conductor substrate 400 can be undoped monocrystalline silicon, the monocrystalline silicon mixed with impurity, silicon-on-insulator (SOI) etc..
Illustratively, the gate structure 401 formed in semiconductor substrate 400 includes gate dielectric layer 402 and grid material
Layer 403.The illustrative gate structure is polysilicon gate construction, gate dielectric 401 be high k dielectric layer, silicon oxide layer,
The dielectric materials such as silicon oxynitride, the gate material layers use polysilicon layer.Illustratively, it is formed on the semiconductor substrate
The step of gate structure：First, gate dielectric is formed on a semiconductor substrate；Then, coprecipitated on the gate dielectric
Product forms polysilicon material layer；Then, the gate dielectric and polysilicon material layer are patterned to form gate structure.It needs
Understand, the present embodiment is illustrated as example using polysilicon gate construction and is not intended to limit the invention, any
Gate structure in semiconductor substrate is suitable for the present invention.
Illustratively, after forming polysilicon gate further include polysilicon gate secondary oxidation step, the secondary oxygen
Change step and form silicon oxide layer thin on polysilicon gate material layer side wall, is on the one hand used to repair polysilicon gate forming process
In caused by polysilicon gate dielectric layer damage, on the other hand can be used as follow-up clearance wall forming process intermediate gap wall with it is more
Buffer layer between polysilicon gate.The polysilicon gate secondary oxidation step is using the method for thermal oxide in polysilicon gate side
Thin silicon dioxide layer is formed on wall and semiconductor substrate.The technique of the polysilicon gate secondary oxidation is people in the art
Technique known to member, then this repeats no more.
Illustratively, it is also formed with isolation structure 404 in the semiconductor substrate.It is formed on the semiconductor substrate
The method of isolation structure uses：First, patterned semiconductor substrate is to form groove；Then, isolated material is filled in the trench,
The isolated material can be the oxide material of any insulation such as silica；Then, it executes chemical mechanical grinding and removes groove
Outer oxide material.The method for forming isolation structure can be any method well-known to those skilled in the art,
This is repeated no more.
It is to be appreciated that the semiconductor substrate with isolation structure as example the present invention will be described not
It is to limit the invention, any semiconductor substrate with gate structure is suitable for the present invention.
Then, step S302 is executed：Well region ion implanting step is executed, to form well region in the semiconductor substrate.
In general, will have NMOS transistor and PMOS simultaneously after the completion of the full-flow process of a semiconductor crystal wafer
Transistor, NMOS transistor are formed in P type trap zone, and PMOS transistor is formed in N-type well region.Herein, only with wherein one
The formation flow of type transistor npn npn illustrates for example.Illustratively, using the forming process of NMOS transistor as example into
Row explanation.
Illustratively, the well region ion implanting step includes：Mask film covering layer on the semiconductor substrate；Patterning
The mask layer, to expose the region of ion trap to be formed；Well region ion implantation technology is executed, on the semiconductor substrate
Form ion trap.The mask film covering layer and the process for patterning the mask layer are common photoresist layer in semiconductor technology
And photoetching process, details are not described herein.
As shown in Figure 4 B, after executing well region ion implanting step, well region 405 is formed in the semiconductor substrate 400.Show
Example property, in NMOS device, the well region ion implanting injects boron ion, in the semiconductor substrate formed p-type from
Sub- trap.In the pmos devices, the well region ion implanting injects phosphonium ion, to form N-type ion in the semiconductor substrate
Trap.
The ion implanting implemented in the well region ion implanting step is using the smaller energetic ion injection in inclination angle, example
Property, the ion implanting uses ranging from 0~7 ° of inclination angle, and the energy of the ion implanting is 50~150keV.It is described
Ion implanting is divided into two parts according to the region of injection：It is directly injected into the first ion implanting part of substrate；Pass through gate structure
Inject the second ion implanting part of substrate.It is described be directly injected into substrate the first ion implanting part generate in the prior art
The ion well region of same depth；Second ion implanting to semiconductor substrate by gate structure partly because carry out ion note
Enter so that shallower ion well region is formed below the gate structure, and this shallower ion well region can be used as adjusting thresholds
Ion implanted region further adjusts threshold voltage of semiconductor device.For this angle, channel threshold tune has further been omitted
Whole ion implantation process step.This also further reduced semiconductor technology cost.For well region ion implanting, use
Ion implantation dosage it is relatively low thus smaller to the damage of gate dielectric.
Then, S303 is executed：Pouch-type and/or LDD ion implanting steps are executed, to form bag in the semiconductor substrate
Type area and/or source drain extension area.
The pouch-type ion implanting to form pouch-type injection region and source drain extension area on a semiconductor substrate, to change
Semiconductor substrate local doping concentrations can avoid when channel region doping concentration is constant due to the reduction of dimensions of semiconductor devices, bring
Source/drain region perforation and so that device is lost gate control.The LDD ion implantings step is formed in the semiconductor substrate to be lightly doped
Source/drain region, on the one hand inhibit thermoelectronic effect, on the other hand provide diffusing buffer layer for the source drain doping of high concentration.
During actual process, according to different device performance requirements, often occur by pouch-type ion implanting and LDD from
Son injection separately or concurrently uses.It is only illustrated herein using LDD ion implantings as example, it is to be understood that this implementation
Example is illustrated using LDD ion implantings as example, is not intended to limit the invention, any execution pouch-type ion implanting
And/or LDD ion implanting steps, the technique to form pouch-type and/or source drain extension area in the semiconductor substrate are applicable in
In the present invention.
As shown in Figure 4 C, LDD ion implantation technologies are executed in the semiconductor substrate 400, in semiconductor substrate 400
In, the both sides of the polysilicon structure 401 form source drain extension area 406.Illustratively, the LDD ion implantation technologies, in P
Arsenic ion is injected in trap, to form source drain extension area in the p-well；Boron ion is injected in N traps, with the shape in the N traps
At source drain extension area.The LDD ion implantation technologies use the ion implantation technology with larger inclination angle, illustratively, institute
It is usually 10~30 ° to state angle of inclination.In this course, still keep mask layer in well region ion implantation technology constant, complete
At LDD ion implantation technologies are executed after well region ion implanting, this need not carry out photoetching to semiconductor substrate again in the process,
I.e. under same etching condition, ion implanting twice is completed, effectively reduces the number of photoetching process, reduces processing step, is saved
The dosage of photoresist mask, while the number that removes photoresist is reduced, it is further reduced processing step, saves production cost.
Illustratively, further include executing pouch-type after completing well region ion implanting, before executing LDD ion implantings
(pocket) the step of ion implanting.Pouch-type ion implanting uses the ion implantation technology with big inclination angle, forms pouch-type
(pocket) ion implanted region, change local doping concentrations, illustratively, bag area ion implanting use with the well region from
Son injects identical ionic type.In the present embodiment, NMOS transistor is formed, using the bag area ion implanting of injection boron ion
It is doped.Shown pouch-type ion implantation technology, using the ion implantation technology in the pouch-type area formed in state of the art,
Details are not described herein.
Illustratively, further include the step to form source/drain after completing well region and forming the formation with source/drain extension area
Suddenly.
Illustratively, further include forming the step of clearance wall in the gate structure both sides before forming the source/drain
Suddenly.The clearance wall is by the raceway groove immediately below heavy doping source/drain and polysilicon gate, to inhibit thermoelectronic effect.Such as Fig. 4 D
It is shown, form clearance wall 407 in 401 both sides of gate structure.Silicon nitride, silica or silicon oxynitride etc. can be used in the clearance wall
Dielectric material.Illustratively, using silicon nitride material.The step of forming the clearance wall include：First, it is served as a contrast in the semiconductor
It is co-deposited on bottom and forms silicon nitride layer；Then, patterned mask layer is formed on the silicon nitride layer；Then, with the figure
The mask layer of case is mask, and the silicon nitride layer is etched using plasma etching industrial, with expose the semiconductor substrate and
Polysilicon gate forms clearance wall structure 407 as shown in 4D.It can be this field to form the technique of how many clearance wall and method
Any technique known to technical staff and method, details are not described herein.
After forming clearance wall, source/drain region ion implanting is executed, to form source/drain region.As shown in Figure 4 E, source/drain is executed
After area's ion implantation technology, source/drain region 408 is formed in semiconductor substrate 400.The source/drain region ion implanting of shown execution
It is consistent with the ionic type for the ion implantation technology injection that above-mentioned formation source drain extension area carries out that technique injects ionic type.Institute
The technique that ion implantation technology is well known to those skilled in the art is stated, details are not described herein.
So far, the introduction of the committed step of the manufacturing method of the semiconductor devices of the embodiment of the present invention is completed.In addition to upper
It states except step, the manufacturing method of the present invention can also include other steps, for example, after forming source drain extension area, be formed
Further include that embedded carbon silicon layer and embedded germanium silicon layer are respectively formed in the semiconductor substrate of grid both sides before clearance wall,
These steps can realize that details are not described herein again by various techniques in the prior art.
The semiconductor devices obtained according to the method for the present invention has half consistent with semiconductor is obtained in the prior art
Conductor performance, showing the semiconductor devices that method using the present invention obtains such as Fig. 5 A and 5B and obtaining 6V in the prior art
The current transfer characteristic correlation curve of NIO devices, wherein 5A are grid current transfer characteristic curve, and 5B is that drain current transfer is special
Linearity curve.It can be seen from the figure that the semiconductor devices that (dotted line is shown) of the invention obtains with the prior art (solid line is shown)
Current transfer characteristic is almost the same.
In conclusion the manufacturing method of semiconductor device according to the invention, by well region ion implantation technology in grid shape
At rear execution, sequentially carried out under same etching condition with pouch-type ion implanting and/or LDD ion implantation technologies, to complete trap
The forming process of area's forming process and pouch-type area and/or source drain extension area, on the one hand, the use to mask is reduced, to reduce
Production cost；On the other hand, the processing step of semiconductor manufacturing is effectively reduced, technology stability is increased.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate is provided, is formed with gate structure on the semiconductor substrate；
Well region ion implanting step is executed, to form well region in the semiconductor substrate；
Pouch-type and/or LDD ion implanting steps are executed, to form pouch-type area and/or source drain extension in the semiconductor substrate
Area.
2. the method as described in claim 1, which is characterized in that the well region ion implanting step includes：
Mask layer is formed on the semiconductor substrate；
The mask layer is patterned to form area to be implanted；
Well region ion implantation technology is executed, to form well region in the semiconductor substrate.
3. method as claimed in claim 2, which is characterized in that the pouch-type and/or LDD ion implanting steps include, in institute
After stating well region ion implantation technology, pouch-type and/or LDD ion implantation technologies are executed in the area to be implanted.
4. the method as described in claim 1, which is characterized in that the gate structure is the lamination of gate oxide and polysilicon layer
Structure.
5. method as claimed in claim 4, which is characterized in that the method further include execute well region ion implanting step it
Before the step of reoxidizing the polysilicon layer.
6. the method as described in claim 1, which is characterized in that the method further includes executing pouch-type and/or LDD ions note
Enter the source drain ion injection step executed after step, to form source/drain in the semiconductor substrate.
7. method as claimed in claim 6, which is characterized in that before forming the source/drain further include in the grid
Structure both sides form the step of clearance wall.
8. the method as described in claim 1, which is characterized in that the semiconductor devices includes NMOS or PMOS.
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| US20070004159A1 (en) * | 2005-06-29 | 2007-01-04 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device using gate-through ion implantation |
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Application publication date: 20181009 |