CN108615686B - Manufacturing method of chip packaging structure and substrate structure - Google Patents
Manufacturing method of chip packaging structure and substrate structure Download PDFInfo
- Publication number
- CN108615686B CN108615686B CN201710146934.XA CN201710146934A CN108615686B CN 108615686 B CN108615686 B CN 108615686B CN 201710146934 A CN201710146934 A CN 201710146934A CN 108615686 B CN108615686 B CN 108615686B
- Authority
- CN
- China
- Prior art keywords
- groove
- solder mask
- breaking
- mask layer
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 13
- 230000000149 penetrating effect Effects 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 100
- 229910000679 solder Inorganic materials 0.000 claims description 63
- 239000012792 core layer Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 7
- 239000000084 colloidal system Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 5
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000008393 encapsulating agent Substances 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 27
- 238000005530 etching Methods 0.000 description 5
- 238000003698 laser cutting Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229920000728 polyester Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a manufacturing method of a chip packaging structure and a substrate structure. First, a carrier is provided, and the carrier includes a substrate and a release film connected to the substrate. And then, forming a laminated structure layer on the release film, and patterning the laminated structure to form a pre-breaking groove penetrating at least part of the laminated structure, wherein the pre-breaking groove is positioned at the edge of the laminated structure and divides the laminated structure into a chip setting part and a pre-breaking part. Then, a chip is placed on the chip placing portion. Then, an encapsulant is formed on the chip mounting portion and covers the chip. And then, disconnecting the pre-breaking part and the chip setting part along the pre-breaking groove, and removing the release film and the substrate through the pre-breaking part. The invention not only can improve the convenience of the manufacturing process, but also can avoid damaging the chip packaging structure when the carrier plate is removed so as to improve the yield of the manufacturing process.
Description
Technical Field
The present invention relates to a method for manufacturing a package structure and a substrate structure, and more particularly, to a method for manufacturing a chip package structure and a substrate structure.
Background
At present, after the chip package structure is fabricated on the flexible carrier, the flexible carrier needs to be further removed to obtain the chip package structure. Because the chip package structure and the flexible carrier are bonded to each other through the release film, and the adhesion force of the release film is not high, the chip package structure and the flexible carrier can be separated after a proper acting force is applied to the release film. Since the release film is sandwiched between the chip package structure and the flexible carrier and the area where the chip and the circuit are located is not damaged, the point of application is usually close to the side edge of the chip package structure and/or the flexible carrier. Generally, the periphery of the chip package structure is flush with the periphery of the flexible carrier, which is not favorable for applying force and may cause damage to the chip package structure if careless.
Disclosure of Invention
The invention provides a manufacturing method of a chip packaging structure and a substrate structure, which can improve the convenience and yield in the manufacturing process.
The invention provides a manufacturing method of a chip packaging structure, which comprises the following steps. First, a carrier is provided, and the carrier includes a substrate and a release film connected to the substrate. And then, forming a laminated structure layer on the release film, and patterning the laminated structure to form a pre-breaking groove penetrating at least part of the laminated structure, wherein the pre-breaking groove is positioned at the edge of the laminated structure and divides the laminated structure into a chip setting part and a pre-breaking part. Then, a chip is placed on the chip placing portion. Then, an encapsulant is formed on the chip mounting portion and covers the chip. And then, disconnecting the pre-breaking part and the chip setting part along the pre-breaking groove, and removing the release film and the substrate through the pre-breaking part.
The invention provides a substrate structure, which comprises a carrier plate and a laminated structure. The carrier plate comprises a substrate and a release film connected with the substrate. The laminated structure is arranged on the release film, wherein the laminated structure is provided with a pre-breaking groove, the pre-breaking groove is positioned at the edge of the laminated structure, and the laminated structure is divided into a chip arrangement part and a pre-breaking part.
Based on the above, in the process of forming the laminated structure on the carrier to fabricate the substrate structure, the invention forms the pre-cut trench penetrating through at least a portion of the laminated structure. Therefore, after the chip packaging structure is manufactured, the carrier plate can be removed through the pre-breaking groove. Therefore, the manufacturing method of the chip package structure and the substrate structure provided by the invention not only can improve the convenience in the manufacturing process, but also can avoid the damage to the chip package structure when the carrier plate is removed so as to improve the yield in the manufacturing process.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a manufacturing process of a chip package structure according to a first embodiment of the invention;
FIGS. 2A and 2B are schematic top views of two embodiments of the substrate structure of FIG. 1C, respectively;
fig. 3A to 3F are schematic cross-sectional views illustrating a manufacturing process of a chip package structure according to a second embodiment of the invention;
FIGS. 4A and 4B are schematic top views of two embodiments of the substrate structure of FIG. 3D, respectively;
fig. 5 is a schematic cross-sectional view of a substrate structure packaged with a plurality of chips according to a third embodiment of the invention.
Description of reference numerals:
100. 200: chip packaging structure
101. 101a, 201: substrate structure
102. 202: pre-breaking groove
110. 210: support plate
111. 211: base material
112. 212, and (3): release film
112a, 212 a: upper surface of
112b, 212 b: lower surface
120. 220, and (2) a step of: laminated structure
121. 221: first solder mask layer
121a, 222 a: first trench
122. 222: conductive layer
122a, 223 a: second trench
123. 223: second solder mask
123 a: third groove
125. 225: chip setting part
126. 226: pre-breaking part
127. 227: the first side edge
128. 129, 228, 229: second side edge
130. 230: chip and method for manufacturing the same
140. 240: packaging colloid
224: core layer
225 a: the first part
226 a: the second part
Detailed Description
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a manufacturing process of a chip package structure according to a first embodiment of the invention. Referring to fig. 1A, first, a carrier 110 is provided, wherein the carrier 110 includes a substrate 111 and a release film 112 connected to the substrate 111, and the substrate 111 may be a flexible substrate made of Polyester (PET), Polyimide (PI), or the like, for temporary carrying. However, the material of the substrate is not limited in the present invention, and in other embodiments, the substrate may be a hard substrate. In the present embodiment, the release film 112 can be a thin film having an upper surface 112a and a lower surface 112b both having adhesive properties, wherein the lower surface 112b of the release film 112 is attached to the substrate 111, and the upper surface 112a of the release film 112 is exposed to the outside for the subsequent bonding of the stacked structure 120 (shown in fig. 1C).
Next, a first solder mask layer 121 is formed on the upper surface 112a of the release film 112. After the first solder mask layer 121 is adhered to the release film 112, the first solder mask layer 121 may be patterned by stamping, etching, or laser cutting, so as to form a first groove 121a penetrating through the first solder mask layer 121, and the first groove 121a exposes the upper surface 112a of the release film 112. Referring to fig. 1B, a conductive layer 122 is formed on the first solder mask layer 121, wherein the conductive layer 122 may be made of copper, other conductive metals or alloys, and the conductive layer 122 may be patterned by stamping, etching or laser cutting, so as to form a second trench 122a penetrating through the conductive layer 122. In the present embodiment, the second trench 122a is aligned with the first trench 121 a. Referring to fig. 1C, a second solder mask layer 123 is formed on the conductive layer 122, and the second solder mask layer 123 is patterned by stamping, etching or laser cutting to form a third trench 123a penetrating through the second solder mask layer 123, wherein the third trench 123a is aligned with the second trench 122 a. To this end, the substrate structure 101 is completed, wherein the first trench 121a, the second trench 122a and the third trench 123a aligned with each other form the pre-breaking trench 102, and the stacked structure 120 formed by the first solder mask layer 121, the conductive layer 122 and the second solder mask layer 123 is penetrated by the pre-breaking trench 102 to expose the upper surface 112a of the release film 112.
In the present embodiment, the pre-breaking trench 102 is located at the edge of the stacked structure 120, and divides the stacked structure 120 into a chip setting portion 125 and a pre-breaking portion 126. Fig. 2A and 2B are schematic top views of two embodiments of the substrate structure of fig. 1C, respectively. Referring to fig. 2A, in an implementation aspect, the stacked structure 120 has a first side 127 and a second side 128 connected to the first side 127, wherein the pre-breaking groove 102 extends from the first side 127 to the second side 128 and is inclined to the first side 127 and the second side 128. The pre-breaking groove 102 has two opposite ends, and the two ends are respectively spaced from the first side 127 and the second side 128. In other embodiments, the two opposite ends of the pre-breaking groove may penetrate the first side and the second side, respectively. Referring to fig. 2B, in another embodiment, the stacked structure 120 has a first side 127 and a second side 129 parallel to the first side 127, wherein the precut groove 102 extends from the first side 127 to the second side 129 and is perpendicular to the first side 127 and the second side 129. The pre-breaking groove 102 has two opposite ends, and the two ends are respectively spaced from the first side 127 and the second side 129.
Referring to fig. 1D, next, the second solder mask layer 123 is disposed on the chip disposing portion 125 of the chip 130, for example, although not shown in the figure, the patterned second solder mask layer 123 may have a plurality of openings to expose a portion of the patterned conductive layer 122, so that the chip 130 may be electrically connected to the patterned conductive layer 122 by wire bonding or flip chip bonding. Next, the encapsulant 140 is formed on the second solder mask layer 123 on the chip mounting portion 125, and covers the chip 130. It is to be noted that, although the embodiment is described with only a single chip, the invention is not limited thereto. In other embodiments, a plurality of chips may be disposed on the chip disposing portion, and the encapsulant collectively encapsulates the plurality of chips.
Referring to fig. 1D and fig. 1E, in the present embodiment, the pre-breaking portion 126 includes a portion of the first solder mask layer 121, a portion of the conductive layer 122 and a portion of the second solder mask layer 123, and finally, the pre-breaking portion 126 is used as a force applying point to break the pre-breaking portion 126 and the chip disposing portion 125 along the pre-breaking groove 102, so that the pre-breaking portion 126, the release film 112 and the substrate 111 are removed simultaneously to separate the chip package structure 100 from the carrier substrate 110. Since the pre-breaking portion 126 can be used as a force application point for removing the carrier 110, the process convenience can be improved, and the chip package structure 100 can be prevented from being damaged when the carrier 110 is removed, thereby improving the process yield.
Fig. 3A to 3F are schematic cross-sectional views illustrating a manufacturing process of a chip package structure according to a second embodiment of the invention. Referring to fig. 3A, first, a carrier 210 is provided, wherein the carrier 210 includes a substrate 211 and a release film 212 connected to the substrate 211, and the substrate 211 may be a flexible substrate made of Polyester (PET), Polyimide (PI), or the like. However, the material of the substrate is not limited in the present invention, and in other embodiments, the substrate may be a hard substrate. In the present embodiment, the release film 212 may be a thin film having an upper surface 212a and a lower surface 212b both having adhesive properties, wherein the lower surface 212b of the release film 212 is attached to the substrate 211, and the upper surface 212a of the release film 212 is exposed to the outside for the subsequent bonding of the stacked structure 220 (shown in fig. 3D).
Next, a first solder mask layer 221 is formed on the upper surface 212a of the release film 212. After the first solder mask layer 221 is adhered to the release film 212, the core layer 224 is disposed on the first solder mask layer 221. Referring to fig. 3C, a conductive layer 222 is formed on the core layer 224, wherein the conductive layer 222 may be made of copper, other conductive metals or alloys, and the conductive layer 222 may be patterned by stamping, etching or laser cutting, so as to form a first trench 222a penetrating through the conductive layer 222, and the core layer 224 is exposed by the first trench 222 a. Referring to fig. 3D, a second solder mask layer 223 is formed on the conductive layer 222, and the second solder mask layer 223 is patterned by stamping, etching or laser cutting to form a second trench 223a penetrating the second solder mask layer 223, wherein the second trench 223a is aligned with the first trench 222 a. To this end, the substrate structure 201 is completed, wherein the first trench 222a and the second trench 223a aligned with each other form the pre-cut trench 202, and the first solder mask layer 221, the core layer 224, the conductive layer 222 and the second solder mask layer 223 form the stacked structure 220. In addition, the conductive layer 222 and the second solder mask 223 are penetrated by the pre-breaking groove 202 to expose the core layer 224.
In the present embodiment, the pre-breaking groove 202 is located at the edge of the stacked structure 220, and divides the stacked structure 220 into a chip setting portion 225 and a pre-breaking portion 226. Fig. 4A and 4B are schematic top views of two embodiments of the substrate structure of fig. 3D, respectively. Referring to fig. 4A, in an implementation aspect, the stacked structure 220 has a first side 227 and a second side 228 connected to the first side 227, wherein the pre-breaking groove 202 extends from the first side 227 to the second side 228 and is inclined to the first side 227 and the second side 228. The pre-breaking groove 202 has two opposite ends, and the two ends are respectively spaced from the first side 227 and the second side 228. In other embodiments, the two opposite ends of the pre-breaking groove may penetrate the first side and the second side, respectively.
Referring to fig. 4B, in another implementation aspect, the stacked structure 220 has a first side 227 and a second side 229 parallel to the first side 227, wherein the precut groove 202 extends from the first side 227 to the second side 229 and is perpendicular to the first side 227 and the second side 229. The pre-breaking groove 202 has two opposite ends, and the two ends are respectively spaced from the first side 227 and the second side 229. In other embodiments, the two opposite ends of the pre-breaking groove may penetrate the first side and the second side, respectively.
Referring to fig. 3E, next, the second solder mask 223 is disposed on the chip disposing portion 225 of the chip 230, for example, although not shown in the figure, the patterned second solder mask 223 may have a plurality of openings to expose a portion of the patterned conductive layer 222, so that the chip 230 may be electrically connected to the patterned conductive layer 222 by wire bonding or flip chip bonding. Next, the encapsulant 240 is formed on the second solder mask 223 on the chip mounting portion 225, and covers the chip 230.
Referring to fig. 3E and 3F, in the present embodiment, the pre-breaking portion 226 includes a portion of the conductive layer 222 and a portion of the second solder mask layer 223, and the pre-breaking groove 202 divides the first solder mask layer 221 and the core layer 224 into a first portion 225a overlapping the chip disposing portion 225 and a second portion 226a overlapping the pre-breaking portion 226. Finally, the pre-breaking portion 226 is used as a force applying point, the pre-breaking portion 226 and the chip disposing portion 225 are disconnected along the pre-breaking groove 202, the first portion 225a and the second portion 226a are disconnected, and the pre-breaking portion 226, the second portion 226a, the release film 212 and the substrate 211 are removed simultaneously, so that the chip package structure 200 is separated from the carrier 210. Since the pre-breaking portion 226 can be used as a force application point for removing the carrier 210, the process convenience can be improved, and the chip package structure 200 can be prevented from being damaged when the carrier 210 is removed, thereby improving the process yield. In the present embodiment, the depth of the pre-breaking groove 202 is such that the core layer 224 is exposed. In other embodiments, the precut groove may further penetrate through the core layer or the core layer and the corresponding first solder mask layer, which are aspects of the present invention.
Fig. 5 is a schematic cross-sectional view of a substrate structure packaged with a plurality of chips according to a third embodiment of the invention. Referring to fig. 5, a substrate structure 101a is substantially similar to the substrate structure 101 of the first embodiment, but the substrate structure 101a has a longer length so as to dispose a plurality of chips 130 thereon. In detail, although not shown in the figure, the second solder mask layer 123 of the chips 130 disposed on the chip disposing portion 125 may have a plurality of openings to expose a portion of the patterned conductive layer 122, so that the chips 130 may be electrically connected to the patterned conductive layer 122 by wire bonding or flip chip bonding. Next, the encapsulant 140 is formed on the second solder mask layer 123 on the chip mounting portion 125 to encapsulate the chips 130. Finally, the pre-breaking portion 126 is used as a force application point to break the pre-breaking portion 126 and the chip setting portion 125 along the pre-breaking groove 102, so that the pre-breaking portion 126, the release film 112 and the substrate 111 are removed simultaneously. Similarly, the substrate structure 201 of the second embodiment may also be increased in size to package a plurality of chips 230 thereon.
In summary, in the process of forming the stacked structure on the carrier to fabricate the substrate structure, the invention forms the pre-breaking groove penetrating through at least a portion of the stacked structure to divide the stacked structure into the chip setting portion and the pre-breaking portion. Therefore, after the chip packaging structure is manufactured, the pre-breaking part and the chip setting part can be disconnected along the pre-breaking groove, and the carrier plate is removed through the pre-breaking part. Therefore, the manufacturing method of the chip package structure and the substrate structure provided by the invention not only can improve the convenience in the manufacturing process, but also can avoid the damage to the chip package structure when the carrier plate is removed so as to improve the yield in the manufacturing process.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (20)
1. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a carrier plate, wherein the carrier plate comprises a base material and a release film connected with the base material;
forming a lamination structure layer on the release film, and patterning the lamination structure to form a pre-breaking groove penetrating through at least part of the lamination structure, wherein the pre-breaking groove is positioned at the edge of the lamination structure and divides the lamination structure into a chip setting part and a pre-breaking part;
arranging a chip on the chip arranging part;
forming a packaging colloid on the chip arrangement part and coating the chip, wherein the vertical projection of the packaging colloid on the laminated structure is not overlapped with the pre-breaking part; and
and disconnecting the pre-breaking part and the chip setting part along the pre-breaking groove, and removing the release film and the substrate through the pre-breaking part.
2. The method of claim 1, wherein the step of forming the stacked structure on the release film and patterning the stacked structure to form the pre-cut trench penetrating at least a portion of the stacked structure comprises:
forming a first solder mask layer on the release film, and patterning the first solder mask layer to form a first groove penetrating through the first solder mask layer, wherein the first groove is exposed out of the release film;
forming a conductive layer on the first solder mask layer, and patterning the conductive layer to form a second trench penetrating through the conductive layer, wherein the second trench is aligned with the first trench; and
and forming a second solder mask layer on the conductive layer, and patterning the second solder mask layer to form a third groove penetrating through the second solder mask layer, wherein the third groove is aligned with the second groove, and the pre-breaking groove is composed of the first groove, the second groove and the third groove.
3. The method of claim 2, wherein the pre-cut portion comprises a portion of the first solder mask layer, a portion of the conductive layer, and a portion of the second solder mask layer.
4. The method of claim 1, wherein the step of forming the stacked structure on the release film and patterning the stacked structure to form the pre-cut trench penetrating at least a portion of the stacked structure comprises:
forming a first solder mask layer on the release film;
arranging a core layer on the first solder mask layer;
forming a conductive layer on the core layer, and patterning the conductive layer to form a first trench penetrating through the conductive layer, wherein the core layer is exposed by the first trench; and
and forming a second solder mask layer on the conductive layer, and patterning the second solder mask layer to form a second groove penetrating through the second solder mask layer, wherein the second groove is aligned with the first groove, and the pre-breaking groove is composed of the first groove and the second groove.
5. The method for manufacturing a chip package structure according to claim 4, wherein the pre-breaking portion comprises a portion of the conductive layer and a portion of the second solder mask layer.
6. The method of manufacturing a chip package structure according to claim 4, wherein the pre-breaking groove divides the first solder mask layer and the core layer into a first portion overlapping with the chip disposing portion and a second portion overlapping with the pre-breaking portion, and when the pre-breaking portion and the chip disposing portion are separated along the pre-breaking groove and the release film and the substrate are removed by the pre-breaking portion, the first portion and the second portion are separated, so that the second portion is removed along with the release film and the substrate.
7. The method of claim 1, wherein the step of forming the pre-break trench through at least a portion of the stacked structure comprises extending the pre-break trench from a first side of the stacked structure to a second side connected to the first side.
8. The method of claim 7, wherein the pre-breaking groove has two opposite ends, and the two ends are spaced apart from the first side and the second side, respectively.
9. The method of claim 1, wherein the step of forming the pre-breaking groove through at least a portion of the stacked structure comprises extending the pre-breaking groove from a first side of the stacked structure to a second side parallel to the first side.
10. The method of claim 9, wherein the pre-breaking groove has two opposite ends, and the two ends are spaced apart from the first side and the second side, respectively.
11. A substrate structure, comprising:
the carrier plate comprises a base material and a release film connected with the base material; and
the laminated structure is arranged on the release film, wherein part of the laminated structure is provided with a pre-breaking groove, the pre-breaking groove is positioned at the edge of the laminated structure, and the laminated structure is divided into a chip arranging part and a pre-breaking part.
12. The substrate structure of claim 11, wherein the laminate structure comprises:
the first solder mask layer is arranged on the release film, wherein the first solder mask layer is provided with a first groove, and the first groove is exposed out of the release film;
a conductive layer disposed on the first solder mask layer, wherein the conductive layer has a second trench aligned with the first trench; and
and the second solder mask layer is arranged on the conducting layer, wherein the second solder mask layer is provided with a third groove, the third groove is aligned with the second groove, and the pre-breaking groove consists of the first groove, the second groove and the third groove.
13. The substrate structure of claim 12, wherein the pre-cut portion comprises a portion of the first solder mask layer, a portion of the conductive layer, and a portion of the second solder mask layer.
14. The substrate structure of claim 11, wherein the laminate structure comprises:
the first solder mask layer is arranged on the release film;
a core layer disposed on the first solder mask layer;
a conductive layer disposed on the core layer, wherein the conductive layer has a first trench exposing the core layer; and
and the second solder mask layer is arranged on the conducting layer, wherein the second solder mask layer is provided with a second groove, the second groove is aligned with the first groove, and the pre-breaking groove is formed by the first groove and the second groove.
15. The substrate structure of claim 14, wherein the pre-cut portion comprises a portion of the conductive layer and a portion of the second solder mask layer.
16. The substrate structure according to claim 14, wherein the pre-breaking groove divides the first solder mask layer and the core layer into a first portion overlapping with the chip placement portion and a second portion overlapping with the pre-breaking portion.
17. The substrate structure of claim 11, wherein the laminated structure has a first side and a second side connected to the first side, and the pre-break groove extends from the first side to the second side.
18. The substrate structure of claim 17, wherein the pre-break trench has opposite ends, and the two ends are spaced apart from the first side and the second side, respectively.
19. The substrate structure of claim 11, wherein the stacked structure has a first side and a second side parallel to the first side, and the pre-break groove extends from the first side to the second side.
20. The substrate structure of claim 18, wherein the pre-break trench has opposite ends, and the two ends are spaced apart from the first side and the second side, respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105141151A TWI621231B (en) | 2016-12-13 | 2016-12-13 | Manufacturing method of chip package structure and substrate structure |
| TW105141151 | 2016-12-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108615686A CN108615686A (en) | 2018-10-02 |
| CN108615686B true CN108615686B (en) | 2020-06-09 |
Family
ID=62640142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710146934.XA Active CN108615686B (en) | 2016-12-13 | 2017-03-13 | Manufacturing method of chip packaging structure and substrate structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108615686B (en) |
| TW (1) | TWI621231B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1461050A (en) * | 2002-05-24 | 2003-12-10 | 富士通株式会社 | Semiconductor device and its mfg. method |
| CN102083282A (en) * | 2009-11-27 | 2011-06-01 | 富葵精密组件(深圳)有限公司 | Method for manufacturing printed circuit board (PCB) |
| CN102945790A (en) * | 2012-02-08 | 2013-02-27 | 日月光半导体制造股份有限公司 | Carrier joint and separation technology of semiconductor wafer |
| CN106057787A (en) * | 2015-04-17 | 2016-10-26 | 台湾积体电路制造股份有限公司 | Discrete polymer in fan-out packages |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011501473A (en) * | 2007-10-26 | 2011-01-06 | イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニー | Multilayer chip carrier and manufacturing method |
| CN103632979B (en) * | 2012-08-27 | 2017-04-19 | 碁鼎科技秦皇岛有限公司 | Chip packaging substrate and structure, and manufacturing methods thereof |
| US9559005B2 (en) * | 2014-01-24 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of packaging and dicing semiconductor devices and structures thereof |
-
2016
- 2016-12-13 TW TW105141151A patent/TWI621231B/en active
-
2017
- 2017-03-13 CN CN201710146934.XA patent/CN108615686B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1461050A (en) * | 2002-05-24 | 2003-12-10 | 富士通株式会社 | Semiconductor device and its mfg. method |
| CN102083282A (en) * | 2009-11-27 | 2011-06-01 | 富葵精密组件(深圳)有限公司 | Method for manufacturing printed circuit board (PCB) |
| CN102945790A (en) * | 2012-02-08 | 2013-02-27 | 日月光半导体制造股份有限公司 | Carrier joint and separation technology of semiconductor wafer |
| CN106057787A (en) * | 2015-04-17 | 2016-10-26 | 台湾积体电路制造股份有限公司 | Discrete polymer in fan-out packages |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201822326A (en) | 2018-06-16 |
| TWI621231B (en) | 2018-04-11 |
| CN108615686A (en) | 2018-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9852973B2 (en) | Manufacturing method of chip package and package substrate | |
| KR102143653B1 (en) | Semiconductor package with EMI shielding and fabricating method for the same | |
| US10297552B2 (en) | Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects | |
| TW201011872A (en) | Package substrate having semiconductor component embedded therein and fabrication method thereof | |
| TW201036055A (en) | Semiconductor process | |
| CN103296011A (en) | Semiconductor packaging body with electromagnetic interference shielding effect, and manufacture method thereof | |
| KR102600106B1 (en) | Method of manufacturing semiconductor packages | |
| US9607860B2 (en) | Electronic package structure and fabrication method thereof | |
| JP5036409B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN108695269A (en) | Semiconductor device packages and its manufacturing method | |
| TWI266375B (en) | Semiconductor device and manufacture method thereof | |
| CN107546186B (en) | Substrate, semiconductor packages and its manufacturing method comprising substrate | |
| US20100252921A1 (en) | Semiconductor device and manufacturing method of the same | |
| US20100029047A1 (en) | Method of fabricating printed circuit board having semiconductor components embedded therein | |
| US9478472B2 (en) | Substrate components for packaging IC chips and electronic device packages of the same | |
| CN107342233A (en) | Low loss component flush type antenna packages structure and its manufacture method | |
| KR20160093248A (en) | Semiconductor package and fabrication method of the same | |
| KR100346899B1 (en) | A Semiconductor device and a method of making the same | |
| CN108615686B (en) | Manufacturing method of chip packaging structure and substrate structure | |
| JP4357278B2 (en) | Integrated circuit die fabrication method | |
| CN108172561B (en) | Bearing substrate, packaging structure thereof and manufacturing method of semiconductor packaging element | |
| JP5620437B2 (en) | Semiconductor device | |
| US6429534B1 (en) | Interposer tape for semiconductor package | |
| US20120104609A1 (en) | Discrete circuit component having copper block electrodes and method of fabrication | |
| CN109411450A (en) | Semiconductor encapsulation device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |