CN108615686A - Manufacturing method of chip packaging structure and substrate structure - Google Patents
Manufacturing method of chip packaging structure and substrate structure Download PDFInfo
- Publication number
- CN108615686A CN108615686A CN201710146934.XA CN201710146934A CN108615686A CN 108615686 A CN108615686 A CN 108615686A CN 201710146934 A CN201710146934 A CN 201710146934A CN 108615686 A CN108615686 A CN 108615686A
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- Prior art keywords
- groove
- layer
- chip
- prejudge
- laminated construction
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims description 106
- 238000010276 construction Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 34
- 239000012792 core layer Substances 0.000 claims description 18
- 239000000084 colloidal system Substances 0.000 claims description 7
- 238000012856 packing Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 abstract description 9
- 239000008393 encapsulating agent Substances 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 238000004080 punching Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229920000728 polyester Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a manufacturing method of a chip packaging structure and a substrate structure. First, a carrier is provided, and the carrier includes a substrate and a release film connected to the substrate. And then, forming a laminated structure layer on the release film, and patterning the laminated structure to form a pre-breaking groove penetrating at least part of the laminated structure, wherein the pre-breaking groove is positioned at the edge of the laminated structure and divides the laminated structure into a chip setting part and a pre-breaking part. Then, a chip is placed on the chip placing portion. Then, an encapsulant is formed on the chip mounting portion and covers the chip. And then, disconnecting the pre-breaking part and the chip setting part along the pre-breaking groove, and removing the release film and the substrate through the pre-breaking part. The invention not only can improve the convenience of the manufacturing process, but also can avoid damaging the chip packaging structure when the carrier plate is removed so as to improve the yield of the manufacturing process.
Description
Technical field
The present invention relates to a kind of production method of encapsulating structure and board structure more particularly to a kind of chip-packaging structures
Production method and board structure.
Background technology
Currently, after the chip-packaging structure that completes on flexible support plate, need further to remove flexible support plate, with
Obtain chip-packaging structure.Since chip-packaging structure is to be engaged with each other by release film with flexible support plate, and release film
Adhesion is not high, therefore in the active force for applying appropriateness after release film, just can make chip-packaging structure and flexible support plate
It separates.Since release film is folded between chip-packaging structure and flexible support plate, and to avoid undermining chip and circuit
Region, therefore the point of application is generally proximal to the lateral margin of chip-packaging structure and/or flexible support plate.In general, chip
The periphery of encapsulating structure flushes the periphery of flexible support plate, therefore is unfavorable for exerting a force, and one have accidentally can be to chip package knot
It is configured to damage.
Invention content
The present invention provides a kind of production method and board structure of chip-packaging structure, can improve convenience on processing procedure with
Yield.
The present invention proposes a kind of production method of chip-packaging structure, includes the following steps.First, support plate is provided, and is carried
Plate includes base material and the release film that connect base material.Then, laminated structural layers are formed on release film, and pattern laminated construction,
Groove is prejudged through at least partly laminated construction to be formed, wherein prejudge the edge that groove is located at laminated construction, and by lamination
Structure is divided into chip setting unit and prejudges portion.Then, setting chip is in chip setting unit.Then, formed packing colloid in
In chip setting unit, and coating chip.Later, edge prejudges groove disconnection and prejudges portion and chip setting unit, and is moved by prejudging portion
Except release film and base material.
The present invention proposes a kind of board structure comprising support plate and laminated construction.Support plate includes base material and connect base material
Release film.Laminated construction is set on release film, and wherein laminated construction, which has, prejudges groove, prejudges groove and is located at laminated construction
Edge, and laminated construction is divided into and chip setting unit and prejudges portion.
Based on above-mentioned, forming laminated construction during on support plate to produce board structure, the present invention is in lamination
Structure is formed through its and at least part of prejudges groove.It whereby, can be by prejudging ditch after chip-packaging structure completes
Slot removes support plate.Therefore, the production method of chip-packaging structure proposed by the invention can not only improve system with board structure
Convenience in journey is also avoided that when removing support plate and causes to damage to improve the yield on processing procedure to chip-packaging structure.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate shown attached drawing
It is described in detail below.
Description of the drawings
Figure 1A to Fig. 1 E is the diagrammatic cross-section of the manufacturing process of the chip-packaging structure of first embodiment of the invention；
Fig. 2A and Fig. 2 B are the schematic top plan view of two state sample implementations of the board structure of Fig. 1 C respectively；
Fig. 3 A to Fig. 3 F are the diagrammatic cross-sections of the manufacturing process of the chip-packaging structure of second embodiment of the invention；
Fig. 4 A and Fig. 4 B are the schematic top plan view of two state sample implementations of the board structure of Fig. 3 D respectively；
Fig. 5 is the diagrammatic cross-section that the board structure of third embodiment of the invention is packaged with multiple chips.
Reference sign：
100、200：Chip-packaging structure
101、101a、201：Board structure
102、202：Prejudge groove
110、210：Support plate
111、211：Base material
112、212：Release film
112a、212a：Upper surface
112b、212b：Lower surface
120、220：Laminated construction
121、221：First soldermask layer
121a、222a：First groove
122、222：Conductive layer
122a、223a：Second groove
123、223：Second soldermask layer
123a：Third groove
125、225：Chip setting unit
126、226：Prejudge portion
127、227：First side
128、129、228、229：Second side
130、230：Chip
140、240：Packing colloid
224：Core layer
225a：First part
226a：Second part
Specific implementation mode
Figure 1A to Fig. 1 E is the diagrammatic cross-section of the manufacturing process of the chip-packaging structure of first embodiment of the invention.It please join
Figure 1A is examined, first, provides support plate 110, wherein support plate 110 includes base material 111 and the release film 112 that connect base material 111, and base material
111 can be with the flexible substrate made by the materials such as polyester (PET) or polyimide (PI), to as temporary carrying.
However, the present invention is not limited the material of base material, in other embodiments, base material can be hard substrate.In this implementation
In example, release film 112 can be upper surface 112a and lower surface the 112b all film with stickiness, the wherein following table of release film 112
Face 112b is attached at base material 111, and the upper surface 112a of release film 112 is exposed to outside, for subsequently binding laminated construction 120
(being shown in Fig. 1 C) is used.
Then, the first soldermask layer 121 is formed on the upper surface 112a of release film 112.Stick making the first soldermask layer 121
After release film 112, it the modes such as can cut by punching press, etching or laser and pattern the first soldermask layer 121, to be formed through the
The first groove 121a of one soldermask layer 121, and first groove 121a exposes the upper surface 112a of release film 112.Please refer to figure
1B then forms conductive layer 122 on the first soldermask layer 121, wherein the material of conductive layer 122 can be copper, other conductive metals
Or alloy, and can be by the modes such as punching press, etching or laser cutting patterned conductive layer 122, to be formed through conductive layer 122
Second groove 122a.In the present embodiment, second groove 122a and first groove 121a is aligned.Please refer to Fig.1 C, later, shape
At the second soldermask layer 123 on conductive layer 122, and it the modes such as can cut by punching press, etching or laser to pattern second anti-welding
Layer 123, to form the third groove 123a through the second soldermask layer 123, and third groove 123a is opposite with second groove 122a
It is accurate.So far, board structure 101 has completed, wherein first groove 121a aligned with each other, second groove 122a and third
Groove 123a compositions prejudge groove 102, and be made of the first soldermask layer 121, conductive layer 122 and the second soldermask layer 123
Laminated construction 120 is run through and is exposed the upper surface 112a of release film 112 by groove 102 is prejudged.
In the present embodiment, prejudge the edge that groove 102 is located at laminated construction 120, and laminated construction 120 is divided into core
Piece setting unit 125 and prejudge portion 126.Fig. 2A and Fig. 2 B are that the vertical view of two state sample implementations of the board structure of Fig. 1 C is illustrated respectively
Figure.Please refer to Fig.2 A, in one state sample implementation, laminated construction 120 have first side 127 and with 127 phase of first side
The second side 128 of connection wherein prejudge groove 102 extends to second side 128 from first side 127, and favours first
Side 127 and second side 128.Prejudging groove 102 has an ends, and both ends respectively with first side 127 and the
Dual side-edge 128 is kept at a distance.In other embodiments, first side and second can be penetrated through respectively by prejudging the ends of groove
Side.Please refer to Fig.2 B, in another state sample implementation, laminated construction 120 have first side 127 and with first side 127
Second side 129 parallel each other, wherein prejudge groove 102 extends to second side 129 from first side 127, and perpendicular to
First side 127 and second side 129.Prejudge groove 102 have ends, and both ends respectively with first side 127
And second side 129 is kept at a distance.
D is please referred to Fig.1, then, setting chip 130 is in the second soldermask layer 123 in chip setting unit 125, for example,
Although not illustrated in diagram, the second soldermask layer 123 after only patterning can have multiple openings to expose the conduction after patterning
The part of layer 122, therefore chip 130 can be engaged by routing or the modes such as chip bonding are electrically connected at the conduction after patterning
Layer 122.Then, packing colloid 140 is formed in the second soldermask layer 123 in chip setting unit 125, and coating chip 130.Especially
Illustrate, although the present embodiment is only lifted single chips and is explained, but not limited to this.In other embodiments, can make multiple
Chip is set in chip setting unit, and packing colloid is made to coat aforesaid plurality of chip jointly.
D and Fig. 1 E are please referred to Fig.1, in the present embodiment, it includes the first soldermask layer of part 121, partially electronically conductive to prejudge portion 126
Layer 122 and the second soldermask layer of part 123, finally, to prejudge, portion 126 is the point of application and edge prejudges the disconnection of groove 102 and prejudges portion
126 with chip setting unit 125, it is removed simultaneously to make to prejudge portion 126, release film 112 and base material 111, so that chip package knot
Structure 100 is detached with support plate 110.The point of application that can be used as removal support plate 110 due to prejudging portion 126, can not only improve processing procedure
On convenience, be also avoided that when removing support plate 110 chip-packaging structure 100 is caused to damage it is good on processing procedure to improve
Rate.
Fig. 3 A to Fig. 3 F are the diagrammatic cross-sections of the manufacturing process of the chip-packaging structure of second embodiment of the invention.It please join
Fig. 3 A are examined, first, provide support plate 210, wherein support plate 210 includes base material 211 and the release film 212 that connect base material 211, and base material
211 can be with the flexible substrate made by the materials such as polyester (PET) or polyimide (PI).However, the present invention is for base material
Material is not limited, and in other embodiments, base material can be hard substrate.In the present embodiment, release film 212 can be upper table
Face 212a and lower surface the 212b all film with stickiness, the lower surface 212b of wherein release film 212 are attached at base material 211, and
It is used for subsequently binding laminated construction 220 (being shown in Fig. 3 D) outside the upper surface 212a of release film 212 is exposed to.
Then, the first soldermask layer 221 is formed on the upper surface 212a of release film 212.Stick making the first soldermask layer 221
After release film 212, setting core layer 224 is on the first soldermask layer 221.Please refer to Fig.3 C, then, formed conductive layer 222 in
In core layer 224, wherein the material of conductive layer 222 can be copper, other conductive metals or alloy, and can by punching press, etching or
The modes patterned conductive layers 222 such as laser cutting, to form the first groove 222a through conductive layer 222, and first groove
222a exposes core layer 224.D is please referred to Fig.3, later, forms the second soldermask layer 223 on conductive layer 222, and punching can be passed through
The modes such as pressure, etching or laser cutting pattern the second soldermask layer 223, to form the second groove through the second soldermask layer 223
223a, and second groove 223a and first groove 222a is aligned.So far, board structure 201 has completed, wherein right each other
Accurate first groove 222a and second groove 223a compositions prejudge groove 202, and by the first soldermask layer 221, core layer 224, lead
Electric layer 222 and the second soldermask layer 223 form laminated construction 220.In addition, conductive layer 222 and the second soldermask layer 223 are prejudged ditch
Slot 202 runs through and exposes core layer 224.
In the present embodiment, prejudge the edge that groove 202 is located at laminated construction 220, and laminated construction 220 is divided into core
Piece setting unit 225 and prejudge portion 226.Fig. 4 A and Fig. 4 B are that the vertical view of two state sample implementations of the board structure of Fig. 3 D is illustrated respectively
Figure.Please refer to Fig.4 A, in one state sample implementation, laminated construction 220 have first side 227 and with 227 phase of first side
The second side 228 of connection wherein prejudge groove 202 extends to second side 228 from first side 227, and favours first
Side 227 and second side 228.Prejudging groove 202 has an ends, and both ends respectively with first side 227 and the
Dual side-edge 228 is kept at a distance.In other embodiments, first side and second can be penetrated through respectively by prejudging the ends of groove
Side.
B is please referred to Fig.4, in another state sample implementation, laminated construction 220 has first side 227 and and first side
227 second sides 229 parallel each other, wherein prejudge groove 202 extends to second side 229 from first side 227, and it is vertical
In first side 227 and second side 229.Prejudge groove 202 have ends, and both ends respectively with first side
227 and second side 229 keep at a distance.In other embodiments, the first side can be penetrated through respectively by prejudging the ends of groove
Side and second side.
E is please referred to Fig.3, then, setting chip 230 is in the second soldermask layer 223 in chip setting unit 225, for example,
Although not illustrated in diagram, the second soldermask layer 223 after only patterning can have multiple openings to expose the conduction after patterning
The part of layer 222, therefore chip 230 can be engaged by routing or the modes such as chip bonding are electrically connected at the conduction after patterning
Layer 222.Then, packing colloid 240 is formed in the second soldermask layer 223 in chip setting unit 225, and coating chip 230.
E and Fig. 3 F are please referred to Fig.3, in the present embodiment, it includes that partial electroconductive layer 222 and part second are anti-to prejudge portion 226
Layer 223, and prejudge groove 202 first soldermask layer 221 is divided into core layer 224 it is equitant with chip setting unit 225
First part 225a and with prejudge 226 equitant second part 226a of portion.Finally, it is the point of application and edge to prejudge portion 226
Prejudge the disconnection of groove 202 and prejudge portion 226 and chip setting unit 225, and disconnect first part 225a and second part 226a, makes
Prejudge portion 226, second part 226a, release film 212 and base material 211 while being removed, so that chip-packaging structure 200 and load
Plate 210 detaches.The point of application that can be used as removal support plate 210 due to prejudging portion 226, can not only improve the facility on processing procedure
Property, it is also avoided that when removing support plate 210 and chip-packaging structure 200 is caused to damage to improve the yield on processing procedure.In this reality
It applies in example, the depth for prejudging groove 202 is to expose core layer 224.In other embodiments, prejudging groove can further run through
Core layer runs through core layer and corresponding first soldermask layer, and above-mentioned is all the enforceable aspect of the present invention.
Fig. 5 is the diagrammatic cross-section that the board structure of third embodiment of the invention is packaged with multiple chips.Referring to FIG. 5,
Board structure 101a and the board structure of first embodiment 101 are substantially similar, and only the length of board structure 101a is longer, in order to
Multiple chips 130 are set thereon.Specifically, these chips 130 are set to the second soldermask layer in chip setting unit 125
123, for example, although not illustrated in diagram, the second soldermask layer 123 after only patterning can have multiple openings to expose figure
The part of conductive layer 122 after case, therefore these chips 130 can be engaged by routing or the modes such as chip bonding are electrically connected
Conductive layer 122 after patterning.Then, packing colloid 140 is formed in the second soldermask layer 123 in chip setting unit 125, with
Coat these chips 130.Finally, it is the point of application to prejudge portion 126 and prejudges portion 126 along the disconnection of groove 102 is prejudged and set with chip
Portion 125 is set, make to prejudge portion 126, release film 112 and base material 111 while being removed.Similarly, the substrate knot of second embodiment
The size of structure 201 can also increase, and encapsulate multiple chips 230 on it.
In conclusion forming laminated construction during on support plate to produce board structure, the present invention is in lamination
Structure be formed through its it is at least part of prejudge groove, laminated construction is divided into and chip setting unit and prejudges portion.Whereby,
After chip-packaging structure completes, portion and chip setting unit can be prejudged along groove disconnection is prejudged, and will by prejudging portion's shifting
Support plate removes.Therefore, the production method of chip-packaging structure proposed by the invention can not only improve on processing procedure with board structure
Convenience, be also avoided that when removing support plate and chip-packaging structure caused to damage to improve the yield on processing procedure.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Technical staff, without departing from the spirit and scope of the present invention, when can make a little change with retouching, but these change and retouching
It should all be within the scope of the present invention.
Claims (20)
1. a kind of production method of chip-packaging structure, which is characterized in that including：
Support plate is provided, and the support plate includes base material and the release film that connect the base material；
Laminated structural layers are formed on the release film, and pattern the laminated construction, to be formed through at least partly described
Laminated construction prejudges groove, wherein described prejudge the edge that groove is located at the laminated construction, and the laminated construction is drawn
It is divided into chip setting unit and prejudges portion；
Chip is set in the chip setting unit；
Packing colloid is formed in the chip setting unit, and coats the chip；And
Prejudge described in groove disconnect described in prejudge portion and the chip setting unit, and to prejudge portion's removal described release by described
Film and the base material.
2. the production method of chip-packaging structure according to claim 1, which is characterized in that formed the laminated construction in
On the release film, and the laminated construction is patterned, prejudges ditch described in at least partly described laminated construction to be formed to run through
The step of slot includes：
The first soldermask layer is formed on the release film, and patterns first soldermask layer, it is anti-through described first to be formed
The first groove of layer, and the first groove exposes the release film；
Conductive layer is formed on first soldermask layer, and patterns the conductive layer, to form the through the conductive layer
Two grooves, and the second groove is aligned with the first groove；And
The second soldermask layer is formed on the conductive layer, and patterns second soldermask layer, it is anti-through described second to be formed
The third groove of layer, and the third groove is aligned with the second groove, it is described prejudge groove by the first groove,
The second groove and the third groove are formed.
3. the production method of chip-packaging structure according to claim 2, which is characterized in that described to prejudge portion include part
First soldermask layer, the part conductive layer and part second soldermask layer.
4. the production method of chip-packaging structure according to claim 1, which is characterized in that formed the laminated construction in
On the release film, and the laminated construction is patterned, prejudges ditch described in at least partly described laminated construction to be formed to run through
The step of slot includes：
The first soldermask layer is formed on the release film；
Core layer is set on first soldermask layer；
Conductive layer is formed in the core layer, and patterns the conductive layer, to form the first ditch through the conductive layer
Slot, and the first groove exposes the core layer；And
The second soldermask layer is formed on the conductive layer, and patterns second soldermask layer, it is anti-through described second to be formed
The second groove of layer, and the second groove is aligned with the first groove, it is described to prejudge groove by the first groove
It is formed with the second groove.
5. the production method of chip-packaging structure according to claim 4, which is characterized in that described to prejudge portion include part
The conductive layer and part second soldermask layer.
6. the production method of chip-packaging structure according to claim 4, which is characterized in that it is described prejudge groove will be described
First soldermask layer is divided into the equitant first part of the chip setting unit with the core layer and prejudges portion with described
Equitant second part, when along it is described prejudge groove disconnect described in prejudge portion and the chip setting unit, and by described pre-
When disconnected portion removes the release film with the base material, the first part is disconnected with the second part, makes described second
Divide and is removed with the release film and the base material.
7. the production method of chip-packaging structure according to claim 1, which is characterized in that formed through at least partly institute
The described the step of prejudging groove for stating laminated construction includes making described to prejudge groove and from the first side of the laminated construction extend
To the second side being connected with the first side.
8. the production method of chip-packaging structure according to claim 7, which is characterized in that described to prejudge groove with phase
To both ends, and the both ends are kept at a distance with the first side and the second side respectively.
9. the production method of chip-packaging structure according to claim 1, which is characterized in that formed through at least partly institute
The described the step of prejudging groove for stating laminated construction includes making described to prejudge groove and from the first side of the laminated construction extend
To the second side parallel each other with the first side.
10. the production method of chip-packaging structure according to claim 9, which is characterized in that described to prejudge groove and have
Ends, and the both ends are kept at a distance with the first side and the second side respectively.
11. a kind of board structure, which is characterized in that including：
Support plate, including base material and the release film that connect the base material；And
Laminated construction is set on the release film, described to prejudge groove and be located at wherein the laminated construction, which has, prejudges groove
The edge of the laminated construction, and the laminated construction is divided into chip setting unit and prejudges portion.
12. board structure according to claim 11, which is characterized in that the laminated construction includes：
First soldermask layer is set on the release film, wherein first soldermask layer has first groove, and first ditch
Slot exposes the release film；
Conductive layer is set on first soldermask layer, wherein the conductive layer have second groove, and the second groove with
The first groove aligns；And
Second soldermask layer is set on the conductive layer, wherein second soldermask layer has third groove, the third groove
It is aligned with the second groove, and described prejudges groove by the first groove, the second groove and the third ditch
Slot is formed.
13. board structure according to claim 12, which is characterized in that described to prejudge portion include that part described first is anti-welding
Layer, the part conductive layer and part second soldermask layer.
14. board structure according to claim 11, which is characterized in that the laminated construction includes：
First soldermask layer is set on the release film；
Core layer is set on first soldermask layer；
Conductive layer is set in the core layer, wherein the conductive layer has first groove, and the first groove exposes
The core layer；And
Second soldermask layer is set on the conductive layer, wherein second soldermask layer has second groove, the second groove
It is aligned with the first groove, and described prejudge groove and be made of the first groove and the second groove.
15. board structure according to claim 14, which is characterized in that it is described prejudge portion include the part conductive layer with
Part second soldermask layer.
16. board structure according to claim 14, which is characterized in that it is described prejudge groove by first soldermask layer with
The core layer is divided into the equitant first part of the chip setting unit and prejudges portion equitant second with described
Part.
17. board structure according to claim 11, which is characterized in that the laminated construction have first side and with
The second side that the first side is connected, and described prejudge groove and extend to the second side from the first side.
18. board structure according to claim 17, which is characterized in that it is described to prejudge groove with ends, and
It keeps at a distance respectively with the first side and the second side at the both ends.
19. board structure according to claim 11, which is characterized in that the laminated construction have first side and with
First side second side parallel each other, and described prejudge groove and extend to the second side from the first side
Side.
20. board structure according to claim 18, which is characterized in that it is described to prejudge groove with ends, and
It keeps at a distance respectively with the first side and the second side at the both ends.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105141151 | 2016-12-13 | ||
| TW105141151A TWI621231B (en) | 2016-12-13 | 2016-12-13 | Manufacturing method of chip package structure and substrate structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108615686A true CN108615686A (en) | 2018-10-02 |
| CN108615686B CN108615686B (en) | 2020-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710146934.XA Active CN108615686B (en) | 2016-12-13 | 2017-03-13 | Manufacturing method of chip packaging structure and substrate structure |
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| TW (1) | TWI621231B (en) |
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| US8163381B2 (en) * | 2007-10-26 | 2012-04-24 | E. I. Du Pont De Nemours And Company | Multi-layer chip carrier and process for making |
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| CN1461050A (en) * | 2002-05-24 | 2003-12-10 | 富士通株式会社 | Semiconductor device and its mfg. method |
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Also Published As
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| CN108615686B (en) | 2020-06-09 |
| TWI621231B (en) | 2018-04-11 |
| TW201822326A (en) | 2018-06-16 |
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