CN108614751A - A kind of method of PCIE winding self-test - Google Patents

Abstract

The present invention relates to a kind of PCIE winding self-test survey technologies based on UVM platforms, it is characterised in that：It is connected by the primary module of bus interface bridge and from module by Signal Matching module, Signal Matching module realizes primary module by the sequential of change primary module and the output signal from module and from the self-test of module, is sent to the read-write requests packet of application layer and completes to wrap to be sent to from the read-write requests packet of module and completion as application layer primary module and wrap.

Description

A kind of method of PCIE winding self-test

Technical field

The method of the present invention relates to a kind of PCIE winding self-tests based on UVM platforms, and in particular to UVM verification platforms with And the connectivity problem of principal and subordinate's block of PCIE bridges.

Background technology

Bus interface (AXI) bridge of existing PCIE is not involved with wherein main (master) module and from (slave) module The problem of being connected.Existing PCIE is also not involved with verifies PCIE modules using UVM verification platforms.

Application layer is to being completed by the slave modules of AXI bridges when PCIE transmission datas.Use driver Simulation application layer sends the relevant signal of memory write request, such as write address, writes data etc., be sent to AXI bridges Slave modules, the XADM modules that then slave modules are re-send in PCIE package, and are sent by the transmitting terminal of PCIE It goes out.Finally, the monitor in out_agent is monitored mac layers of output port, when monitor from application layer send out When the memory write request packet to come over, monitor components parse the data bit of our needs by being parsed to the packet, Address bit etc. will be write in the memory that data are stored in monitor then by these signals.Meanwhile monitor meetings Driver is notified to send a relevant message of completing to mac layers of input terminal.It is sent to application finally by slave modules Layer is collected by monitor to be monitored.

When application layer sends memory read request packet, likewise, driver2 meeting simulation application layers, send storage The relevant signal of device read request, such as address is read, type of data packet reads mark etc. signal, then packages by PCIE, It retransmits away, when the monitor monitorings in out_agent receive the packet, it is parsed, it is found that the packet is One read request packet, then, the reading information parsed (such as reading address etc.) can be sent in MEM and read number by monitor According to, and by the data notification read out to driver, then completion of the driver groups unification with data, which is wrapped, is sent to mac layers Input terminal.It is sent to application layer finally by slave modules, is collected by monitor2 to be monitored.Existing technical side Case needs multiple excitation generators, needs multiple data collectors, and component requirement is more, and utilization rate is relatively low, is not that hair is every Kind TLP packets can all use various components.Correspondingly, in many testcase, component be idle.Also, it is right The requirement of verification platform is high, and the contact of various components is relatively more, it is easy to bug is generated in platform.

Invention content

The side of the purpose of the present invention is to overcome the above shortcomings and to provide a kind of PCIE winding self-tests based on UVM platforms Method reduces the component in UVM platforms, improves the utilization rate of each component of UVM platforms, reduces the generation of platform bug.The present invention's What purpose was realized in：A method of the PCIE winding self-tests based on UVM platforms, by Signal Matching module by AXI Master the and slave modules of bridge connect, and to realize the self-test of master and slave, master is sent to application The read-write requests packet and completion packet of layer, are sent to the read-write requests packet of slave modules as application layer and complete packet.

Its further technical solution is as follows：

1) TLP packets are being write for a memory, is being sent to by the data packet for generating transaction In sequencer, then driver obtains data packet from sequencer and is sent to mac layers of receiving terminal of connection Interface completes the input to the memory write packet of mac layers of receiving terminal；

2) the LCRC detections that the packet can be Jing Guo data link layer, the ECRC detections of transaction layer and the Abnormal Packet of transaction layer Detection etc..If format, the content etc. of packet are correct, which can enter AXI bridges smoothly by three layers of PCIE Master modules；

3) after above-mentioned master modules, finally address signal, data-signal, several signals of marking signal are sent To the slave modules of AXI bridges；

4) after above-mentioned slave modules are combined signal, the transmitter module being sent in PCIE, signal is being sent It is combined in device module, the format for being combined into TLP packets is sent to the transmitting terminal of PCIE transaction layers and is added ECRC, then LCRC is added in data link layer, is sent finally by mac layers；

5) in mac layers of output end, there are one out_agent components, the monitor components in out_agent components are used Mac layer of output end is collected to monitor, and has the function of parsing TLP packets.It is that memory writes TLP packets when being resolved to the TLP packets After, it can parse write address with data are write, and then by write address and writes data and is stored in local memory.With The prior art is compared, the beneficial effects of the invention are as follows：

The present invention, will by adding a Signal Matching module between the master modules and slave modules of AXI bridges Master modules and slave modules connect, and eliminating PCIE needs the connection of application layer come the problem of being detected；Subtract significantly The component in UVM platforms is lacked, it is only necessary to which monitor and two driver just completes the transmission and monitoring of data, greatly The big utilization rate for reducing workload and each component of UVM platforms；Reduce the definition of interface, only in the mac of PCIE layers Transmission and output end define an interface, and need not then be redefined in that one end that application layer connects in PCIE interface。

Specific implementation mode

The method of the present invention relates to a kind of PCIE winding self-tests based on UVM platforms, the method is by connecing bus It the master (master) of mouthful (AXI) bridge and is connected from (slave) module, it, will to realize the self-test of master and slave Master is sent to the read-write requests packet of application layer and completes packet, and the read-write requests of slave modules are sent to as application layer Packet and completion packet.

When we to the mac layer receiving terminals of PCIE send a reading memory TLP packet when, reading address should with before The write address for writing tlp packets is consistent, can just carry out read operation in this way, and otherwise, the data of reading may be initial in memory Value.Likewise, the TLP packets can pass through the receiving terminal of PCIE, send after the detection of various data packet formats and content To receiving processing module (RADM), RADM modules are by judging that the type of data packet is re-fed into the master modules of AXI bridges, so These signals are sent to Signal Matching module signal_match_mstr by master modules afterwards, and the module is to each signal weight It is newly adjusted, is adjusted to then send these signals to AXI bridges by the slave module received signals of AXI bridges Slave modules.Slave modules send a signal to XADM modules, and the group package operation by XADM modules enters the hair of PCIE Sending end is finally output to by mac layers of output end in interface by the addition of the ECRC and LCRC of transmitting terminal.Simultaneously Monitor in out_agent can be monitored collection to the output packet in interface, collected a whole TLP packet with Afterwards, which can be parsed, the type of the packet, address and data (if with data) can be parsed.When discovery should Packet is a memory read request packet, then the data of local memory will be read according to address, then by the address It is combined into the data of reading in the driver that a transaction is sent in another individual in_agent1.Its In, it is to be connected by the port defined in UVM platforms between out_agent and in_agent1, and in out_agent Port is connected directly with the port of monitor therein, and the port in in_agent1 is straight with the port of driver therein Connect the purpose connected, the monitor in the out_agent thus reached is connected with the driver in in_agent.Work as in_ Driver in agent1 receive the data packet with address and data that the monitor in out_agent sends over Afterwards, which can parse address and data, address and data, which are then combined into completion, wraps, in other in packet Hold and defined by oneself, especially indicates the bit of the type of cpl packets.Cpl packages are closed after completing, then passes through in_ Driver in agent1 is sent to the mac layers of the receiving terminal of PCIE, the completion packet using the receiving terminal of PCIE mac layers, After data link layer (being mainly detected to LCRC), transaction layer (main ECRC detections and Abnormal Packet detection), it is sent to RADM, RADM detect that the data type of the packet is the completion packet that memory is read, then can be sent to the slave modules of AXI bridges, should Signal after parsing will be sent to Signal Matching module (signal_match_slv) by module again after Packet analyzing.Each signal After Signal Matching, the master modules that module is sent to AXI bridges can be matched.And at this point, the master modules of AXI bridges It will be considered that it is module that application layer sends over, can't report an error.Then master modules send signal to PCIE transmitting terminals XADM modules package, the output end of last mac layer of PCIE transmitting terminals again exports.And at this point, connection mac layers of output end Out_agent returns monitoring and is collected into the packet again, it is found that the packet is then the completion packet that a memory is read solves the packet Analysis parses address with after data, is compared with the data corresponding to local corresponding address, check that the completion packet exists Either with or without there is mistake during being flowed in PCIE.

Claims (2)

1. a kind of PCIE winding self-test survey technologies based on UVM platforms, it is characterised in that：By the primary module of bus interface bridge and from Module is connected by Signal Matching module, Signal Matching module by change primary module and output signal from module when Sequence realizes primary module and from the self-test of module, primary module is sent to the read-write requests packet of application layer and complete packet as Application layer is sent to read-write requests packet and completion packet from module.

2. a kind of PCIE winding self-test survey technologies based on UVM platforms according to claim 1, it is characterised in that the method Include the following steps：

1) TLP packets are being write for a memory, is defining packet module by the way that the data packet of generation to be sent in sequencer, then Driver obtains the interface that data packet is sent to connection physical layer receiving terminal from sequencer, completes to physical layer receiving terminal The input of memory write packet；

2) cyclic redundancy check that the packet can be Jing Guo data link layer, the cyclic redundancy check of transaction layer and transaction layer it is abnormal Shape packet detects；

3) after primary module, then address data signal is sent to Signal Matching module, Signal Matching module can make address Signal is sent to prior to data-signal a cycle from module, and then data-signal and data flag signal are sent to bus interface The slave module of bridge；

4) after module is combined signal, the transmitter being sent in PCIE, signal is combined in transmitter, group The transmitting terminal that the format of synthesis TLP packets is sent to PCIE transaction layers is added cyclic redundancy check, then in data link layer Cyclic redundancy check is added, is sent finally by physical layer；

5) in the output end of physical layer there are one output agent component, the data monitoring device assembly in output agent component is used for supervising Survey collect physical layer output end, and have the function of parse TLP packets, when be resolved to the TLP packets for memory write TLP packets with Afterwards, it can parse write address with data are write, and then be stored in data in local memory.