CN108598164A - GaN-based enhanced power electronic device and manufacturing method thereof - Google Patents

GaN-based enhanced power electronic device and manufacturing method thereof Download PDF

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Publication number
CN108598164A
CN108598164A CN201810471447.5A CN201810471447A CN108598164A CN 108598164 A CN108598164 A CN 108598164A CN 201810471447 A CN201810471447 A CN 201810471447A CN 108598164 A CN108598164 A CN 108598164A
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China
Prior art keywords
barrier layer
gan
layer
electronic device
power electronic
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CN201810471447.5A
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Chinese (zh)
Inventor
刘新宇
黄森
王鑫华
康玄武
魏珂
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201810471447.5A priority Critical patent/CN108598164A/en
Publication of CN108598164A publication Critical patent/CN108598164A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A GaN-based enhancement type power electronic device and a manufacturing method thereof are provided, the electronic device comprises a substrate, a GaN epitaxial layer, a back barrier layer, a GaN channel layer and a barrier layer from bottom to top in sequence, a source electrode, a grid electrode and a drain electrode are formed on the barrier layer, and a passivation layer is deposited on the barrier layer among the source electrode, the grid electrode and the drain electrode; wherein the back barrier layer and barrier layer are independently selected from AlGaN, AlInN, or AlInGaN. The invention can obviously improve the threshold voltage of the GaN-based enhanced device and improve the yield and the threshold uniformity of the large-size enhanced GaN-based power electronic device.

Description

A kind of GaN base enhanced power electronic device and preparation method thereof
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of GaN base enhanced power electronic device and its making Method.
Background technology
Enhanced is the core requirement of power electronic device trouble free service.There are mainly four types of technologies to realize in the world at present AlGaN/GaN base enhancement devices:1) the groove etched thinned AlGaN potential barrier of grid;2) it is injected in AlGaN potential barrier electronegative Fluorine ion;3) P- (Al) GaN cap layers are grown in potential barrier layer surface;4) InGaN or thickness GaN contrapolarizations are grown in potential barrier layer surface Layer.By the above technology although can realize enhanced, the threshold value of device is confined to+3V or less.In order to break through GaN base power electricity The threshold value bottleneck of sub- device expands its application in high-voltage power electronic field, there is an urgent need for by design novel enhancement type material and The threshold value of GaN base enhancement device is increased to+3V or more by device architecture.
Invention content
In order to solve the problems in the existing technology, the present invention proposes a kind of GaN base enhanced power electronic device And production method, the threshold voltage for improving GaN base enhancement device.
In order to achieve the above object, on the one hand, the present invention proposes a kind of GaN base enhanced power electronic device, under Include substrate, GaN epitaxial layer, back of the body barrier layer, GaN channel layers and barrier layer successively on and, formed on the barrier layer source, Grid and drain electrode, deposition has passivation layer on the barrier layer between the source electrode, grid and drain electrode;
The wherein described back of the body barrier layer and barrier layer are independently selected from AlGaN, AlInN or AlInGaN.
Preferably, the back of the body barrier layer is AlGaN or AlInN, and wherein Al components are fixed, and the content of Al components is situated between Between 0-100mol.%.
Preferably, the back of the body barrier layer is AlGaN or AlInN, and wherein Al components are gradually reduced or gradually from bottom to top Increase, reduced from y mol.% or be increased to x mol.%, wherein x, y is between 0-100.
Preferably, the back of the body barrier layer is AlInGaN, and Al, In and Ga components are fixed with thickness, or are gradually increased Or reduce.
Preferably, the thickness of the back of the body barrier layer is 1-1000nm.
Preferably, the thickness of the barrier layer is 0-10nm.
Preferably, the passivation layer is selected from AlN, SiO2Or SiNx.
Preferably, gate dielectric layer or no gate dielectric layer are formed between the grid and the barrier layer.On the other hand, The present invention proposes a kind of production method of GaN base enhanced power electronic device, including:
In the GaN epitaxial layer growth back of the body barrier layer of substrate;
The GaN channel layers of high-crystal quality are grown on the back of the body barrier layer;
Barrier layer is grown on the GaN channel layers;
Passivation layer is formed on the barrier layer;
The passivation layer is etched, source electrode, grid and drain electrode are then made;
Passivation layer is formed on the barrier layer between the source electrode, grid and drain electrode.
Preferably, the back of the body barrier layer uses MOCVD, MBE or HVPE methods to prepare.
Preferably, the passivation layer is prepared by MOCVD, LPCVD, PECVD or ALD.
Preferably, the production method further includes the steps that rectangular at gate dielectric layer under the gate.
Compared with prior art, using the invention has the advantages that:
1, the present invention raises the conduction bands of GaN channel layers using the reversed polarization effect of Al (In, Ga) N back of the body barrier layers, with into one Step exhausts the two-dimensional electron gas in Al (In, Ga) N/GaN hetero-junctions raceway grooves, to significantly improve the threshold of GaN base enhancement device Threshold voltage;
2, the present invention realizes the enhanced grid structure of no etching using thin potential barrier Al (In, Ga) N/GaN heterojunction structures, carries The high yield and threshold value uniformity of the enhanced GaN base power electronic device of large scale, has pushed GaN base power electronic device Application process.
Description of the drawings
Fig. 1 is the GaN base enhanced power electronic device structure schematic diagram of one embodiment of the invention;
Fig. 2 is the GaN base enhanced power electronic device structure schematic diagram of another embodiment of the present invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference Attached drawing, the present invention is described in further detail.
The invention discloses a kind of GaN base enhanced power electronic device structures for carrying on the back barrier structure with Al (In, Ga) N And production method.Production method therein includes:A thin layer Al (In, Ga) N Back are first grown in thicker GaN epitaxial layer Barrier (back of the body barrier layer), and then grows a floor height crystal quality GaN layer, finally grows the ultra-thin barrier layers of Al (In, Ga) N, To form enhanced Al (In, Ga) N/GaN heterogeneous structure materials, source electrode, gate medium, grid are finally prepared on the material structure Pole and drain electrode and passivation layer form transistor arrangement.
Al (In, Ga) N back of the body barrier layer is to use MOCVD, prepared by MBE or HVPE methods, thickness between 1nm extremely 1000nm。
It can be AlGaN or AlInN ternary alloy layers or AlInGaN quaternary alloys that Al (In, Ga) N, which carries on the back barrier layer,.
Al (In, Ga) is if N carries on the back barrier layer AlGaN ternary alloy layers, and Al components are between 0 and 100%.
Al (In, Ga) is if N carries on the back barrier layer AlGaN ternary alloy layers, and Al components can be fixed, between 0 He Some numerical value between 100%;It can also be gradually to successively decrease or increase from bottom to up, reduced from y% or be increased to x%, wherein X, y are between 0 and 100.
Al (In, Ga) is if N carries on the back barrier layer AlInN ternary alloy layers, and Al components are between 0% and 100%.
Al (In, Ga) is if N carries on the back barrier layer AlInN ternary alloy layers, and Al components can be fixed, between 0 He Some numerical value between 100%;It can also be gradually to successively decrease or increase from bottom to up, reduced from y% or be increased to x%, wherein X, y are between 0 and 100.
Al (In, Ga) if N carry on the back barrier layer AlInGaN quaternary alloy layers, Al, In, Ga components between 0 and 100% it Between, they can be fixed with thickness, can also gradually change, and can gradually increase, can also be to be gradually reduced.
Al (In, Ga) N barrier layers can be AlGaN or AlInN in barrier layer Al (In, Ga) the N/GaN heterojunction structures Ternary alloy layer or AlInGaN quaternary alloys, thickness is between 0nm to 10nm.
The passivation layer uses AlN, SiO2Or SiNxMaterial preparation, can by MOCVD, LPCVD, PECVD or Prepared by ALD growths, the passivation layer can go out highdensity positive charge in Al (In, Ga) N barrier layer spatial inductions, significantly improve Al In (In, Ga) N barrier layers/GaN hetero-junctions raceway grooves two-dimensional electron gas (i.e. between grid and source electrode, grid and drain electrode Between two-dimensional electron gas), to effectively reduce device conducting resistance.
The present invention raises the conduction band of GaN channel layers by the reversed polarization effect of Al (In, Ga) N back of the body barrier layers, with further The two-dimensional electron gas in Al (In, Ga) N back of the body barrier layer/GaN hetero-junctions raceway grooves is exhausted, to significantly improve the enhanced device of GaN base The threshold voltage of part has pushed applications of the GaN in high threshold, high-power electric and electronic system.
In one embodiment of the invention, a thin layer is first grown using MOCVD in the thicker GaN epitaxial layer 2 of substrate 1 AlInN carries on the back barrier layer 3, and thickness 100nm grows a floor height crystal quality GaN channel layers 4, most on AlInN back of the body barrier layers 3 The ultra-thin barrier layers 5 of AlGaN are grown afterwards, and thickness 5nm first passes through to form enhanced AlGaN/GaN heterogeneous structure materials LPCVD forms SiNxThen passivation layer 9 prepares source electrode 6, grid 7 and drain electrode 8 on the material structure, forms transistor arrangement, As shown in Figure 1, in figure 10 be two-dimensional electron gas.
In another embodiment, gate dielectric layer 11 is also formed between grid and barrier layer, as shown in Figure 2.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the present invention Within the scope of.

Claims (10)

1. a kind of GaN base enhanced power electronic device, which is characterized in that from bottom to top successively include substrate, GaN epitaxial layer, Carry on the back barrier layer, GaN channel layers and barrier layer, form source, grid and drain electrode on the barrier layer, the source electrode, grid and Deposition has passivation layer on the barrier layer between drain electrode;
The wherein described back of the body barrier layer and barrier layer are independently selected from AlGaN, AlInN or AlInGaN.
2. GaN base enhanced power electronic device according to claim 1, wherein the back of the body barrier layer be AlGaN or AlInN, wherein Al components are fixed, and the content of Al components is between 0-100mol.%, alternatively, Al components are from bottom to top It is gradually reduced or gradually increases, reduced from y mol.% or be increased to x mol.%, wherein x, y is between 0-100.
3. GaN base enhanced power electronic device according to claim 1, wherein the back of the body barrier layer is AIInGaN, Al, In and Ga component are fixed with thickness, or gradually increase or reduce.
4. GaN base enhanced power electronic device according to claim 1, wherein the thickness of the back of the body barrier layer is 1- 1000nm, it is preferable that the thickness of the barrier layer is 0-10nm.
5. GaN base enhanced power electronic device according to claim 1, wherein the passivation layer is selected from AlN, SiO2Or SiNx。
6. GaN base enhanced power electronic device according to claim 1, wherein the grid and the barrier layer it Between be formed with gate dielectric layer or no gate dielectric layer.
7. a kind of production method of any one of claim 1-6 GaN base enhanced power electronic devices, including:
In the GaN epitaxial layer growth back of the body barrier layer of substrate;
The GaN channel layers of high-crystal quality are grown on the back of the body barrier layer;
Barrier layer is grown on the GaN channel layers;
Passivation layer is formed on the barrier layer;
The passivation layer is etched, source electrode, grid and drain electrode are then made.
8. production method according to claim 7, wherein the back of the body barrier layer uses MOCVD, MBE or HVPE method systems It is standby.
9. production method according to claim 7, wherein the passivation layer passes through MOCVD, LPCVD, PECVD or ALD It prepares.
10. production method according to claim 7, wherein the production method further includes rectangular at grid under the gate The step of dielectric layer.
CN201810471447.5A 2018-05-17 2018-05-17 GaN-based enhanced power electronic device and manufacturing method thereof Pending CN108598164A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1599960A (en) * 2001-12-03 2005-03-23 克里公司 Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors
JP2005086102A (en) * 2003-09-10 2005-03-31 Univ Nagoya Field effect transistor and method of manufacturing field effect transistor
US20080203430A1 (en) * 2007-02-23 2008-08-28 Grigory Simin Enhancement mode insulated gate heterostructure field-effect transistor
CN101916773A (en) * 2010-07-23 2010-12-15 中国科学院上海技术物理研究所 Double-channel MOS-HEMT (Metal Oxide Semiconductor-High Electron Mobility Transistor) device and manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1599960A (en) * 2001-12-03 2005-03-23 克里公司 Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors
JP2005086102A (en) * 2003-09-10 2005-03-31 Univ Nagoya Field effect transistor and method of manufacturing field effect transistor
US20080203430A1 (en) * 2007-02-23 2008-08-28 Grigory Simin Enhancement mode insulated gate heterostructure field-effect transistor
CN101916773A (en) * 2010-07-23 2010-12-15 中国科学院上海技术物理研究所 Double-channel MOS-HEMT (Metal Oxide Semiconductor-High Electron Mobility Transistor) device and manufacturing method

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Application publication date: 20180928