CN108598092B - Array substrate manufacturing method and array substrate - Google Patents

Array substrate manufacturing method and array substrate Download PDF

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CN108598092B
CN108598092B CN201810458089.4A CN201810458089A CN108598092B CN 108598092 B CN108598092 B CN 108598092B CN 201810458089 A CN201810458089 A CN 201810458089A CN 108598092 B CN108598092 B CN 108598092B
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insulating layer
conductive
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conductive layer
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CN108598092A (en
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苏日嘎拉图
刘珊珊
李沙
钟蔚
卜华娟
彭美发
张军
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InfoVision Optoelectronics Kunshan Co Ltd
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InfoVision Optoelectronics Kunshan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

An array substrate manufacturing method and an array substrate are provided, the array substrate manufacturing method comprises the following steps: sequentially forming a first metal layer, a gate insulating layer and a semiconductor layer on a substrate; sequentially forming a first insulating layer, a protective layer, a second insulating layer and a first conducting layer, wherein through holes corresponding to the protective layer, the second insulating layer and the first conducting layer are formed, and the protective layer and the first conducting layer are sequentially annealed, or forming an auxiliary conducting part above the protective layer, wherein the auxiliary conducting part penetrates through the through holes of the protective layer to be in contact with the first insulating layer; a third insulating layer and a second conductive layer are sequentially formed. According to the array substrate manufacturing method and the array substrate, due to the fact that the through holes are formed in the second insulating layer, gas of the protective layer can be fully released and discharged through the through holes in the secondary annealing process, or the auxiliary conducting part is arranged to seal the protective layer, the gas is sealed below the auxiliary conducting part, and therefore the situation that the gas of the protective layer enters the liquid crystal layer to cause liquid crystal bubbles is avoided, and the quality of the liquid crystal display device is improved.

Description

Array substrate manufacturing method and array substrate
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate manufacturing method and an array substrate.
Background
At present, the size of a display panel and the pixel density (PPI) of a liquid crystal display are getting larger and larger, so that it is difficult to reduce the load of data lines and scanning lines when designing an array substrate.
However, the resin material is likely to have residual gas therein, and the residual gas in the resin material is released in a subsequent process, particularly under a specific condition, such as a high temperature or high humidity condition, and liquid crystal bubbles are likely to be generated in the liquid crystal layer, and the generation of the liquid crystal bubbles seriously affects the product quality.
Disclosure of Invention
The invention aims to provide an array substrate manufacturing method and an array substrate, which can avoid liquid crystal bubbles.
The embodiment of the invention provides a manufacturing method of an array substrate, which comprises the following steps:
forming a first metal layer on a substrate, forming a gate insulating layer on the substrate and covering the first metal layer, forming a semiconductor layer on the gate insulating layer, and forming a second metal layer on the gate insulating layer, the second metal layer including a source electrode, a drain electrode, and a data line, the source electrode and the drain electrode being spaced apart from each other and respectively in direct contact with the semiconductor layer to cover a portion of the semiconductor layer; sequentially forming a first insulating layer, a protective layer, a second insulating layer and a first conductive layer; the first insulating layer covers the grid insulating layer, covers the second metal layer and covers the semiconductor layer exposed between the source electrode and the drain electrode, the protective layer covers the first insulating layer, the second insulating layer covers the protective layer, and the first conducting layer is formed on the second insulating layer; wherein the content of the first and second substances,
forming via holes corresponding to the positions on the protective layer, the second insulating layer and the first conductive layer respectively, annealing the protective layer and the first conductive layer in sequence, or forming an auxiliary conductive part above the protective layer, forming a via hole on the protective layer, and annealing the first conductive layer, wherein the auxiliary conductive part covers a part above the protective layer, penetrates through the via hole of the protective layer and is in contact with the first insulating layer, and the auxiliary conductive part is positioned at the corresponding position between adjacent pixel units in the same row of the array substrate;
and forming a third insulating layer on the first conductive layer, covering the first conductive layer with the third insulating layer, and forming a second conductive layer on the third insulating layer, wherein the second conductive layer penetrates through the third insulating layer, the first conductive layer, the second insulating layer, the protective layer and the first insulating layer and is electrically connected with the drain electrode of the second metal layer.
Preferably, the first insulating layer, the protective layer, the second insulating layer and the first conductive layer are sequentially formed, the first insulating layer covers the gate insulating layer, covers the second metal layer and covers the semiconductor layer exposed between the source and the drain, the second insulating layer covers the protective layer, and the first conductive layer is formed on the second insulating layer; the method comprises the following steps of forming through holes corresponding to the protective layer, the second insulating layer and the first conductive layer respectively, and annealing the protective layer and the first conductive layer sequentially:
forming the first insulating layer on the gate insulating layer, covering the gate insulating layer, the second metal layer and the semiconductor layer exposed between the source and the drain;
forming the protective layer on the first insulating layer, exposing and developing the protective layer and the first insulating layer, and annealing the protective layer;
forming the second insulating layer on the protective layer, exposing and etching the second insulating layer, and forming a third via hole;
and forming the first conductive layer on the second insulating layer, exposing and developing the first conductive layer, etching the first conductive layer, and annealing the first conductive layer.
Preferably, the first insulating layer, the protective layer, the second insulating layer and the first conductive layer are sequentially formed, the first insulating layer covers the gate insulating layer, covers the second metal layer and covers the semiconductor layer exposed between the source and the drain, the second insulating layer covers the protective layer, and the first conductive layer is formed on the second insulating layer; the method comprises the following steps of forming through holes corresponding to the protective layer, the second insulating layer and the first conductive layer respectively, and annealing the protective layer and the first conductive layer sequentially:
forming the first insulating layer on the gate insulating layer, covering the gate insulating layer, the second metal layer and the semiconductor layer exposed between the source and the drain;
forming the protective layer on the first insulating layer, exposing and developing the protective layer and the first insulating layer, and annealing the protective layer;
forming the second insulating layer on the protective layer;
forming the first conductive layer on the second insulating layer, exposing and developing the first conductive layer while etching the first conductive layer and the second insulating layer, and then annealing the first conductive layer.
Preferably, the first insulating layer, the protective layer, the second insulating layer and the first conductive layer are sequentially formed, the first insulating layer covers the gate insulating layer, covers the second metal layer and covers the semiconductor layer exposed between the source and the drain, the second insulating layer covers the protective layer, and the first conductive layer is formed on the second insulating layer; the method comprises the following steps of forming through holes corresponding to the protective layer, the second insulating layer and the first conductive layer respectively, and annealing the protective layer and the first conductive layer sequentially:
forming the first insulating layer on the gate insulating layer, covering the gate insulating layer, the second metal layer and the semiconductor layer exposed between the source and the drain;
forming the protective layer on the first insulating layer, and annealing the protective layer;
forming the second insulating layer on the protective layer, exposing and etching the protective layer, and forming a first via hole and a third via hole on the protective layer and the second insulating layer respectively;
and forming the first conductive layer on the second insulating layer, exposing and developing the first conductive layer, and etching and annealing the first conductive layer.
Preferably, the step of forming an auxiliary conductive portion above the protection layer, forming a via hole on the protection layer, and annealing the first conductive layer, wherein the auxiliary conductive portion covers a portion above the protection layer, and the via hole penetrating through the protection layer contacts the first insulating layer, and the auxiliary conductive portion is located at a corresponding position between adjacent pixel units in the same row of the array substrate specifically includes:
forming the first insulating layer on the gate insulating layer, covering the gate insulating layer, the second metal layer and the semiconductor layer exposed between the source and the drain, and forming a hole in the first insulating layer to form a second via hole;
forming the protective layer on the first insulating layer, exposing and developing the protective layer to form a first via hole, and annealing the protective layer;
forming an auxiliary conductive layer on the protective layer, wherein the auxiliary conductive layer also passes through the second via hole and covers the first insulating layer, and meanwhile, the auxiliary conductive layer is exposed, developed and etched to form the auxiliary conductive part;
forming the second insulating layer on the auxiliary conductive layer, wherein the second insulating layer covers the auxiliary conductive layer and covers the part of the protective layer without the auxiliary conductive layer;
and forming the first conductive layer on the second insulating layer, exposing and developing the first conductive layer, etching and annealing the first conductive layer, wherein the position of the second insulating layer exposed after the first conductive layer is etched corresponds to the position of the auxiliary conductive layer.
Preferably, the step of forming an auxiliary conductive portion above the protection layer, forming a via hole on the protection layer, and annealing the first conductive layer, wherein the auxiliary conductive portion covers a portion above the protection layer, and contacts the first insulating layer through the via hole of the protection layer, and the auxiliary conductive portion is located at a corresponding position between adjacent pixel units in the same row of the array substrate specifically includes:
forming the first insulating layer on the gate insulating layer, covering the gate insulating layer, the second metal layer and the semiconductor layer exposed between the source and the drain;
forming the protective layer on the first insulating layer, exposing and developing the protective layer to form a first via hole, and annealing;
forming the second insulating layer on the protective layer, and forming a hole on the second insulating layer to form a third via hole;
and forming the first conducting layer on the second insulating layer, wherein the first conducting layer penetrates through the third through hole and the first through hole and covers the first insulating layer, exposing and developing the first conducting layer, etching and annealing the first conducting layer, forming a first part and a second part after etching the first conducting layer, the first part forms a common electrode of the array substrate, and the second part penetrates through the third through hole and the first through hole and covers the first insulating layer to form the auxiliary conducting part.
The embodiment of the invention also provides an array substrate, which comprises a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, a protective layer, an auxiliary conducting layer, a second insulating layer, a first conducting layer, a third insulating layer and a second conducting layer, wherein the first metal layer is formed on the substrate and forms a gate, the gate insulating layer covers the first metal layer, the semiconductor layer is formed on the gate insulating layer and is positioned right above the gate, the second metal layer is formed on the gate insulating layer and comprises a source electrode, a drain electrode and a data wire which are separated from each other, the source electrode and the drain electrode are respectively contacted with the semiconductor layer to cover part of the semiconductor layer, the first insulating layer covers the gate insulating layer, covers the second metal layer and covers the semiconductor layer exposed between the source electrode and the drain electrode, the protective layer is formed on the first insulating layer, the second insulating layer covers the protective layer, the first conductive layer is formed on the second insulating layer, the third insulating layer covers the first conductive layer, the second conductive layer is formed on the third insulating layer, the first conductive layer and the second conductive layer respectively form a common electrode and a pixel electrode, a plurality of pixel units are arranged in an array form on the array substrate, a pixel electrode is arranged in each pixel unit, the pixel electrode in each pixel unit is in conductive connection with the corresponding drain electrode in the pixel unit through a contact hole, it is characterized in that the protective layer does not cover the corresponding position of the pixel electrode in each pixel unit and the corresponding drain electrode conductive connection, and an auxiliary electrode part is arranged between the two pixel units in the same row, is arranged above the protective layer and penetrates through the protective layer to be in contact with the first insulating layer.
Preferably, the auxiliary conductive portion is an auxiliary electrode layer disposed on the protective layer and contacting the first insulating layer through the protective layer.
Preferably, the first conductive layer includes a first portion and a second portion separated from each other, the first portion and the second conductive layer forming a common electrode and a pixel electrode, respectively, the second portion being in contact with the first insulating layer through the second insulating layer, the protective layer to form the auxiliary conductive portion.
According to the array substrate manufacturing method and the array substrate provided by the invention, the through hole is formed on the second insulating layer, the protective layer is subjected to secondary annealing, or the auxiliary conducting part is arranged to seal the protective layer, so that the gas of the protective layer is fully released and discharged through the through hole, or the gas is sealed below the auxiliary conducting part to be prevented from entering liquid crystal, and therefore, liquid crystal bubbles caused by the fact that the gas of the protective layer enters the liquid crystal layer in the subsequent manufacturing process are avoided, and the quality of the liquid crystal display device is improved.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate manufactured by the manufacturing method of the array substrate according to the first, second and third embodiments of the present invention;
fig. 2a to fig. 2i are schematic views illustrating a method for manufacturing an array substrate according to a first embodiment of the present invention;
FIGS. 3a to 3d are schematic views illustrating a method for manufacturing an array substrate according to a second embodiment of the present invention;
FIGS. 4a to 4f are schematic views illustrating a method for manufacturing an array substrate according to a third embodiment of the present invention;
fig. 5a to 5c are schematic structural views of an array substrate manufactured by a method for manufacturing an array substrate according to a fourth embodiment of the present invention;
FIGS. 6a to 6j are schematic views illustrating a method for manufacturing an array substrate according to a fourth embodiment of the present invention;
FIGS. 7a to 7c are schematic structural views of an array substrate manufactured by a method for manufacturing an array substrate according to a fifth embodiment of the present invention;
fig. 8a to 8g are schematic views illustrating a method for manufacturing an array substrate according to a fifth embodiment of the invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the present invention will be made with reference to the accompanying drawings and examples.
As shown in fig. 1, the first, second, and third embodiments of the method for manufacturing an array substrate of the present invention are used to manufacture the array substrate shown in fig. 1, and the array substrate includes a substrate 100, a first metal layer 110, a gate insulating layer 120, a semiconductor layer 130, a second metal layer 140, a first insulating layer 150, a protective layer 160, a second insulating layer 170, a first conductive layer 180, a third insulating layer 190, and a second conductive layer 200. The first metal layer 110 is formed on the substrate 100 and forms a gate, the gate insulating layer 120 covers the first metal layer 110, and the semiconductor layer 130 is formed on the gate insulating layer 120 and the semiconductor layer 130 is located right above the gate. The semiconductor layer 130 is, for example, an amorphous silicon (a-Si) semiconductor layer, but is not limited thereto. The second metal layer 140 is formed on the gate insulating layer 120, the second metal layer 140 includes a source electrode 142, a drain electrode 144 and a data line spaced apart from each other, and the source electrode 142 and the drain electrode 144 are in contact with the semiconductor layer 130 to cover a portion of the semiconductor layer 130, in other words, a portion of the semiconductor layer 130 is exposed between the source electrode 142 and the drain electrode 144. In the present embodiment, the source electrode 142 is connected to a data line (not shown), but not limited thereto. The first insulating layer 150 covers the gate insulating layer 120, and covers the second metal layer 140 and the semiconductor layer 130 exposed between the source electrode 142 and the drain electrode 144. The protection layer 160 is formed on the first insulation layer 150, the second insulation layer 170 covers the protection layer 160, the first conductive layer 180 is formed on the second insulation layer 170, the third insulation layer 190 covers the first conductive layer 180, and the second conductive layer 200 is formed on the third insulation layer 190. The first conductive layer 180 and the second conductive layer 200 may form a common electrode and a pixel electrode, respectively. A plurality of pixel units arranged in an array are formed on the array substrate, a pixel electrode is arranged in each pixel unit, and the pixel electrode in each pixel unit is electrically connected with the corresponding drain 144 in the pixel unit through a contact hole.
First embodiment
The manufacturing method of the array substrate of the embodiment includes the following steps:
s11, as shown in fig. 2a, a first metal layer 110 is formed on the substrate 100, a gate insulating layer 120 is formed on the substrate 100, the first metal layer 110 is covered, a semiconductor layer 130 is formed on the gate insulating layer 120, and a second metal layer 140 is formed on the gate insulating layer 120. The substrate 100 is, for example, a transparent glass substrate, and the first metal layer 110 is, for example, a gate electrode. The semiconductor layer 130 is, for example, an amorphous silicon (a-Si) semiconductor layer, but is not limited thereto. The second metal layer 140 is, for example, a source electrode 142, a drain electrode 144, and a data line, and the source electrode 142 and the drain electrode 144 are spaced apart from each other and directly contact the semiconductor layer 130 to cover a portion of the semiconductor layer 130, respectively. In other words, a portion of the semiconductor layer 130 is exposed between the source electrode 142 and the drain electrode 144. In this step, the first metal layer 110, the semiconductor layer 130 and the second metal layer 140 are formed by exposure and etching.
Specifically, step S11 may include:
step S112: a first metal layer 110 is formed on the substrate 100 by a first mask process.
Step S114: a gate insulating layer 120 is formed on the substrate 100 and covers the first metal layer 110.
Step S116: the semiconductor layer 130 is formed on the gate insulating layer 120 by using a second photo-masking process, and the semiconductor layer 130 is located right above the gate of the first metal layer 110.
Step S118: after the semiconductor layer 130 is formed, a second metal layer 140 is formed on the gate insulating layer 120 by using a third photo-masking process.
S12, as shown in fig. 2b, a first insulating layer 150 is formed on the gate insulating layer 120, covering the gate insulating layer 120, the second metal layer 140 and the semiconductor layer 130 exposed between the source electrode 142 and the drain electrode 144. Specifically, the first insulating layer 150 is a film layer and is formed by a film formation method.
S13, as shown in fig. 2c, forming the protection layer 160 on the first insulating layer 150, as shown in fig. 2d, exposing and developing the protection layer 160 and the first insulating layer 150, forming a pattern on the protection layer 160, and annealing the protection layer 160. The protective layer 160 is made of a resin material, and is disposed between the second metal layer 140 and the first conductive layer to reduce capacitance therebetween, reducing loads of the data lines and the scan lines. Exposing and developing the protection layer 160 and the first insulating layer 150 may form a first via 162 and a second via 152 on the protection layer 160 and the first insulating layer 150, respectively. The temperature at which the protective layer 160 is annealed is about 230 c for about 60 minutes.
S14, as shown in fig. 2e, a second insulating layer 170 is formed on the protection layer 160, as shown in fig. 2f, the second insulating layer 170 is exposed and etched, and a third via 172 is formed. Specifically, the second insulating layer 170 is a film layer and is formed by a film formation method.
S15, as shown in fig. 2g, a first conductive layer 180 is formed on the second insulating layer 170, as shown in fig. 2h, and the first conductive layer 180 is exposed to light and developed, and the first conductive layer 180 is etched, and then the first conductive layer 180 is annealed. For example, the first conductive layer 180 is an ITO layer, and may be made of an indium tin oxide material. Etching first conductive layer 180 may form fourth via 182 on first conductive layer 180. The temperature at which first conductive layer 180 is annealed is about 250 c for about 72 minutes. The mask for exposing and etching the second insulating layer 170 and the mask for etching the first conductive layer 180 are the same mask.
S16, as shown in fig. 2i, a third insulating layer 190 is formed on the first conductive layer 180, such that the third insulating layer 190 covers the first conductive layer 180, and a second conductive layer 200 is formed on the third insulating layer 190. In this step, the second conductive layer 200 needs to be formed with a plurality of pixel electrodes arranged in an array by a method of exposure and etching or other methods, which will not be described herein. During the formation of the second conductive layer 200, the second conductive layer 200 is conductively connected to the drain 144 of the second metal layer 140 through the third insulating layer 190, the fourth via 182 of the first conductive layer 180, the third via 172 of the second insulating layer 170, the first via 162 of the protective layer 160, and the second via 152 of the first insulating layer 150. The second conductive layer 200 is made of a transparent conductive material such as Indium Tin Oxide (ITO), but not limited thereto.
In the manufacturing method of the array substrate, the third via hole 172 is formed on the second insulating layer 170, and the protective layer 160 is annealed for the second time in the annealing process of the first conductive layer 180 after the third via hole 172 is formed, so that the gas in the protective layer 160 is fully released and discharged through the fourth via hole 182, thereby avoiding liquid crystal bubbles caused by the gas in the protective layer 160 entering the liquid crystal layer in the subsequent manufacturing process, and improving the quality of the liquid crystal display device.
Second embodiment
The array substrate manufacturing steps S21 to S23 of the present embodiment are the same as those of the array substrate manufacturing steps S11 to S13 of the first embodiment, as shown in fig. 2a to 2d, and will not be described in detail herein. Compared with the manufacturing steps of the array substrate in row one, the manufacturing steps of the array substrate in this embodiment are different in that:
s24, as shown in fig. 3a, a second insulating layer 170 is formed on the protective layer 160. Specifically, the second insulating layer 170 is a film layer and is formed by a film formation method.
S25, as shown in fig. 3b, a first conductive layer 180 is formed on the second insulating layer 170, as shown in fig. 3c, the first conductive layer 180 is exposed to light and developed, and the first conductive layer 180 and the second insulating layer 170 are etched at the same time, and then the first conductive layer 180 is annealed. The first conductive layer 180 is an ITO layer, and may be made of an indium tin oxide material. Etching first conductive layer 180 and second insulating layer 170 may form fourth via 182 and third via 172 on first conductive layer 180 and second insulating layer 170, respectively. The temperature at which first conductive layer 180 is annealed is about 250 c for about 72 minutes.
S26, as shown in fig. 3d, is the same as the manufacturing step S16 of the array substrate of the first embodiment, and will not be described in detail.
In the array substrate manufacturing method, the first conductive layer 180 and the second insulating layer 170 are etched at the same time, the fourth via 182 and the third via 172 may be formed on the first conductive layer 180 and the second insulating layer 170, respectively, and then the first conductive layer 180 is annealed. In the annealing process of the first conductive layer 180, the protective layer 160 is annealed for the second time, so that the gas in the protective layer can be fully released and discharged through the fourth via hole 182, thereby avoiding the gas in the protective layer 160 from entering the liquid crystal layer in the subsequent manufacturing process to cause liquid crystal bubbles, and improving the quality of the liquid crystal display device.
Third embodiment
The array substrate manufacturing steps S31 to S32 of the present embodiment are the same as the array substrate manufacturing steps S11 to S12 of the first embodiment, as shown in fig. 2a and 2b, and will not be described in detail. The present embodiment is different from the first embodiment in that:
s33, as shown in fig. 4a, the protection layer 160 is formed on the first insulating layer 150, and the protection layer 160 is annealed. The protective layer 160 is made of a resin material, and is disposed between the second metal layer 140 and the first conductive layer to reduce capacitance therebetween, reducing loads of the data lines and the scan lines. The temperature at which the protective layer 160 is annealed is about 230 c for about 60 minutes.
S34, as shown in fig. 4b, forming a second insulating layer 170 on the protection layer 160, as shown in fig. 4c, exposing and etching the protection layer 160 and the second insulating layer 170, and forming a first via 162 and a third via 172 on the protection layer 160 and the second insulating layer 170, respectively. Specifically, the second insulating layer 170 is a film layer and is formed by a film formation method.
S35, as shown in fig. 4d, a first conductive layer 180 is formed on the second insulating layer 170, as shown in fig. 4e, and the first conductive layer 180 is exposed to light and developed, and the first conductive layer 180 is etched and annealed. For example, the first conductive layer 180 is an ITO layer, and may be made of an indium tin oxide material. Etching first conductive layer 180 may form fourth via 182 on first conductive layer 180. The temperature at which first conductive layer 180 is annealed is about 250 c for about 72 minutes.
S36, as shown in fig. 4f, compared with the step S16 of fabricating the array substrate of the first embodiment, the difference is that: before forming the second conductive layer 200, the first insulating layer 150 is etched to allow the second conductive layer 200 to pass through the first insulating layer, which is not described herein.
In the method for manufacturing the array substrate, the protective layer 160 and the second insulating layer 170 are exposed and etched to form the first via 162 and the third via 172, respectively. The first conductive layer 180 is then exposed and developed, etched to form a fourth via 182, and the first conductive layer 180 is annealed. Because the third via hole 172 is formed on the second insulating layer 170, and the protective layer 160 is annealed for the second time in the annealing process of the first conductive layer 180 after the third via hole 172 is formed, the gas in the protective layer can be fully released and discharged through the fourth via hole 182, thereby avoiding the liquid crystal bubbles caused by the gas in the protective layer 160 entering the liquid crystal layer in the subsequent manufacturing process, and improving the quality of the liquid crystal display device.
In this embodiment, since the first insulating layer 150 is not opened after the first conductive layer 180 is formed, the third conductive layer can be formed before the second conductive layer 200 is formed, in contrast, the third conductive layer cannot be formed in the first and second embodiments.
The array substrate manufacturing method of the fourth embodiment is used for manufacturing the array substrate shown in fig. 5a to 5c, and the array substrate is different from the array substrate implemented in the first embodiment in that: the second metal layer 140 includes a source electrode 142, a drain electrode 144, and a data line 146, which are spaced apart from each other, and the source electrode 142 and the drain electrode 144 are in contact with the semiconductor layer 130, respectively, to cover a portion of the semiconductor layer 130, in other words, a portion of the semiconductor layer 130 is exposed between the source electrode 142 and the drain electrode 144. In the present embodiment, the source 142 is connected to the data line 146, and the drain 144 is connected to the scan line 112, but not limited thereto. The array substrate is formed with a plurality of pixel units PX arranged in an array, each pixel unit PX is provided with a pixel electrode therein, the pixel electrode in each pixel unit PX is electrically connected to the corresponding drain 144 in the pixel unit PX through the contact hole 147, and the protective layer 160 does not cover the position where the pixel electrode in each pixel unit PX is electrically connected to the corresponding drain 144. An auxiliary electrode layer 161 is disposed between two pixel units PX in the same row, and the auxiliary electrode layer 161 is disposed on the protection layer 160 and contacts the first insulating layer 150 through the protection layer 160 to close the opening of the protection layer 160.
In the array substrate, the auxiliary conductive layer 161 covering the protective layer 160 is arranged at the position corresponding to the etched first conductive layer 180, so that the auxiliary conductive layer 161 and the first conductive layer 180 form a whole conductive layer, which can prevent the gas in the protective layer 160 from entering the liquid crystal through the second insulating layer 170, and the subsequent position where the second conductive layer 200 passes through each layer and is in conductive connection with the drain electrode 144 does not have the protective layer 160, thereby avoiding the gas in the protective layer 160 from entering the liquid crystal layer in the subsequent manufacturing process to cause liquid crystal bubbles, and improving the quality of the liquid crystal display device.
Fourth embodiment
The fabricating step S41 of the array substrate of this embodiment is the same as the fabricating step S11 of the array substrate of the first embodiment, as shown in fig. 2a, and will not be described in detail here. Compared with the manufacturing steps of the array substrate in row one, the manufacturing steps of the array substrate in this embodiment are different in that:
s42, as shown in fig. 6a, a first insulating layer 150 is formed on the gate insulating layer 120, covering the gate insulating layer 120, the second metal layer 140 and the semiconductor layer 130 exposed between the source electrode 142 and the drain electrode 144, and as shown in fig. 6b, a hole is formed in the first insulating layer 150 to form a second via hole (not shown). Specifically, the first insulating layer 150 is a film layer and is formed by a film formation method.
S43, as shown in fig. 6c, forming the protection layer 160 on the first insulating layer 150, as shown in fig. 6d, exposing and developing the protection layer 160 to form the first via 162, forming a pattern on the protection layer 160, and annealing the protection layer 160. The protective layer 160 is made of a resin material, and is disposed between the second metal layer 140 and the first conductive layer to reduce capacitance therebetween, reducing loads of the data lines and the scan lines. The temperature at which the protective layer 160 is annealed is about 230 c for about 60 minutes.
S44, as shown in fig. 6e, forming an auxiliary conductive layer 161 on the passivation layer 160, the auxiliary conductive layer 161 further passing through the first via 162 and covering the first insulating layer 150, as shown in fig. 6f, and simultaneously exposing, developing and etching the auxiliary conductive layer 161 to form a pattern.
S45, as shown in fig. 6g, a second insulating layer 170 is formed on the auxiliary conductive layer 161, and the second insulating layer 170 covers the auxiliary conductive layer 161 and the passivation layer 160. Specifically, the second insulating layer 170 is a film layer and is formed by a film formation method.
S46, as shown in fig. 6h, forming a first conductive layer 180 on the second insulating layer 170, as shown in fig. 6i, exposing and developing the first conductive layer 180, and etching and annealing the first conductive layer 180, where the second insulating layer 170 is exposed after etching the first conductive layer 180 and corresponds to the auxiliary conductive layer 161, specifically, where the second insulating layer 170 is exposed after etching the first conductive layer 180 is located between two pixel units of the array substrate and the first conductive layer 180 is not located between the two pixel units. The first conductive layer 180 is an ITO layer, and may be made of an indium tin oxide material. The temperature at which first conductive layer 180 is annealed is about 250 c for about 72 minutes.
S47, as shown in fig. 6j, a third insulating layer 190 is formed on the first conductive layer 180, such that the third insulating layer 190 covers the first conductive layer 180, and a second conductive layer 200 is formed on the third insulating layer 190. In this step, the second conductive layer 200 needs to be formed with a plurality of pixel electrodes arranged in an array by a method of exposure and etching or other methods, which will not be described herein.
In the process of forming the second conductive layer 200, the second conductive layer 200 passes through the third insulating layer 190, the first conductive layer 180, the second insulating layer 170 and the second via hole of the first insulating layer 150 to be electrically connected to the drain electrode 144 of the second metal layer 140, that is, the position where the second conductive layer 200 is electrically connected to the drain electrode 144 is not covered with the protection layer 160 (see fig. 5b), which is not described herein again.
In the manufacturing method of the array substrate, the auxiliary conductive layer 161 covering the protective layer 160 is arranged at the position corresponding to the etched first conductive layer 180, so that the auxiliary conductive layer 161 and the first conductive layer 180 form a whole conductive layer, which can prevent the gas in the protective layer 160 from entering the liquid crystal through the second insulating layer 170, and the subsequent second conductive layer 200 does not have the protective layer 160 at the position where the second conductive layer passes through each layer and is in conductive connection with the drain electrode 144, thereby avoiding the gas in the protective layer 160 from entering the liquid crystal layer to cause liquid crystal bubbles in the subsequent manufacturing process and improving the quality of the liquid crystal display device.
The array substrate manufacturing method of the fifth embodiment is used to manufacture the array substrate shown in fig. 7a to 7c, which is different from the array substrate of the fourth embodiment in that: the first conductive layer 180 includes a first portion 185 and a second portion 186 separated from each other, and the first portion 185 and the second conductive layer 200 may form a common electrode and a pixel electrode, respectively. The array substrate is formed with a plurality of pixel units PX arranged in an array, each pixel unit PX is provided with a pixel electrode therein, the pixel electrode in each pixel unit PX is electrically connected to the corresponding drain 144 in the pixel unit PX through the contact hole 147, and the protective layer 160 does not cover the corresponding position where the pixel electrode in each pixel unit PX is electrically connected to the corresponding drain 144. Moreover, a second portion 186 is disposed between two pixel units PX in the same row of the second conductive layer 200, and the second portion 186 passes through the second insulating layer 170 and the protective layer 160 to contact the first insulating layer 150 to close the opening of the protective layer 160.
In the array substrate, the position corresponding to the space between the two pixel units PX is covered by the second portion 186 of the first conductive layer 180, and the first via hole 162 of the protection layer 160 is covered, so that the gas in the protection layer 160 can be prevented from entering the liquid crystal through the second insulating layer 170, and then the subsequent second conductive layer 200 passes through the positions of the layers and the drain 144 in conductive connection without the protection layer 160, thereby preventing the gas in the protection layer 160 from entering the liquid crystal layer to cause liquid crystal bubbles in the subsequent manufacturing process, and improving the quality of the liquid crystal display device.
Fifth embodiment
The steps S51 to S52 of fabricating the array substrate are the same as those of the steps S11 to S12 of the first embodiment, and will not be described in detail. As shown in fig. 2a and 2b, the present embodiment is different from the first embodiment in that:
s53, as shown in fig. 8a, forming the protection layer 160 on the first insulating layer 150, as shown in fig. 8b, exposing and developing the protection layer 160 to form the first via 162, forming a pattern on the protection layer 160, and annealing the protection layer 160. The protective layer 160 is made of a resin material, and is disposed between the second metal layer 140 and the first conductive layer to reduce capacitance therebetween, reducing loads of the data lines and the scan lines. The temperature at which the protective layer 160 is annealed is about 230 c for about 60 minutes.
S54, as shown in fig. 8c, a second insulating layer 170 is formed on the protective layer 160, as shown in fig. 8d, and a hole is formed on the second insulating layer 170 to form a third via 172. Specifically, the second insulating layer 170 is a film layer and is formed by a film formation method.
S55, as shown in fig. 8e, forming a first conductive layer 180 on the second insulating layer 170, the first conductive layer 180 passing through the third via 172 and the first via 162 and covering the first insulating layer 150, as shown in fig. 8f, exposing and developing the first conductive layer 180, etching and annealing the first conductive layer 180, the first conductive layer 180 etching to form a first portion 185 and a second portion 186, the first portion 185 being a common electrode of the array substrate, the second portion 186 passing through the third via 172 and the first via 162 and covering the first insulating layer 150, specifically, the second portion 186 formed by etching the first conductive layer 180 is located corresponding to an area between two pixel units of the array substrate. The first conductive layer 180 is an ITO layer, and may be made of an indium tin oxide material. The temperature at which first conductive layer 180 is annealed is about 250 c for about 72 minutes.
S56, as shown in fig. 8g, a third insulating layer 190 is formed on the first conductive layer 180, such that the third insulating layer 190 covers the first conductive layer 180, and a second conductive layer 200 is formed on the third insulating layer 190. In this step, the second conductive layer 200 needs to be formed with a plurality of pixel electrodes arranged in an array by a method of exposure and etching or other methods, which will not be described herein. In the process of forming the second conductive layer 200, the second conductive layer 200 passes through the third insulating layer 190, the first conductive layer 180, the second insulating layer 170 and the first insulating layer 150 to be electrically connected to the drain 144 of the second metal layer 140, that is, the position where the second conductive layer 200 is electrically connected to the drain 144 is not covered with the protection layer 160 (see fig. 7b), which is not described herein again. The second conductive layer 200 is made of a transparent conductive material such as Indium Tin Oxide (ITO), but not limited thereto.
In the manufacturing method of the array substrate, the position corresponding to the space between the two pixel units is covered by the second part 186 of the first conductive layer 180, and the first through hole 162 of the protective layer 160 is covered, so that the gas in the protective layer 160 can be prevented from entering the liquid crystal through the second insulating layer 170, and then the subsequent second conductive layer 200 passes through the layers and is not provided with the protective layer 160 at the position in conductive connection with the drain electrode 144, so that the gas in the protective layer 160 can be prevented from entering the liquid crystal layer in the subsequent manufacturing process to cause liquid crystal bubbles, and the quality of the liquid crystal display device is improved.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. An array substrate manufacturing method comprises the following steps:
forming a first metal layer (110) on a substrate (100), forming a gate insulating layer (120) on the substrate (100) and covering the first metal layer (110), forming a semiconductor layer (130) on the gate insulating layer (120), forming a second metal layer (140) on the gate insulating layer (120), wherein the second metal layer (140) comprises a source electrode (142), a drain electrode (144) and a data line, and the source electrode (142) and the drain electrode (144) are separated from each other and respectively directly contact with the semiconductor layer (130) to cover a part of the semiconductor layer (130); sequentially forming a first insulating layer (150), a protective layer (160), a second insulating layer (170) and a first conductive layer (180); the first insulating layer (150) covers the gate insulating layer (120), covers the second metal layer (140) and covers the semiconductor layer (130) exposed between the source (142) and the drain (144), the protective layer (160) covers the first insulating layer (150), the second insulating layer (170) covers the protective layer (160), and the first conductive layer (180) is formed on the second insulating layer (170); it is characterized in that the preparation method is characterized in that,
forming a third insulating layer (190) on the first conductive layer (180), such that the third insulating layer (190) covers the first conductive layer (180), and forming a second conductive layer (200) on the third insulating layer (190), the second conductive layer (200) being conductively connected to the drain electrode (144) of the second metal layer (140) through the third insulating layer (190), the first conductive layer (180), the second insulating layer (170), the protective layer (160), and the first insulating layer (150);
in the manufacturing method of the array substrate, when the protective layer (160), the second insulating layer (170) and the first conductive layer (180) are formed, via holes corresponding to the positions of the protective layer (160), the second insulating layer (170) and the first conductive layer (180) are respectively formed, and the protective layer (160) and the first conductive layer (180) are sequentially annealed; or, when the protection layer (160), the second insulation layer (170) and the first conductive layer (180) are formed, an auxiliary conductive part is formed above the protection layer (160), a via hole is formed on the protection layer (160), and the first conductive layer (180) is annealed, the auxiliary conductive part covers a part above the protection layer (160), and contacts with the first insulation layer (150) through the via hole of the protection layer (160), and the auxiliary conductive part is located at a corresponding position between adjacent pixel units in the same row of the array substrate.
2. The method of claim 1, wherein the first insulating layer (150), the passivation layer (160), the second insulating layer (170) and the first conductive layer (180) are sequentially formed, the first insulating layer (150) covers the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source electrode (142) and the drain electrode (144), the second insulating layer (170) covers the passivation layer (160), and the first conductive layer (180) is formed on the second insulating layer (170); through holes corresponding in position are respectively formed on the protective layer (160), the second insulating layer (170) and the first conductive layer (180), and the annealing of the protective layer (160) and the first conductive layer (180) in sequence specifically comprises the following steps:
forming the first insulating layer (150) on the gate insulating layer (120), covering the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source (142) and the drain (144);
forming the protective layer (160) on the first insulating layer (150), exposing and developing the protective layer (160) and the first insulating layer (150), and annealing the protective layer (160);
forming the second insulating layer (170) on the protective layer (160), exposing and etching the second insulating layer (170), and forming a third via hole (172);
the first conductive layer (180) is formed on the second insulating layer (170), and the first conductive layer (180) is exposed and developed, and the first conductive layer (180) is etched, and then the first conductive layer (180) is annealed.
3. The method of claim 1, wherein the first insulating layer (150), the passivation layer (160), the second insulating layer (170) and the first conductive layer (180) are sequentially formed, the first insulating layer (150) covers the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source electrode (142) and the drain electrode (144), the second insulating layer (170) covers the passivation layer (160), and the first conductive layer (180) is formed on the second insulating layer (170); through holes corresponding in position are respectively formed on the protective layer (160), the second insulating layer (170) and the first conductive layer (180), and the annealing of the protective layer (160) and the first conductive layer (180) in sequence specifically comprises the following steps:
forming the first insulating layer (150) on the gate insulating layer (120), covering the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source (142) and the drain (144);
forming the protective layer (160) on the first insulating layer (150), exposing and developing the protective layer (160) and the first insulating layer (150), and annealing the protective layer (160);
forming the second insulating layer (170) on the protective layer (160);
the first conductive layer (180) is formed on the second insulating layer (170), the first conductive layer (180) is exposed to light and developed, and the first conductive layer (180) and the second insulating layer (170) are simultaneously etched, and then the first conductive layer (180) is annealed.
4. The method of claim 1, wherein the first insulating layer (150), the passivation layer (160), the second insulating layer (170) and the first conductive layer (180) are sequentially formed, the first insulating layer (150) covers the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source electrode (142) and the drain electrode (144), the second insulating layer (170) covers the passivation layer (160), and the first conductive layer (180) is formed on the second insulating layer (170); through holes corresponding in position are respectively formed on the protective layer (160), the second insulating layer (170) and the first conductive layer (180), and the annealing of the protective layer (160) and the first conductive layer (180) in sequence specifically comprises the following steps:
forming the first insulating layer (150) on the gate insulating layer (120), covering the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source (142) and the drain (144);
forming the protection layer (160) on the first insulating layer (150), and annealing the protection layer (160);
forming the second insulating layer (170) on the protective layer (160), exposing and etching the protective layer (160), and forming a first via hole (162) and a third via hole (172) on the protective layer (160) and the second insulating layer (170), respectively;
the first conductive layer (180) is formed on the second insulating layer (170), and the first conductive layer (180) is exposed and developed, and the first conductive layer (180) is etched and annealed.
5. The method for manufacturing an array substrate according to claim 1, wherein forming an auxiliary conductive portion over the passivation layer (160), forming a via hole on the passivation layer (160), and annealing the first conductive layer (180), the auxiliary conductive portion covering a portion over the passivation layer (160) and contacting the first insulating layer (150) through the via hole of the passivation layer (160), the auxiliary conductive portion being located at a corresponding position between adjacent pixel units in a same row of the array substrate, comprises:
forming the first insulating layer (150) on the gate insulating layer (120), covering the second metal layer (140) and the semiconductor layer (130) exposed between the source (142) and the drain (144), and forming a second via hole by forming the first insulating layer (150);
forming the protective layer (160) on the first insulating layer (150), exposing and developing the protective layer (160) to form a first via hole (162), and annealing the protective layer (160);
forming an auxiliary conductive layer (161) on the protection layer (160), wherein a part of the auxiliary conductive layer (161) also passes through the second via hole (162) and covers the first insulating layer (150), and simultaneously, exposing, developing and etching the auxiliary conductive layer (161) to form the auxiliary conductive part;
forming the second insulating layer (170) on the auxiliary conductive layer (161), wherein the second insulating layer (170) covers the auxiliary conductive layer (161) and covers the portion of the protection layer (160) without the auxiliary conductive layer (161);
and forming the first conductive layer (180) on the second insulating layer (170), exposing and developing the first conductive layer (180), etching and annealing the first conductive layer (180), wherein the position of the second insulating layer (170) exposed after etching the first conductive layer (180) corresponds to the position of the auxiliary conductive layer (161).
6. The method for manufacturing an array substrate according to claim 1, wherein forming an auxiliary conductive portion over the protection layer (160), forming a via hole on the protection layer (160), and annealing the first conductive layer (180), the auxiliary conductive portion covering a portion over the protection layer (160) and contacting the first insulating layer (150) through the via hole of the protection layer (160), the auxiliary conductive portion being located at a corresponding position between adjacent pixel units in a same row of the array substrate by:
forming the first insulating layer (150) on the gate insulating layer (120), covering the gate insulating layer (120), the second metal layer (140) and the semiconductor layer (130) exposed between the source (142) and the drain (144);
forming the protective layer (160) on the first insulating layer (150), exposing and developing the protective layer (160) to form a first via hole (162), and annealing;
forming the second insulating layer (170) on the protective layer (160), and forming a hole on the second insulating layer (170) to form a third via hole (172);
forming the first conductive layer (180) on the second insulating layer (170), the first conductive layer (180) passing through the third via (172) and the first via (162) and covering the first insulating layer (150), exposing and developing the first conductive layer (180), etching and annealing the first conductive layer (180), the first conductive layer (180) being etched to form a first portion (185) and a second portion (186), the first portion (185) forming a common electrode of the array substrate, a portion of the second portion (186) passing through the third via (172) and the first via (162) and covering the first insulating layer (150) to form the auxiliary conductive portion.
7. An array substrate includes a substrate (100), a first metal layer (110), a gate insulating layer (120), a semiconductor layer (130), a second metal layer (140), a first insulating layer (150), a protective layer (160), an auxiliary conductive layer (161), a second insulating layer (170), a first conductive layer (180), a third insulating layer (190), and a second conductive layer (200), the first metal layer (110) is formed on the substrate (100) and forms a gate, the gate insulating layer (120) covers the first metal layer (110), the semiconductor layer (130) is formed on the gate insulating layer (120) and makes the semiconductor layer (130) be positioned right above the gate, the second metal layer (140) is formed on the gate insulating layer (120), the second metal layer (140) includes a source electrode (142), a drain electrode (144), and a data line (146) that are separated from each other, the source electrode (142) and the drain electrode (144) are respectively in contact with the semiconductor layer (130) to cover a part of the semiconductor layer (130), the first insulating layer (150) covers the gate insulating layer (120), and covers the second metal layer (140) and the semiconductor layer (130) exposed between the source electrode (142) and the drain electrode (144), the protective layer (160) is formed on the first insulating layer (150), the second insulating layer (170) covers the protective layer (160), the first conductive layer (180) is formed on the second insulating layer (170), the third insulating layer (190) covers the first conductive layer (180), the second conductive layer (200) is formed on the third insulating layer (190), the first conductive layer (180) and the second conductive layer (200) respectively form a common electrode and a pixel electrode, a plurality of pixel units (PX) arranged in an array are formed on the array substrate, the pixel unit comprises a protective layer (160), a drain electrode (144) and a pixel electrode, wherein the pixel electrode in each pixel unit (PX) is electrically connected with the corresponding drain electrode (144) in the pixel unit (PX) through a contact hole, the protective layer (160) is not covered at the corresponding position where the pixel electrode in each pixel unit (PX) is electrically connected with the corresponding drain electrode (144), an auxiliary electrode part is arranged between two pixel units (PX) in the same row, and the auxiliary electrode part is arranged above the protective layer (160) and is in contact with the first insulating layer (150) through the protective layer (160).
8. The array substrate of claim 7, wherein the auxiliary conductive portion is an auxiliary electrode layer (161) disposed on the protection layer (160) and contacting the first insulating layer (150) through the protection layer (160).
9. The array substrate of claim 7, wherein the first conductive layer (180) comprises a first portion (185) and a second portion (186) separated from each other, the first portion (185) and the second conductive layer (200) forming a common electrode and a pixel electrode, respectively, the second portion (186) passing through the second insulating layer (170), the protection layer (160) and the first insulating layer (150) to form the auxiliary conductive portion.
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