CN108573932A - Silicon carbide substrate for epitaxy and semiconductor chip - Google Patents
Silicon carbide substrate for epitaxy and semiconductor chip Download PDFInfo
- Publication number
- CN108573932A CN108573932A CN201710812888.2A CN201710812888A CN108573932A CN 108573932 A CN108573932 A CN 108573932A CN 201710812888 A CN201710812888 A CN 201710812888A CN 108573932 A CN108573932 A CN 108573932A
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- CN
- China
- Prior art keywords
- silicon carbide
- carbide substrate
- face
- epitaxial layer
- gallium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 56
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000407 epitaxy Methods 0.000 title claims abstract description 26
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 62
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 60
- 230000007547 defect Effects 0.000 claims abstract description 24
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 230000003746 surface roughness Effects 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004627 transmission electron microscopy Methods 0.000 description 2
- 241001062009 Indigofera Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003902 lesion Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- ZBZHVBPVQIHFJN-UHFFFAOYSA-N trimethylalumane Chemical compound C[Al](C)C.C[Al](C)C ZBZHVBPVQIHFJN-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
Abstract
The invention provides a silicon carbide substrate for epitaxy and a semiconductor chip, wherein the silicon carbide substrate is provided with a surface and a plurality of patterned structures formed by protruding from the surface, and the crystal face of the surface is a (0001) face; the width of the patterned structure is gradually reduced from bottom to top and forms at least one inclined side face, and the crystal face of the side face is a (-1,0,1,2) face. And a gallium nitride epitaxial layer is arranged on the top of the silicon carbide substrate to form the semiconductor chip. Therefore, the bottom of the GaN epitaxial layer forms laterally extending dislocation defects, which are not easy to form upwardly extending penetrating dislocation defects, so that the GaN epitaxial layer has good epitaxial quality.
Description
Technical field
The present invention relates to semiconductor epitaxy, more particularly to a kind of epitaxy silicon carbide substrate and semiconductor chip.
Background technology
Existing semiconductor subassembly, for example, semiconductor luminous assembly, high-velocity electrons mobility field-effect transistor (High-
Electron-mobility transistor, HEMT), laser diode, light emitting diode etc., be to set on a substrate mostly
Gallium nitride epitaxial layer is set, then makes the structure of component on gallium nitride epitaxial layer.
Current technology is all the setting gallium nitride epitaxial layer on sapphire substrate, but is existed between sapphire and gallium nitride
Lattice mismatch, the difference of coefficient of thermal expansion, therefore, the quality for being formed by gallium nitride epitaxial layer is often bad.Gallium nitride
The quality of epitaxial layer is related to the efficiency of component.To promote the quality of gallium nitride epitaxial layer, the current practice is in indigo plant mostly
One buffer layer is set between jewel substrate and gallium nitride epitaxial layer, then epitaxial layer of growing up on the buffer layer.The purpose of buffer layer is
It is to reduce the unmatched situation of lattice, reduce defect concentration or reduce the difference of coefficient of thermal expansion between substrate and epitaxial layer
It is different, the quality of epitaxial layer is promoted whereby.
For sapphire substrate, the Lattice Matching between silicon carbide substrate and gallium nitride more preferably, therefore, is being carbonized
The quality for the gallium nitride epitaxial layer being arranged on silicon substrate will be better than the quality for the gallium nitride epitaxial layer being arranged on sapphire substrate.
The quality for how further promoting the gallium nitride epitaxial layer on silicon carbide substrate is that relevant scholar, manufacturer exert
The direction of power research and development.
Invention content
In view of this, the purpose of the present invention is to provide a kind of epitaxy silicon carbide substrate and semiconductor chip, can obtain
Obtain quality more preferably gallium nitride epitaxial layer.
In order to achieve the above objectives, epitaxy silicon carbide substrate provided by the invention has a top, and the top is used for
Gallium nitride epitaxial layer, multiple pattern structures that the top has a surface and formed from the surface bulge are set, wherein
The crystal face on the surface is (0001) face；The width of the pattern structure is gradually reduced and forms at least one inclination from lower to upper
Side, the crystal face of the side is (- 1,0,1,2) face.
In order to achieve the above objectives, the present invention also provides a kind of semiconductor chip, including above-mentioned epitaxy is with silicon carbide-based
Plate and a gallium nitride epitaxial layer are set to the top of the epitaxy silicon carbide substrate.
It is an advantage of the current invention that due to the pattern structure side for being formed in epitaxy silicon carbide substrate crystal face be (-
1,0,1,2) face can be conducive to the growth of gallium nitride epitaxial layer, and therefore, gallium nitride epitaxial layer can first be grown up by the side of pattern structure,
Then just toward lateral and up accumulate.Thus, form the dislocation defects extended laterally in the bottom of gallium nitride epitaxial layer, just
Be not easy to be formed up extend penetrate dislocation defects, allow gallium nitride epitaxial layer that there is good epitaxy quality.
Description of the drawings
Fig. 1 is the schematic diagram of the silicon carbide substrate of first embodiment of the invention；
Fig. 2A~Fig. 2 E are the manufacturing process schematic diagram of the silicon carbide substrate of first embodiment of the invention；
Fig. 3 is the schematic diagram at the silicon carbide substrate gallium nitride growth epitaxial layer initial stage of first embodiment of the invention；
Fig. 4 is the schematic diagram of the semiconductor chip of first embodiment of the invention；
Fig. 5 is the semiconductor chip of first embodiment of the invention with the image of transmission electron microscopy observation；
Fig. 6 is the schematic diagram of the silicon carbide substrate of second embodiment of the invention；
Fig. 7 is the schematic diagram at the silicon carbide substrate gallium nitride growth epitaxial layer initial stage of second embodiment of the invention；
Fig. 8 is the schematic diagram of the semiconductor chip of second embodiment of the invention；
Fig. 9 is the semiconductor chip of second embodiment of the invention with the image of transmission electron microscopy observation.
Symbol description：
1, semiconductor chip；
10, silicon carbide substrate；
12, top；
122, surface；
124, pattern structure；
124a, side；
16, gallium nitride epitaxial layer；
16a, gallium nitride；
162, link surface；
164, dislocation defects；
2, semiconductor chip；
20, silicon carbide substrate；
202, pattern structure；
202a, top surface；
202b, side；
204, surface；
22, gallium nitride epitaxial layer；
22a, gallium nitride；
222, link surface；
224, dislocation defects；
100, silicon carbide base material；
102, upper surface；
104, hard shielding；
106, photoresist layer is patterned；
θ, angle；
W, width；
H, height；
D, D ', spacing.
Specific implementation mode
Below in conjunction with the accompanying drawings to the specific implementation mode of epitaxy silicon carbide substrate provided by the invention and semiconductor chip
It elaborates.
Refering to Figure 1, it is the silicon carbide substrate 10 of first embodiment of the invention, the silicon carbide substrate 10 has
One top 12, multiple pattern structures 124 that the top 12 has a surface 122 and convexed to form from the surface 122.
Wherein, the crystal face on the surface 122 is (0001) face.The pattern structure 124 is in pyramid in the present embodiment
Shape, width are gradually reduced and form inclined at least one side 124a from lower to upper, the crystal face of the side 124a be (- 1,
0,1,2) face, in the present embodiment, the quantity of at least one side 124a is six faces.Each side 124a and the surface
It is formed with an angle theta (angle i.e. between (0001) face and (- 1,0,1,2) face) between 122, in the present embodiment, the angle theta
It it is 110~130 degree, it is therefore preferable to 121.5 degree.The maximum width W of the bottom of each pattern structure 124 is 1~5 micron,
Preferably 1~3 micron；By the surface 122 start to each pattern structure 124 highest point height H be 0.3~
2 microns.Space D between the bottom of two neighboring pattern structure 124 is 2~3 microns, it is therefore preferable to 2.5 microns.It is each described
The surface roughness of side 124a is less than the surface roughness on the surface 122.
Fig. 2A~Fig. 2 E are please referred to, are the manufacturing process schematic diagram of the silicon carbide substrate of first embodiment of the invention.Institute
The manufacturing process for stating silicon carbide substrate 10 includes the following steps：
(a) Fig. 2A is please referred to, a silicon carbide base material 100 is taken, there is a upper surface 102.
(b) Fig. 2 B are please referred to, a shielding (hard mask) firmly is set on the upper surface of the silicon carbide base material 102
104, in the present embodiment, the SiO of 500nm is deposited using PECVD2As the hard shielding 104.
(c) Fig. 2 C are please referred to, with yellow light lithographic techniques fabricating patterned photoresist layer 106 in the hard shielding 104, at this
In embodiment, photoresist layer 106 be 2 μm of diameter, 1 μm of spacing dotted array photoresist.
(d) Fig. 2 D are please referred to, the region for not being patterned the covering of photoresist layer 106 in hard shielding 104 is removed with etching technics,
In the present embodiment, with Multicarity plasma etching system (Multi-chamber Plasma Etching System) into
Photoresist figure is transferred in hard shielding 104 by the deep dry etch process of row first stage 170 seconds.
(e) Fig. 2 E are please referred to, it is same not by the region of 104 covering of shielding firmly with dry etching processing procedure removal silicon carbide base material 100
When with laterally etched.In the present embodiment, with Multicarity plasma etching system (Multi-chamber Plasma
Etching System) carry out second stage deep dry etch process, to form the surface on the silicon carbide base material 100
122 and the pattern structure 124.It is finally immersed in BOE (Buffered Oxide Etecher) and removes photoresist to etch
Layer 106 and hard shielding 10 4, so complete the making of the silicon carbide substrate 10 of the present embodiment.Physics can be used in dry etching processing procedure
Property etching, chemically etching or physical plus chemically compound etching.
Due to the use of dry etching processing procedure, compared to the side 124a of pattern structure 124, the surface 122 is by larger
Damage, therefore the surface 122 formed with micro-crack, stress is larger the defects of a damage zone, thus the surface 122
Surface roughness be more than pattern structure 124 side 124a surface roughness.Certainly also can use laser, ion implantation or
Bombardment, electronics, which are stated, bombards the surface 122 to form damage zone.
Fig. 3 and Fig. 4 is please referred to, making the process that the present embodiment is semiconductor chip 1 is：With MOCVD in the silicon carbide
Grow up on substrate 10 a gallium nitride epitaxial layer 16, at the initial stage of the gallium nitride epitaxial layer 16 growth, gallium nitride 16a is first in pattern
The side 124a growth (please referring to Fig. 3) of change structure 124 is then covered in the surface 122, together toward lateral gradually extension accumulation
When up accumulation form the gallium nitride epitaxial layer 16 for being directly arranged at the top of the silicon carbide substrate 10.Due to gallium nitride
16a, which is first grown up by the side 124a of pattern structure 124 and stretches accumulation, is covered in the surface 122, and therefore, the gallium nitride is of heap of stone
Crystal layer 16 is directly connected in the side 124a of the pattern structure 124 and is in direct contact the surface 122.And then form this reality
Apply the semiconductor chip 1 (please referring to Fig. 4) of example.The gallium nitride epitaxial layer 16 has multiple joint faces 162, each joint face
162 are connected to the side 124a that crystal face is (- 1,0,1,2) face, the crystal face of each joint face 162 be (- 1,1,0,
1) face.
The gallium nitride epitaxial layer 16 has at the position for connecting each side 124a toward the dislocation defects extended laterally
(dislocation) 164, and the gallium nitride epitaxial layer 16 does not have at the position for being in direct contact the surface 122 and up prolongs
The dislocation defects stretched.Therefore, the dislocation defects 164 extended laterally will be not easy up to extend and formed and penetrate poor row so that described
The quality of the gallium nitride epitaxial layer 16 of 124 top of pattern structure is higher, is conducive to subsequent processing procedure.
Referring to Fig. 5, its boundary for the gallium nitride epitaxial layer 16 and silicon carbide substrate 10 of the semiconductor chip 1 of the present embodiment
The image that face is observed with transmission electron microscope (TEM), wherein (b) be (a) magnified image.By in Fig. 5 it can be seen that, gallium nitride
Epitaxial layer 16 can obviously observe the dislocation defects extended laterally in the region of 124 side 124a of adjacent pattern structure, and nitrogen
Change the dislocation defects that gallium epitaxial layer 16 does not upwardly extend then in the region on the surface 122 of neighbouring silicon carbide substrate 10, by
This is it is found that the gallium nitride epitaxial layer 16 is that first the side 124a by pattern structure 124 grows up in growth, and is not easy to
The surface 122 is grown up, therefore, be not easy to be formed upwardly extend penetrate dislocation defects.
Fig. 6 is the schematic diagram of the silicon carbide substrate 20 of second embodiment of the invention, has and is approximately identical to the first implementation
The structure of example, unlike, the pattern structure 202 of the present embodiment is trapezoidal, and pattern structure 202 has a top surface 202a,
The surface roughness of top surface 202a is more than the surface roughness of its side 202b, the top surface of two neighboring pattern structure 202
Space D between 202a ' it is 2~5 microns, it is preferably 3 microns.The manufacturing process of the silicon carbide substrate 20 and first is implemented
Example is roughly the same, the difference is that in the step of carrying out dry etching to silicon carbide base material in the present embodiment, laterally etched journey
It spends less, thus forms the top surface.Due to the step of carrying out dry etching to silicon carbide base material, the media fraction of dry etching can be worn
Hard shielding thoroughly, and the top surface 202a of pattern of lesions structure 202, therefore, the top surface 202a of pattern structure 202 can also form damage
Hinder area.
Fig. 7 and Fig. 8 is please referred to, the process for making the semiconductor chip 2 of the present embodiment is roughly the same with first embodiment,
At the initial stage that gallium nitride epitaxial layer 22 is grown up, gallium nitride 22a first (please refers to figure in the side 202b of pattern structure 202 growth
7) it then, is covered in the surface 204 toward lateral gradually extension accumulation, while up being accumulated, the semiconductor of the present embodiment is formed
Chip 2 (please refers to Fig. 8).There are the gallium nitride epitaxial layer 22 multiple joint faces 222, the joint face 222 to be connected to
Crystal face is the side 202b in (- 1,0,1,2) face, and the crystal face of each joint face 222 is (- 1,1,0,1) face.
The gallium nitride epitaxial layer 22 has at the position for connecting each side 202b toward the dislocation defects extended laterally
224, and the gallium nitride epitaxial layer 22 does not have the dislocation defects up extended at the position for being in direct contact the surface 204.
The dislocation defects 224 extended laterally will be not easy up to extend and formed and penetrate poor row so that 202 top of the pattern structure
The quality of gallium nitride epitaxial layer 22 is higher.
Please join Fig. 9, be the interface of gallium nitride epitaxial layer 22 and the silicon carbide substrate 20 of the semiconductor chip 2 of the present embodiment with
Transmission electron microscope (TEM) observation image, wherein (b) be (a) magnified image.By in Fig. 9 it can be seen that, gallium nitride epitaxy
Layer 22 can obviously observe the dislocation defects extended laterally in the region of 202 side 202b of adjacent pattern structure, and gallium nitride
The difference that epitaxial layer 22 does not upwardly extend then in the region on the surface 204 of neighbouring silicon carbide substrate 20 and the top surface 202a
Defect is arranged, it follows that the gallium nitride epitaxial layer 22 is that first the side 202b by pattern structure 202 grows up in growth,
And be not easy to grow up in the surface 204 and the top surface 202a, therefore, be not easy to be formed upwardly extend penetrate dislocation defects.
Gallium nitride epitaxial layer is directly arranged at the top of silicon carbide substrate in foregoing embodiments, and silicon carbide substrate and nitridation
The intermediary layer (such as aluminium carbide buffer layer) of silicon carbide and other materials other than gallium nitride is not set between gallium epitaxial layer.
It is mentioned above, since the crystal face for the pattern structure side for being formed in epitaxy silicon carbide substrate is (- 1,0,1,2)
Face can be conducive to gallium nitride epitaxial layer and grow, and therefore, gallium nitride epitaxial layer can first be grown up by the side of pattern structure, then just past
It accumulates laterally and up.Thus, form the dislocation defects extended laterally in the bottom of gallium nitride epitaxial layer, just it is not easy to be formed
What is up extended penetrates dislocation defects, and gallium nitride epitaxial layer is allowed to have good epitaxy quality.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (13)
1. a kind of epitaxy silicon carbide substrate has a top, for gallium nitride epitaxial layer to be arranged, feature exists at the top
In multiple pattern structures that the top has a surface and formed from the surface bulge, wherein the crystal face on the surface
For (0001) face；The width of the pattern structure is gradually reduced and forms at least one inclined side, the side from lower to upper
The crystal face in face is (- 1,0,1,2) face.
2. epitaxy silicon carbide substrate according to claim 1, which is characterized in that between each side and the surface
It is formed with an angle, the angle is 110~130 degree.
3. epitaxy silicon carbide substrate according to claim 1, which is characterized in that the quantity of at least one side is six
Face.
4. epitaxy silicon carbide substrate according to claim 1, which is characterized in that the bottom of each pattern structure
Maximum width is 1~5 micron.
5. epitaxy silicon carbide substrate according to claim 1, which is characterized in that the height of each pattern structure is
0.3~2 micron.
6. epitaxy silicon carbide substrate according to claim 1, which is characterized in that the two neighboring pattern structure
Spacing between bottom is 2~3 microns.
7. epitaxy silicon carbide substrate according to claim 1, which is characterized in that the surface roughness of each side is small
Surface roughness in the surface.
8. epitaxy silicon carbide substrate according to claim 7, which is characterized in that each pattern structure has a top
Face, the surface roughness of the top surface of each pattern structure are more than the surface roughness of its side.
9. epitaxy silicon carbide substrate according to claim 8, which is characterized in that the two neighboring pattern structure
Spacing between top surface is 2~5 microns.
10. a kind of semiconductor chip, which is characterized in that include：
Epitaxy silicon carbide substrate as described in claim 1 to 9 any one；And
One gallium nitride epitaxial layer is set to the top of the epitaxy silicon carbide substrate.
11. semiconductor chip according to claim 10, which is characterized in that the gallium nitride epitaxial layer has multiple connections
Face, the joint face are connected to the side, and the crystal face of each joint face is (- 1,1,0,1) face.
12. semiconductor chip according to claim 10, which is characterized in that the gallium nitride epitaxial layer is each described in connection
The position of side has toward the dislocation defects extended laterally.
13. semiconductor chip according to claim 12, which is characterized in that the gallium nitride epitaxial layer is contacting the table
The position in face does not have the dislocation defects up extended.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106107342 | 2017-03-07 | ||
| TW106107342A TWI621219B (en) | 2017-03-07 | 2017-03-07 | Silicon carbide substrate for epitaxy and semiconductor wafer |
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| Publication Number | Publication Date |
|---|---|
| CN108573932A true CN108573932A (en) | 2018-09-25 |
| CN108573932B CN108573932B (en) | 2020-06-16 |
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| CN201710812888.2A Active CN108573932B (en) | 2017-03-07 | 2017-09-11 | Silicon carbide substrate for epitaxy and semiconductor chip |
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| CN (1) | CN108573932B (en) |
| TW (1) | TWI621219B (en) |
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| TWI772950B (en) * | 2020-11-04 | 2022-08-01 | 長河企業有限公司 | Meta-structure for semiconductor substrate and method for manufacturing thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350388A (en) * | 2007-07-20 | 2009-01-21 | 广镓光电股份有限公司 | Semiconductor structure combination for semiconductor actinoelectricity component great crystal and production thereof |
| CN102347352A (en) * | 2010-07-30 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
| CN104218131A (en) * | 2013-05-31 | 2014-12-17 | 丰田合成株式会社 | Method for producing group iii nitride semiconductor and group iii nitride semiconductor |
| CN105355739A (en) * | 2015-10-23 | 2016-02-24 | 安徽三安光电有限公司 | Patterned substrate, preparation method and light-emitting diode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201642306A (en) * | 2015-05-28 | 2016-12-01 | 固美實國際股份有限公司 | Substrate for epitaxial growth of group III-V compound semiconductor |
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2017
- 2017-03-07 TW TW106107342A patent/TWI621219B/en active
- 2017-09-11 CN CN201710812888.2A patent/CN108573932B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350388A (en) * | 2007-07-20 | 2009-01-21 | 广镓光电股份有限公司 | Semiconductor structure combination for semiconductor actinoelectricity component great crystal and production thereof |
| CN102347352A (en) * | 2010-07-30 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
| US20160064271A1 (en) * | 2010-07-30 | 2016-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inverted Trapezoidal Recess for Epitaxial Growth |
| CN104218131A (en) * | 2013-05-31 | 2014-12-17 | 丰田合成株式会社 | Method for producing group iii nitride semiconductor and group iii nitride semiconductor |
| CN105355739A (en) * | 2015-10-23 | 2016-02-24 | 安徽三安光电有限公司 | Patterned substrate, preparation method and light-emitting diode |
Also Published As
| Publication number | Publication date |
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| CN108573932B (en) | 2020-06-16 |
| TW201834153A (en) | 2018-09-16 |
| TWI621219B (en) | 2018-04-11 |
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