CN108564980B - Shift register unit and driving method thereof, gate drive circuit and display device - Google Patents

Shift register unit and driving method thereof, gate drive circuit and display device Download PDF

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Publication number
CN108564980B
CN108564980B CN201810082366.6A CN201810082366A CN108564980B CN 108564980 B CN108564980 B CN 108564980B CN 201810082366 A CN201810082366 A CN 201810082366A CN 108564980 B CN108564980 B CN 108564980B
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pull
node
signal
unit
control
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CN108564980A (en
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陶健
唐锋景
董职福
李红敏
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention provides a shift register unit, a driving method thereof, a grid driving circuit and a display device, wherein the shift register unit comprises: the control end of the input unit is electrically connected with the input end point of the trigger signal, and the output end of the input unit is electrically connected with the pull-up node and the first pull-up node control unit and used for providing a first signal to the pull-up node when the control end of the input unit receives the first signal; the control end, the input end and the output end of the output unit are respectively and electrically connected with the pull-up node, the clock end and the information output end and are used for conducting the clock end and the signal output end under the control of a first signal of the pull-up node; the control end, the input end and the output end of the pull-up node enhancement unit are respectively electrically connected with the clock end, the first level signal end and the pull-up node, and the pull-up node enhancement unit is used for conducting the first level signal end and the pull-up node when receiving a falling edge signal of the clock end, providing the first signal to the pull-up node, outputting the falling edge signal in time through the output unit which is fully opened, and reducing the Tf time.

Description

Shift register unit and driving method thereof, gate drive circuit and display device
Technical Field
The invention relates to the technical field of display, in particular to a shift register unit, a driving method thereof, a gate driving circuit and a display device.
Background
A TFT (Thin Film Transistor) type display screen is a mainstream display device in various notebook computers and desktop computers, and each liquid crystal pixel on the display screen is driven by a Thin Film Transistor integrated behind the pixel, so the TFT type display screen is also an active matrix liquid crystal display device.
As the resolution of the liquid crystal display panel is higher, PPI (Pixels Per Inch Per Inch) is higher. With the progress of display technology, the Gate driving circuit has evolved into a GOA (Gate Driver On Array, Array substrate row Driver); generally, the GOA is composed of a plurality of shift register units.
The conventional shift register unit mainly comprises an input unit, a reset unit, a pull-up node control unit, a pull-down node control unit, an output unit and the like.
However, when the conventional shift register unit receives the falling edge of the clock signal, the output electrical signal of the output unit cannot be pulled down to a low level quickly, so that Tf (Fall Time) of the output electrical signal is easily too large, the waveform of the falling edge of the output electrical signal is distorted, and insufficient charging or incorrect output is easily caused.
Disclosure of Invention
The invention provides a shift register unit, a driving method thereof, a gate driving circuit and a display device aiming at the defects of the prior art, and aims to solve the problem that Tf is large or the waveform of the falling edge of an output electric signal is distorted in the prior art.
An embodiment of the present invention provides, according to a first aspect, a shift register unit including: the device comprises an input unit, a pull-up node enhancing unit, an output unit, a trigger signal input end, a signal output end, a clock end, a first level signal end and a pull-up node;
the control end of the input unit is electrically connected with the trigger signal input endpoint, and the output end of the input unit is electrically connected with the pull-up node and the first pull-up node control unit and is used for providing a first signal for the pull-up node when the control end of the input unit receives the first signal;
the control end, the input end and the output end of the output unit are respectively and electrically connected with the pull-up node, the clock end and the information output end, and the output unit is used for conducting the clock end and the signal output end under the control of a first signal of the pull-up node;
the pull-up node enhancing unit is electrically connected with the clock end, the first level signal end and the pull-up node respectively at a control end, an input end and an output end, and is used for conducting the first level signal end with the pull-up node and providing a first signal for the pull-up node when receiving a falling edge signal of the clock end.
Preferably, the shift register unit according to the embodiment of the present invention further includes:
and the first pull-up node control unit is electrically connected with the pull-up node at one end, is connected with the signal output end point at the other end, and is used for charging and providing a first signal for the pull-up node when receiving the first signal of the input unit or the first signal of the pull-up node enhancing unit.
Preferably, the shift register unit according to the embodiment of the present invention further includes: the pull-down circuit comprises a first pull-down node control unit, a second level signal end and a pull-down node;
the control end, the first input end and the output end of the first pull-down node control unit are respectively and electrically connected with the pull-up node, the second level signal end and the pull-down node;
and the control end, the input end and the output end of the second pull-down node control unit are respectively electrically connected with the pull-up node, the second level signal end and the pull-down node, and are used for providing a second signal for the pull-down node according to a second signal of the second level signal end under the control of the first signal of the pull-up node.
Preferably, the shift register unit according to the embodiment of the present invention further includes: the reset unit, the reset end and the third level signal end;
the reset unit, the control end, the input end and the output end are respectively electrically connected with the reset end, the third level signal end and the pull-up node and used for providing a second signal to the pull-up node according to a second signal of the third level signal end under the control of the first signal of the reset end.
Preferably, the second input terminal of the first pull-down node control unit is electrically connected to the first level signal terminal, and is configured to conduct the first signal of the first level signal terminal to the pull-down node under the control of the second signal of the pull-up node.
Preferably, the shift register unit according to the embodiment of the present invention further includes: a second pull-up node control unit and a pull-down unit;
the control end, the input end and the output end of the second pull-up node control unit are respectively connected with the pull-down node, the second level signal end and the pull-up node, and are used for conducting a second signal of the second level signal end to the pull-up node under the control of the first signal of the pull-down node so as to enable the output unit to be switched off;
the pull-down unit, the control end, the input end and the output end are respectively electrically connected with the pull-down node, the second level signal end and the signal output end and used for conducting a second signal of the second level signal end to the signal output end under the control of a first signal of the pull-down node.
Preferably, the pull-up node enhancing unit includes: fifth to eighth transistors;
a gate and a first electrode of the sixth transistor are respectively electrically connected with the clock end and the second level signal end, and a second electrode of the sixth transistor is electrically connected with a first electrode of the fifth transistor and a gate of the seventh transistor;
a grid electrode and a second electrode of the fifth transistor are both electrically connected with the first level signal end;
a seventh transistor, a second pole and a first pole of which are respectively and electrically connected with the first level signal end and the second pole of the eighth transistor;
a gate and a first pole of the eighth transistor are both electrically connected to the pull-up node.
Embodiments of the present invention also provide a gate driving circuit according to the second aspect, including: multiple sets of shift register units according to the first aspect of the present invention are provided.
Embodiments of the present invention also provide, according to a third aspect, a display device including: multiple sets of shift register units according to the first aspect of the present invention are provided.
An embodiment of the present invention further provides, according to a fourth aspect, a driving method of a shift register unit according to the first aspect, including:
when an input unit in the shift register unit receives a first signal from a trigger signal input end of the shift register unit through a control end of the input unit, the first signal is provided for the pull-up node;
when the output unit in the shift register unit receives the first signal of the pull-up node through the control end of the output unit, the clock end and the signal output end which are respectively and electrically connected with the output unit in the shift register unit are conducted;
and when a control end of the pull-up node enhancing unit receives a falling edge signal of the clock end, a pull-up node enhancing unit in the shift register unit conducts a first level signal end electrically connected with the pull-up node enhancing unit and the pull-up node respectively, and provides a first signal for the pull-up node.
In the embodiment of the invention, when the pull-up node enhancement unit receives a falling edge signal of a clock end, the pull-up node enhancement unit conducts a first level signal end with a pull-up node and provides a first signal to the pull-up node; when the input end of the output unit receives a falling edge signal (from high level to low level) of the clock end, a pull-up node electrically connected with the control end of the output unit can still maintain a first signal (high level), so that the output unit can keep a fully opened state, namely, the input end and the output end of the output unit are fully conducted, the falling edge signal (and subsequent low level signals) of the clock end can be timely and fully conveyed to the signal output end through the fully opened output unit, the Tf time of the output signal of the signal output end is greatly reduced, the waveform distortion degree of the falling edge of the output electric signal is greatly reduced, the charging efficiency is greatly improved, the probability of error output of the signal output end is greatly reduced, and the reliability is improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an example of a shift register unit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a conventional shift register;
FIG. 4 is a timing diagram of a shift register according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
An embodiment of the present invention provides a shift register unit, and a schematic diagram of a module structure of a construction method of the shift register unit is shown in fig. 1, where the schematic diagram includes: the circuit comprises an INPUT unit, a pull-up node enhancement unit, an OUTPUT unit, a trigger signal INPUT end (INPUT), a signal OUTPUT end (OUTPUT), a clock end (CLK), a first level signal end (VGH) and a pull-up node (PU).
And the control end of the input unit is electrically connected with the input end point of the trigger signal, and the output end of the input unit is electrically connected with the pull-up node and the first pull-up node control unit and is used for providing a first signal to the pull-up node when the control end of the input unit receives the first signal.
The control end, the input end and the output end of the output unit are respectively and electrically connected with the pull-up node, the clock end and the information output end and are used for conducting the clock end and the signal output end under the control of a first signal of the pull-up node;
and the control end, the input end and the output end of the pull-up node enhancement unit are respectively and electrically connected with the clock end, the first level signal end and the pull-up node, and are used for conducting the first level signal end and the pull-up node when receiving a falling edge signal of the clock end and providing a first signal to the pull-up node. Further, the first signal is specifically a high level signal.
Therefore, in the embodiment of the present invention, when the pull-up node enhancing unit receives the falling edge signal of the clock end, the first level signal end is conducted with the pull-up node, and a first signal is provided to the pull-up node; when the input end of the output unit receives a falling edge signal (from high level to low level) of the clock end, a pull-up node electrically connected with the control end of the output unit can still maintain a first signal (high level), so that the output unit can keep a fully opened state, namely, the input end and the output end of the output unit are fully conducted, the falling edge signal (and subsequent low level signals) of the clock end can be timely and fully conveyed to the signal output end through the fully opened output unit, the Tf time of the output signal of the signal output end is greatly reduced, the waveform distortion degree of the falling edge of the output electric signal is greatly reduced, the charging efficiency is greatly improved, the probability of error output of the signal output end is greatly reduced, and the reliability is improved.
Preferably, as shown in fig. 1, the shift register unit according to the embodiment of the present invention further includes: a first pull-up node control unit.
And one end of the first pull-up node control unit is electrically connected with the pull-up node, and the other end of the first pull-up node control unit is connected with the signal output end point, and is used for charging the first pull-up node control unit and providing a first signal for the pull-up node when receiving the first signal of the input unit or the first signal of the pull-up node enhancement unit.
Preferably, as shown in fig. 1, the shift register unit according to the embodiment of the present invention further includes: a first pull-down node control unit, a second level signal terminal (VGL), and a pull-down node (PD);
and the control end, the first input end and the output end of the first pull-down node control unit are respectively and electrically connected with the pull-up node, the second level signal end and the pull-down node, and are used for disconnecting a circuit between the first signal and the pull-down node under the control of the first signal of the pull-up node and preventing the first signal from being transmitted to the pull-down node at the moment.
And the control end, the input end and the output end of the second pull-down node control unit are respectively electrically connected with the pull-up node, the second level signal end and the pull-down node and are used for providing a second signal to the pull-down node according to a second signal of the second level signal end under the control of the first signal of the pull-up node. Further, the second signal is specifically a low level signal.
Preferably, as shown in fig. 1, the shift register unit according to the embodiment of the present invention further includes: a RESET unit, a RESET terminal (RESET), and a third level signal terminal (VSS);
and the control end, the input end and the output end of the reset unit are respectively and electrically connected with the reset end, the third level signal end and the pull-up node, and the reset unit is used for providing a second signal to the pull-up node according to a second signal of the third level signal end under the control of a first signal of the reset end.
Preferably, as shown in fig. 1, in the first pull-down node control unit according to the embodiment of the present invention, the second input terminal is electrically connected to the first level signal terminal, and is configured to conduct the first signal of the first level signal terminal to the pull-down node under the control of the second signal of the pull-up node.
Preferably, as shown in fig. 1, the shift register unit according to the embodiment of the present invention further includes: a second pull-up node control unit and a pull-down unit.
And the control end, the input end and the output end of the second pull-up node control unit are respectively connected with the pull-down node, the second level signal end and the pull-up node and are used for conducting a second signal of the second level signal end to the pull-up node under the control of the first signal of the pull-down node, so that the output unit is turned off.
And the control end, the input end and the output end of the pull-down unit are respectively and electrically connected with the pull-down node, the second level signal end and the signal output end, and are used for conducting a second signal of the second level signal end to the signal output end under the control of a first signal of the pull-down node.
Fig. 2 is a circuit configuration diagram of an example of a shift register unit according to an embodiment of the present invention. With reference to fig. 1 and fig. 2, the following relationships between the devices and the functional units are assigned:
an input unit: a transistor M1;
pull-up node enhancement unit (identified by dashed box in fig. 2): transistors M5, M6, M7, and M8;
an output unit: a transistor M3;
a first pull-up node control unit: a capacitor C;
a second pull-down node control unit: transistors M9, M10, and M11;
a second pull-down node control unit: a transistor M12;
a reset unit: a transistor M2;
a second pull-up node control unit: a transistor M13;
a pull-down unit: transistor M4.
The circuit comprises a trigger signal INPUT end INPUT, a signal OUTPUT end OUTPUT, a clock end CLK, a RESET end RESET, a first level signal end VGH, a second level signal end VGL, a third level signal end VSS, a fourth level signal end VDD, a pull-up node PU and a pull-down node PD.
The electrical connection between the devices in each functional unit is described below.
Preferably, as shown in fig. 2, the gate, the second pole and the first stage of the first transistor M1 in the INPUT unit according to the embodiment of the present invention are electrically connected to the trigger signal INPUT terminal INPUT, the fourth level signal terminal VDD and the pull-up node PU, respectively, for providing the first signal to the pull-up node PU when the gate of the first transistor M1 receives the first signal INPUT by the INPUT.
Preferably, as shown in fig. 2, the capacitor C in the first pull-up node unit according to the embodiment of the present invention has one end electrically connected to the pull-up node PU and the other end electrically connected to the signal OUTPUT terminal OUTPUT, and the OUTPUT terminal is initially in the second signal (low level) state, and starts to be charged when the first signal (high level) is received by the pull-up node PU, so that the level of PU is raised to the first signal.
Preferably, as shown in fig. 2, in the third transistor M3 of the OUTPUT unit according to the embodiment of the present invention, the gate, the second pole and the first pole are electrically connected to the pull-up node PU, the clock terminal CLK and the signal OUTPUT terminal OUTPUT, respectively, for conducting the clock terminal CLK and the signal OUTPUT terminal OUTPUT under the control of the first signal of the pull-up node PU, and outputting the signal of CLK to the signal OUTPUT terminal OUTPUT.
Preferably, as shown in fig. 2, the pull-up node enhancing unit according to the embodiment of the present invention includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
The sixth transistor M6 has a gate and a first pole electrically connected to the clock terminal CLK and the second level signal terminal VGL, respectively, and a second pole electrically connected to the first pole of the fifth transistor M5 and the gate of the seventh transistor M7.
The gate and the second pole of the fifth transistor M5 are electrically connected to the first level signal terminal VGH.
The seventh transistor M7 has a second pole and a first pole electrically connected to the first level signal terminal VGH and the second pole of the eighth transistor M8, respectively.
The gate and the first pole of the eighth transistor M8 are both electrically connected to the pull-up node PU.
M6 is used to turn off when CLK outputs a falling edge signal (transitions from high to low). At this time, M5 turns on the first signal of VGH to the gate of M7, so that M7 is turned on. M7 turns on the first signal of VGH to the second pole of M8. At this time, since the level at both ends of the capacitor C has not changed abruptly, PU is still the first signal (high level), M8 is in a conducting state, the first signal of VGH is conducted from the second pole to PU electrically connected to the first pole, and C is charged, so that PU is maintained at the first level, M3 of the OUTPUT unit is sufficiently conducted, and the falling edge signal of CLK is sufficiently transmitted to OUTPUT in time.
Preferably, as shown in fig. 2, the first pull-down node control unit according to the embodiment of the present invention includes: a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
The tenth transistor M10 has a gate, a first pole and a second pole electrically connected to the pull-up node PU, the second level signal terminal VGL and the gate of the eleventh transistor M11, respectively.
The ninth transistor M9 has a gate and a second pole electrically connected to the first level signal terminal VGH, and a first pole electrically connected to the gate of the eleventh transistor M11.
The eleventh transistor M11 has a second pole and a first pole electrically connected to the first level signal terminal VGH and the pull-down node PD, respectively.
M10 is used to conduct the second signal of VGL to the gate of M11 under the control of the first signal of the pull-up node PU, so that M11 is turned off and the first signal of VGH is prevented from conducting to PD.
And M10 is turned off under the control of the second signal of the PU; at this time, M9 turns on the first signal of VGH to the gate of M11, so that M11 is turned on; m11 turns on the first signal of VGH to PD.
Preferably, as shown in fig. 2, the second pull-down node control unit according to the embodiment of the present invention includes a twelfth transistor M12. A twelfth transistor M12, having a gate, a first stage, and a second pole electrically connected to the pull-up node PU, the second level signal terminal VGL, and the pull-down node PD, respectively, and configured to provide a second signal to the pull-down node PD according to a second signal of the second level signal terminal VGL under the control of the first signal of the pull-up node PU; and under the control of a second signal of the PU, opening an electrical path between the VGL and the PD.
Preferably, as shown in fig. 2, the reset unit of the embodiment of the present invention includes a second transistor M2.
The gate, the input end and the output end of the second transistor M2 are electrically connected with the RESET terminal RESET, the third level signal terminal VSS and the pull-up node PU, respectively, and are configured to provide a second signal to the pull-up node PU according to a second signal of the third level signal terminal VSS under the control of the first signal of the RESET terminal RESET.
Preferably, as shown in fig. 2, the second pull-up node control unit according to the embodiment of the present invention includes a thirteenth transistor M13.
The thirteenth transistor M13, the gate, the input terminal, and the output terminal of which are respectively connected to the pull-down node PD, the second level signal terminal VGL, and the pull-up node PU, is used for conducting the second signal of the second level signal terminal VGL to the pull-up node PU under the control of the first signal of the pull-down node PD, so that the output unit M3 is turned off.
Preferably, as shown in fig. 2, the pull-down unit of the embodiment of the present invention includes a fourth transistor M4.
The fourth transistor M4 has a gate, an input end, and an OUTPUT end electrically connected to the pull-down node PD, the second level signal end VGL, and the signal OUTPUT end OUTPUT, respectively, and is configured to conduct the second signal of the second level signal end VGL to the signal OUTPUT end OUTPUT under the control of the first signal of the pull-down node PD, so as to prevent the OUTPUT signal from outputting a noise signal in the reset stage (pull-down stage).
In fact, when the transistor of the embodiment of the invention is an NMOS, the first and second poles are a source and a drain.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method for a shift register unit, including:
when an input unit in the shift register unit receives a first signal from a trigger signal input end of the shift register unit through a control end of the input unit, the first signal is provided to a pull-up node;
the output unit in the shift register unit is used for conducting a clock end and a signal output end which are respectively and electrically connected with the output unit in the shift register unit when receiving a first signal of the pull-up node through a control end of the output unit;
and when the control end of the pull-up node enhancing unit receives a falling edge signal of the clock end, the pull-up node enhancing unit in the shift register unit conducts a first level signal end and a pull-up node which are respectively and electrically connected with the pull-up node enhancing unit, and provides a first signal to the pull-up node.
The operation principle of the embodiment of the present invention is specifically described below with reference to a timing chart example.
FIG. 3 is a timing diagram of a conventional shift register; FIG. 4 is a timing diagram of a shift register according to an embodiment of the present invention. T1 is the charging phase of the shift register, T2 is the outputting phase of the shift register, T3 is the phase of the shift register outputting the falling edge signal, and T4 is the resetting phase of the shift register.
As shown in fig. 3, in the conventional shift register, the falling edge of OUTPUT is distorted more seriously when approaching the second signal (low level) falling to VGL, and OUTPUT cannot be pulled to be consistent with the second signal of VGL in time. This is because the existing shift register lacks the pull-up node enhancement unit in the embodiment of the present invention, and M3 in the output unit is not sufficiently opened.
Referring to fig. 2 and 4, during the period T1, VDD is high, INPUT is high, M1 is turned on to provide the first signal (high) to the PU point, and charges the capacitor C, so that the PU point is set high to the first signal (high).
At stage T1, when PU reaches high, M3 begins to turn on, but since CLK still OUTPUTs low, OUTPUT remains low. M10 is turned on so that the low level of VGL causes the gate to M11, causing M11 to turn off, breaking the electrical path between the high level of VGH and the PD. At the same time, M12 is turned on, turning on the low of VGL to PD, causing the PD point to be set low.
In addition, at stage T1, when the PD point is set low, M13 is turned off and M4 is turned off.
At stage T2, INPUT goes low, PU point remains high, M4 and M13 are still off-set, CLK INPUT is high, M3 is fully turned on, and CLK signal is output from OUTPU full swing.
At stage T3, when the CLK signal goes low (OUTPUT falling edge signal), M6 turns off, M7 turns on, M8 also turns on because PU is high, VGH charges PU, M3 is still fully on, and OUTPUT is pulled low quickly by the CLK signal. This solves the problem that the PU point bootstrap effect disappears when the CLK signal goes low, causing M3 to open insufficiently, resulting in distortion of the OUTPUT falling edge.
At stage T4, RESET inputs HIGH, M2 turns ON, turns VSS LOW to PU, and turns PU LOW.
In stage T4, when the PU changes to low level, M12 is turned off, and the electric path between the low level of VGL and the PD is switched; m10 turns off, causing M9 to turn on the high of VGH to the gate of M11, causing M11 to turn on the high of VGH to PD, setting PD high.
At stage T4, when PD goes high, M13 turns on, M13 turns on VGL low to PU, which is lowered to low so that M3 no longer OUTPUTs high to OUTPUT. M4 is turned on, turning on the low level of VGL to OUTPUT, clamping OUTPUT at the low level, and preventing OUTPUT from outputting a noise signal.
Based on the same invention concept, an embodiment of the present invention further provides a gate driving circuit, which includes a plurality of sets of shift register units provided by the embodiment of the present invention.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including: a plurality of shift register units provided in the embodiments of the present invention.
It will be understood by those within the art that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. Those skilled in the art will appreciate that the computer program instructions may be implemented by a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the features specified in the block or blocks of the block diagrams and/or flowchart illustrations of the present disclosure.
Those of skill in the art will appreciate that various operations, methods, steps in the processes, acts, or solutions discussed in the present application may be alternated, modified, combined, or deleted. Further, various operations, methods, steps in the flows, which have been discussed in the present application, may be interchanged, modified, rearranged, decomposed, combined, or eliminated. Further, steps, measures, schemes in the various operations, methods, procedures disclosed in the prior art and the present invention can also be alternated, changed, rearranged, decomposed, combined, or deleted.
The foregoing is only a partial embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (9)

1. A shift register unit, comprising: the device comprises an input unit, a pull-up node enhancing unit, an output unit, a trigger signal input end, a signal output end, a clock end, a first level signal end, a pull-up node and a first pull-up node control unit;
the control end of the input unit is electrically connected with the trigger signal input endpoint, and the output end of the input unit is electrically connected with the pull-up node and the first pull-up node control unit and is used for providing a first signal for the pull-up node when the control end of the input unit receives the first signal;
the control end, the input end and the output end of the output unit are respectively and electrically connected with the pull-up node, the clock end and the information output end, and the output unit is used for conducting the clock end and the signal output end under the control of a first signal of the pull-up node;
the control end, the input end and the output end of the pull-up node enhancement unit are respectively electrically connected with the clock end, the first level signal end and the pull-up node, and are used for conducting the first level signal end with the pull-up node and providing a first signal for the pull-up node when receiving a falling edge signal of the clock end;
one end of the first pull-up node control unit is electrically connected with the pull-up node, and the other end of the first pull-up node control unit is connected with the signal output end point, and is used for charging and providing a first signal for the pull-up node when receiving the first signal of the input unit or the first signal of the pull-up node enhancement unit;
the input unit comprises a first transistor, a grid electrode of the first transistor is used as a control end of the input unit, a first electrode of the first transistor is used as an output end of the input unit, and a second electrode of the first transistor is electrically connected with a fourth level signal end.
2. The shift register unit according to claim 1, further comprising: the pull-down circuit comprises a first pull-down node control unit, a second level signal end and a pull-down node;
the control end, the first input end and the output end of the first pull-down node control unit are respectively and electrically connected with the pull-up node, the second level signal end and the pull-down node;
and the control end, the input end and the output end of the second pull-down node control unit are respectively electrically connected with the pull-up node, the second level signal end and the pull-down node, and are used for providing a second signal for the pull-down node according to a second signal of the second level signal end under the control of the first signal of the pull-up node.
3. The shift register unit according to claim 2, further comprising: the reset unit, the reset end and the third level signal end;
the reset unit, the control end, the input end and the output end are respectively electrically connected with the reset end, the third level signal end and the pull-up node and used for providing a second signal to the pull-up node according to a second signal of the third level signal end under the control of the first signal of the reset end.
4. The shift register cell of claim 3,
and the second input end of the first pull-down node control unit is electrically connected with the first level signal end and is used for conducting a first signal of the first level signal end to the pull-down node under the control of a second signal of the pull-up node.
5. The shift register unit according to claim 4, further comprising: a second pull-up node control unit and a pull-down unit;
the control end, the input end and the output end of the second pull-up node control unit are respectively connected with the pull-down node, the second level signal end and the pull-up node, and are used for conducting a second signal of the second level signal end to the pull-up node under the control of the first signal of the pull-down node so as to enable the output unit to be switched off;
the pull-down unit, the control end, the input end and the output end are respectively electrically connected with the pull-down node, the second level signal end and the signal output end and used for conducting a second signal of the second level signal end to the signal output end under the control of a first signal of the pull-down node.
6. The shift register unit of claim 1, wherein the pull-up node enhancement unit comprises: fifth to eighth transistors;
a gate and a first electrode of the sixth transistor are respectively electrically connected with the clock end and the second level signal end, and a second electrode of the sixth transistor is electrically connected with a first electrode of the fifth transistor and a gate of the seventh transistor;
a grid electrode and a second electrode of the fifth transistor are both electrically connected with the first level signal end;
a seventh transistor, a second pole and a first pole of which are respectively and electrically connected with the first level signal end and the second pole of the eighth transistor;
a gate and a first pole of the eighth transistor are both electrically connected to the pull-up node.
7. A gate drive circuit, comprising: sets of shift register cells as claimed in any one of claims 1 to 6.
8. A display device, comprising: sets of shift register cells as claimed in any one of claims 1 to 6.
9. A driving method based on the shift register unit of any one of claims 1-6, comprising:
when an input unit in the shift register unit receives a first signal from a trigger signal input end of the shift register unit through a control end of the input unit, the first signal is provided for the pull-up node;
when the output unit in the shift register unit receives the first signal of the pull-up node through the control end of the output unit, the clock end and the signal output end which are respectively and electrically connected with the output unit in the shift register unit are conducted;
and when a control end of the pull-up node enhancing unit receives a falling edge signal of the clock end, a pull-up node enhancing unit in the shift register unit conducts a first level signal end electrically connected with the pull-up node enhancing unit and the pull-up node respectively, and provides a first signal for the pull-up node.
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