CN108549589A - A kind of model taking method of low overhead - Google Patents
A kind of model taking method of low overhead Download PDFInfo
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- CN108549589A CN108549589A CN201810235355.7A CN201810235355A CN108549589A CN 108549589 A CN108549589 A CN 108549589A CN 201810235355 A CN201810235355 A CN 201810235355A CN 108549589 A CN108549589 A CN 108549589A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/181—Eliminating the failing redundant component
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
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Abstract
The present invention provides a kind of model taking method of low overhead, this method is by taking mould m=3 as an example, modulo operation can pass through the number of statistics remainder 1 and remainder 2, then it is tabled look-up determining remainder according to the number of remainder 1 and remainder 2, further according to the final result of the positive and negative determining remainder of input data, this method greatly reduces the expense of modulo operation compared with directly using % model taking methods.
Description
Technical field
The present invention relates to residue check fields, more particularly, to a kind of model taking method of low overhead.
Background technology
Space radiation environment has a serious impact the electronic product of spacecraft, and single particle effect is mainly to examine
The influence of worry.In space application, single particle effect can generate serious consequence, including information is lost and disabler.When with
When the charged particle of transfer energy enough hits chip, it is possible to single particle effect phenomenon occur, and then cause the system failure.Spoke
It penetrates where transient error caused by effect has become being primarily upon of people, only application fault tolerance technology just can guarantee circuit
Reliability.
Triplication redundancy technology is used widely in the fault-tolerant signal processing under radiation environment.Triplication redundancy uses three
Equal modules carry out identical filtering operation to input data, select two-way or the identical result in three tunnels to be exported, completely eliminate
The influence that single spur track failure exports signal processing.But in triplication redundancy technology, all operations and storage resource consumption
All increase to original three times, this makes triplication redundancy technology that can not be used in many resource-constrained applications, such as spaceborne flat
Fault-tolerant signal processing on platform etc..
In order to reduce fault-tolerant expense, researcher proposes the fault-tolerant networks based on residue check.Based on residue check
Fault-tolerant networks in, if verification branch using smaller modulus, can make hardware spending be significantly less than it is common calculate branch, because
This can significantly reduce the expense of whole tolerant system.
If it is essential operation to data modulus using the fault-tolerant signal processing technology based on residue check.And
And if the fault-tolerant networks based on residue check are complex, using more modulo operation, then the modulus in entire fault-tolerant networks
The resource overhead of operation can also account for significant proportion.
Invention content
The present invention provides a kind of model taking method of low overhead, to reduce modulo operation in the fault-tolerant networks based on residue check
Resource overhead.
In order to reach above-mentioned technique effect, technical scheme is as follows：
A kind of model taking method of low overhead, includes the following steps：
S1：If binary system signed number x is negative, x is first become into binary system positive number, is then assigned to y；Else if
Binary system signed number x is positive number, then the value of x is directly assigned to y；
S2：The number for counting on the 0th, 2,4,6 etc. the even bits of binary system positive number y 1, is set as m；Same statistics binary system is just
1 number in the 1st, 3,5,7 etc. several odd bits is set as n, and wherein m is the number that remainder is 1, and n is the number that remainder is 2；
S3：The number for counting on the 0th, 2,4 etc. the even bits of binary system positive number m 1, is set as a；Count binary system positive number m's
1 number in 1st, 3,5 etc. odd bits is set as b, and wherein a is the number that remainder is 1, and b is the number that remainder is 2；
S4：The number for counting on the 0th, 2,4 etc. the even bits of binary system positive number n 1, is set as c；Count binary system positive number m's
1 number in 1st, 3,5 etc. odd bits is set as d, and wherein c is the number that remainder is 2, and d is the number that remainder is 1；
S5：The number that remainder is 1 be a and d's and, be set as e；The number that remainder is 2 be b and c's and, f is set as, according to e
Remainder can be determined with the value of f, establishes a read only memory ROM, and read only memory ROM exports corresponding according to the value of e and f
Remainder；
S6：The remainder of ROM outputs is 2 binary system positive numbers, if input data x is positive number, directly by ROM outputs
Remainder is as modulo operation final result, if input data x is negative, conduct after the ROM remainder step-by-steps exported are negated
Modulo operation final result.
Further, in the step S1, if binary system signed number x is positive number, the value of x is directly assigned to y, such as
Fruit x is negative, then negates binary number x step-by-steps and be assigned to y after adding 1.
Further, in the step S2, if being 1 on the 0th, 2,4,6 etc. the even bits of binary system positive number y, each
Corresponding position represents numerical value as 4N, wherein N be the integers such as 0,1,2,3,4NIt is 1 to mould M=3 remainders, so that it is 1 that m, which is remainder,
Number；
If being 1 in the 1st, 3,5,7 etc. the odd bits of binary system positive number y, each corresponding position represents numerical value as 2*4N,
Wherein N is the integers such as 0,1,2,3,2*4NIt is 2 to mould M=3 remainders, so the number that it is 2 that n, which is remainder,.
Further, in step S3, due to the number that m is remainder 1, so the number that it is 1 that a, which is remainder, b is that remainder is 2
Number.
Further, in step S4, due to n be remainder 2 number, if the 0th of binary number n the, 2,4, the even bits such as 6
Upper is 1, then each corresponding position represents numerical value as 2*4N, wherein N is the integers such as 0,1,2,3,2*4NIt is 2 to mould M=3 remainders, institute
The number for being 2 by remainder of c；
Due to the number that n is remainder 2, if the 1st of binary number n the, 3,5, in the odd bits such as 7 be 1, each corresponding positions
It sets and represents numerical value as 4N+1, wherein N is the integers such as 0,1,2,3, and it is the number that remainder is 1 that 4N+1, which is 1, d to mould M=3 remainders,.
Further, in step S5, the number that remainder is 1 is e；The number that remainder is 2 is f；It can be with according to the value of e and f
Calculate the remainder to 3 complementations, the value of different e and f correspond to different remainders, and this correspondence, which is equivalent to, establishes one
The truth table of the combination logic function of a read only memory ROM.
Further, in step S6, the remainder of ROM outputs is 2 binary system positive numbers 0,1,2, if input data x is just
Number, then the 0 and ROM remainders exported are stitched together using position splicing operator becomes the signed number that a highest order is 0, makees
It is exported for final result；If input data x be negative, remainder generally also be negative, can first by ROM output more than
Number step-by-step adds 1 to become corresponding negative again after negating, and 1 and this negative, which are stitched together, using position splicing operator becomes one
The signed number that highest order is 1 directly exports, as final as a result, wherein if remainder is 0 without aforesaid operations；
Since the remainder that can be generated to three branches in the fault-tolerant networks based on residue check is compared, and if remainder
For negative, negative can be become positive number to facilitate the comparison between remainder plus modulus；Mould is 3, if input data x is negative,
Then can by ROM export remainder step-by-step negate, so that it may with obtain negative plus modulus become positive number as a result, wherein if remaining
Number is 0, then directly exports, without aforesaid operations, if input data x is positive number, the remainder for directly exporting ROM as
As a result.
Compared with prior art, the advantageous effect of technical solution of the present invention is：
In the method for the present invention by taking mould m=3 as an example, modulo operation can be by the number of statistics remainder 1 and remainder 2, then
It is tabled look-up determining remainder according to the number of remainder 1 and remainder 2, further according to the final result of the positive and negative determining remainder of input data, this
Kind method greatly reduces the expense of modulo operation compared with directly using % model taking methods.
Description of the drawings
Fig. 1 is the method for the present invention.
Specific implementation mode
The attached figures are only used for illustrative purposes and cannot be understood as limitating the patent；
In order to more preferably illustrate that the present embodiment, the certain components of attached drawing have omission, zoom in or out, actual product is not represented
Size；
To those skilled in the art, it is to be appreciated that certain known features and its explanation, which may be omitted, in attached drawing
's.
The following further describes the technical solution of the present invention with reference to the accompanying drawings and examples.
Embodiment 1
As shown in Figure 1, a kind of low overhead model taking method, includes the following steps：
Binary number x step-by-steps are negated again if the highest order of binary load x is 1 plus 1 become positive number, just by S1
Several values are assigned to y, if the highest order of binary number x is 0, its value is directly assigned to y；
S2 seeks the 0th, 2,4,6,8,10,12,14 upper 1 number of binary number y, m is set as, if on binary number y
It is 1 that rheme, which sets number, then the remainder that its 3 modulus of value pair represented obtains is 1；
The the 1st, 3,5,7,9,11,13 upper 1 number for seeking binary number y, is set as n, if the above-mentioned positions binary number y
Upper number is 1, then the remainder that its 3 modulus of value pair represented obtains is 2；
In addition, the maximum value that the maximum value of m is 8, n is 7；
S3 seeks the 0th, 2 upper 1 number of binary number m, is set as a, due to the number that m is remainder 1 in S2 steps, institute
Using a as the number of remainder 1；
The the 1st, 3 upper 1 number for seeking binary number m, is set as b, due to the number that m is remainder 1 in S2 steps, so b
For the number of remainder 2；
S4 seeks the 0th, 2 upper 1 number of binary number n, is set as c, due to the number that n is remainder 2 in S2 steps, institute
Using c as the number of remainder 2；
The 1st upper 1 number for seeking binary number n, is set as d, due to the number that n is remainder 2 in S2 steps, so d is
The number of remainder 1；
S5, asks that remainder is 1 in S3 and S4 steps and remainder is 2 total numbers respectively, acquire a and d's and, be set as e, e is
Remainder is the summation of 1 number；Acquire b and c's and, be set as f, f is the summation that remainder is 2 numbers；
Remainder can be determined according to the value of e and f, for example, when e and f is 1, output remainder is 0.This relationship is equivalent to
The truth table of one logical combination is got up the information storage of this truth table using read only memory ROM.According to the value of e and f
Corresponding remainder is exported, remainder has the binary number 0 that bit wide is 2,1,2 three kind of situation；
S6, if the binary number x highest orders in S1 steps are 0, using the remainder of read only memory ROM output as most
Terminate fruit；
Read only memory ROM is exported the remainder in addition to 0 by S7 if the binary number x highest orders in S1 steps are 1
Step-by-step is used as final result after negating；If it is 0 to export remainder, without inversion operation directly as final result.For example, such as
It is 2 that fruit, which exports remainder, then represent complementation result it is practical be -2, but after bit wide is negated for 2 binary system remainder, 2 step-by-step
1 is reformed into, this is equivalent to the result for adding a modulus 3 by -2.
The present embodiment is by first calculating the number of the remainder 1 and remainder 2 of binary system signed number x, then passes through 1 He of remainder
2 number tables look-up to obtain the final remainder of signed number x.Money is more saved than directly using % modulus in Verilog programs
Source expense.
Method described herein carries out emulation and design synthesis using Vivado tools, as a result as follows：
The data x for being 49,33,16,6 for bit wide, using the resource overhead ratio of the model taking method newly proposed in Verilog
Directly the resource overhead of % modulus is used to save 46.2%, 41.8%, 65.0%, 85.7% respectively in program.It can be seen that this
Apply for that a kind of modulo operation method of the low overhead proposed is very effective the resource overhead for reducing modulo operation.
The same or similar label correspond to the same or similar components；
Position relationship described in attached drawing is used to only for illustration, should not be understood as the limitation to this patent；
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement etc., should be included in the claims in the present invention made by within the spirit and principle of invention
Protection domain within.
Claims (7)
1. a kind of model taking method of low overhead, which is characterized in that include the following steps：
S1：If binary system signed number x is negative, x is first become into binary system positive number, is then assigned to y；Else if two into
It is positive number to be formed with symbolic number x, then the value of x is directly assigned to y；
S2：The number for counting on the 0th, 2,4,6 etc. the even bits of binary system positive number y 1, is set as m；Same statistics binary system positive number
1 number in 1st, 3,5,7 etc. odd bits is set as n, and wherein m is the number that remainder is 1, and n is the number that remainder is 2；
S3：The number for counting on the 0th, 2,4 etc. the even bits of binary system positive number m 1, is set as a；Count binary system positive number m the 1st,
3, in the odd bits such as 51 number, be set as b, wherein a is the number that remainder is 1, and b is the number that remainder is 2；
S4：The number for counting on the 0th, 2,4 etc. the even bits of binary system positive number n 1, is set as c；Count binary system positive number m the 1st,
3, in the odd bits such as 51 number, be set as d, wherein c is the number that remainder is 2, and d is the number that remainder is 1；
S5：The number that remainder is 1 be a and d's and, be set as e；The number that remainder is 2 be b and c's and, f is set as, according to e's and f
Value can determine remainder, establish a read only memory ROM, and read only memory ROM is corresponding remaining according to the output of the value of e and f
Number；
S6：The remainder of ROM outputs is 2 binary system positive numbers, if input data x is positive number, the remainder for directly exporting ROM
As modulo operation final result, if input data x is negative, modulus is used as after the ROM remainder step-by-steps exported are negated
Operation final result.
2. the model taking method of low overhead according to claim 1, which is characterized in that in the step S1, if binary system
Signed number x is positive number, then the value of x is directly assigned to y, if x is negative, binary number x step-by-steps is negated and are assigned to after adding 1
y。
3. the model taking method of low overhead according to claim 2, which is characterized in that in the step S2, if binary system
It is 1 on the 0th, 2,4,6 etc. the even bits of positive number y, then each corresponding position represents numerical value as 4N, wherein N is 0,1,2,3 etc. whole
Number, 4NIt is 1 to mould M=3 remainders, so the number that it is 1 that m, which is remainder,；
If being 1 in the 1st, 3,5,7 etc. the odd bits of binary system positive number y, each corresponding position represents numerical value as 2*4N, wherein N
For the integers such as 0,1,2,3,2*4NIt is 2 to mould M=3 remainders, so the number that it is 2 that n, which is remainder,.
4. the model taking method of low overhead according to claim 3, which is characterized in that in step S3, since m is remainder 1
Number, so the number that it is 1 that a, which is remainder, b is the number that remainder is 2.
5. the model taking method of low overhead according to claim 4, which is characterized in that in step S4, since n is remainder 2
Number, if the 0th of binary number n the, 2,4, on the even bits such as 6 be 1, each corresponding position represents numerical value as 2*4N, wherein N
For the integers such as 0,1,2,3,2*4NIt is 2 to mould M=3 remainders, so the number that it is 2 that c, which is remainder,；
Due to the number that n is remainder 2, if the 1st of binary number n the, 3,5, in the odd bits such as 7 be 1, each corresponding position generation
Table numerical value is 4N+1, and wherein N is the integers such as 0,1,2,3, and it is the number that remainder is 1 that 4N+1, which is 1, d to mould M=3 remainders,.
6. the model taking method of low overhead according to claim 5, which is characterized in that in step S5, the number that remainder is 1 is
e；The number that remainder is 2 is f；The remainder to 3 complementations, the value correspondence of different e and f can be calculated according to the value of e and f
Different remainders, this correspondence are equivalent to the truth table for the combination logic function for establishing a read only memory ROM.
7. the model taking method of low overhead according to claim 6, which is characterized in that in step S6, the remainder of ROM outputs is
2 binary system positive numbers 0,1,2, if input data x is positive number, the remainder that 0 and ROM is exported using position splicing operator is spelled
It picks up to become the signed number that a highest order is 0, is exported as final result；If input data x is negative,
Remainder is generally also negative, adds 1 to become corresponding negative again after can first negating the ROM remainder step-by-steps exported, is spelled using position
Connecing operator and 1 and this negative are stitched together becomes a highest order for 1 signed number, as final as a result, wherein
If remainder is 0, directly export, without aforesaid operations；
Since the remainder that can be generated to three branches in the fault-tolerant networks based on residue check is compared, and if remainder is negative
Negative can be become positive number to facilitate the comparison between remainder by number plus modulus；Mould is 3, can if input data x is negative
Negated with the remainder step-by-step for exporting ROM, so that it may with obtain negative plus modulus become positive number as a result, wherein if remainder is
0, then it directly exports, without aforesaid operations, if input data x is positive number, directly using the remainder of ROM outputs as knot
Fruit.
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Citations (4)
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|---|---|---|---|---|
| CN102567130A (en) * | 2012-01-06 | 2012-07-11 | 清华大学 | Multi-sampling judgment method for fault-tolerant filtering based on remainder check |
| CN103092729A (en) * | 2013-01-29 | 2013-05-08 | 清华大学 | Fine-adjustment remainder validation fault-tolerant high-pass/band-pass filtering processing method based on input |
| CN103092731A (en) * | 2013-02-01 | 2013-05-08 | 清华大学 | Fine-adjustment remainder validation fault-tolerant low-pass filtering processing method based on input |
| CN101464788B (en) * | 2008-12-31 | 2013-07-31 | 无锡中星微电子有限公司 | Device for checking whether binary number is multiple of three, and checking chip thereof |
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2018
- 2018-03-21 CN CN201810235355.7A patent/CN108549589A/en active Pending
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| CN101464788B (en) * | 2008-12-31 | 2013-07-31 | 无锡中星微电子有限公司 | Device for checking whether binary number is multiple of three, and checking chip thereof |
| CN102567130A (en) * | 2012-01-06 | 2012-07-11 | 清华大学 | Multi-sampling judgment method for fault-tolerant filtering based on remainder check |
| CN103092729A (en) * | 2013-01-29 | 2013-05-08 | 清华大学 | Fine-adjustment remainder validation fault-tolerant high-pass/band-pass filtering processing method based on input |
| CN103092731A (en) * | 2013-02-01 | 2013-05-08 | 清华大学 | Fine-adjustment remainder validation fault-tolerant low-pass filtering processing method based on input |
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Application publication date: 20180918 |