CN108538779A - Dual damascene process method - Google Patents
Dual damascene process method Download PDFInfo
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- CN108538779A CN108538779A CN201810270881.7A CN201810270881A CN108538779A CN 108538779 A CN108538779 A CN 108538779A CN 201810270881 A CN201810270881 A CN 201810270881A CN 108538779 A CN108538779 A CN 108538779A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of dual damascene process methods, including step：Step 1: providing a semiconductor substrate for being formed with bottom metal layer；Step 2: forming NDC layers, NDC layers of thickness setting is more than follow-up secondarily etched consumption；Step 3: sequentially forming the first interlayer film, etching groove stop-layer and the second interlayer film；Step 4: the first photoetching offset plate figure of formation, which defines the forming region of through-hole and etch for the first time, forms through-hole；Step 5: being formed, the second photoetching offset plate figure defines the forming region of top layer metallic layer groove and progress etches obtain top layer metallic layer groove for the second time, and the bottom of through-hole still remains with NDC layers after the completion of etching for the second time；Step 6: the NDC layers that removal via bottoms retain form the double damask structure being formed by stacking by through-hole and top layer metallic layer groove.Energy simplification of flowsheet of the invention, saves process costs and process time；Hedge defect caused by the lithography and etching of photoresist can be eliminated.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of dual damascene (Dual
Damsecene, DD) process.
Background technology
It is the device junction composition in each step of existing method, existing dual damascene process side as shown in Figure 1A to Fig. 1 F
Method includes the following steps：
Step 1: as shown in Figure 1A, providing semi-conductive substrate, being formed with bottom metal layer on the semiconductor substrate
101, between the bottom metal layer 101 isolation have bottom dielectric film 102.
The semiconductor substrate is silicon substrate.
The material of the bottom metal layer 101 is copper.The material of the bottom dielectric film 102 can selective oxidation as needed
Layer or nitration case or other medium with low dielectric constant.
Step 2: as shown in Figure 1A, forming nitrogen doped silicon carbide (N Doped SiC, NDC) layer 103, the NDC layers 103
As the barrier layer that the bottom metal layer 101 diffuses up, usual thickness is set as
Step 3: as shown in Figure 1A, the first interlayer film 104, etching groove are sequentially formed on the surface of the NDC layers 103
Stop-layer 105, the second interlayer film 106 and darc layer 107.
In general, the material of first interlayer film 104 is oxidation film.First interlayer film 104 uses pecvd process shape
At.The material of second interlayer film 106 is oxidation film.Second interlayer film 106 is formed using pecvd process.The ditch
The material of groove etched stop-layer 105 is silicon nitride.The thickness of the etching groove stop-layer 105 isFirst interlayer
The thickness of film 104 isThe thickness of second interlayer film 106 isThe first thickness isDescribed
Two thickness are
The material of the darc layer 107 is SiON, and thickness is
Step 4: as shown in Figure 1A, carrying out first time photoetching process and forming the first photoetching offset plate figure 108, first light
Photoresist figure 108 defines the forming region of through-hole 109.
As shown in Figure 1B, it is mask successively to second interlayer film 106, described with first photoetching offset plate figure 108
Etching groove stop-layer 105 and first interlayer film 104 carry out etching for the first time and form the through-hole 109, the through-hole 109
Bottom be located in the corresponding bottom metal layers.NDC layers 103 can be consumed part thickness described in the first time etching
Degree.
Step 5: as shown in Figure 1B, removing first photoetching offset plate figure 108 and the darc layer 107.
The formation on barrier layer is performed etching later, and forming step includes：
Step 51, as shown in Figure 1 C, coating photoresist 110.
Step 52, as shown in figure iD to photoresist 110 carve, and returns photoresist 110 after carving and is only filled in through-hole 109
Bottom.
Step 6: as referring to figure 1E, carrying out second of photoetching process and forming the second photoetching offset plate figure 111, second light
Photoresist figure 111 defines the forming region of the top layer metallic layer groove 112.
As shown in fig. 1F, it is mask with first photoetching offset plate figure 108 and with the etching groove stop-layer 105 is
Stop-layer carries out second of etching to second interlayer film 106 and obtains the top layer metallic layer groove 112.
Step 7: second of etching needs to remove photoresist 110 after completing, 109 bottom of through-hole is being removed later
The remaining NDC layers 103.Eventually form be formed by stacking by the through-hole 109 and the top layer metallic layer groove 112 it is double big
Ma Shige structures.
Further include being formed simultaneously the via metal and top in double damask structure filling metal after step 7
Portion's metal layer, the via metal realize the connection between the metal layer at top and the bottom metal layers.
From the foregoing, it will be observed that need to form the etching barrier layer being made of photoresist 110 using multiple steps in the prior art, with
It prevents the bottom metal layer 101 of 109 bottom of through-hole described in second of etching to be exposed, and subsequently also needs to going
Except photoresist 110, process costs are higher, and the process time is also longer.In addition, the remaining light formed using lithography and etching technique
The film thickness of photoresist 110 is not easy to control, has hedge defect.
Invention content
Technical problem to be solved by the invention is to provide a kind of dual damascene process method, can simplification of flowsheet,
Save process costs and process time；Hedge defect caused by the lithography and etching of photoresist can also be eliminated.
In order to solve the above technical problems, dual damascene process method provided by the invention includes the following steps：
Step 1: providing semi-conductive substrate, it is formed with bottom metal layer, the bottom gold on the semiconductor substrate
Isolation has bottom dielectric film between belonging to layer.
Step 2: forming NDC layers, following setting is done to NDC layers of the thickness：
NDC layers of the thickness is more than the first thickness needed for the barrier layer diffused up as the bottom metal layer.
Second thickness after NDC layers of the thickness increases and increases on the basis of first thickness is more than follow-up first time
The thickness consumed in etching and second of etching process.
Step 3: sequentially forming the first interlayer film, etching groove stop-layer and the second interlayer on NDC layers of the surface
Film.
Step 4: carrying out first time photoetching process forms the first photoetching offset plate figure, first photoetching offset plate figure defines
The forming region of through-hole successively stops second interlayer film, the etching groove using first photoetching offset plate figure as mask
Only layer and first interlayer film carry out etching for the first time and form the through-hole, and the bottom of the through-hole is located at the corresponding bottom
On portion's metal layer.
Step 5: removal first photoetching offset plate figure, carries out second of photoetching process and forms the second photoetching offset plate figure, institute
The forming region that the second photoetching offset plate figure defines the top layer metallic layer groove is stated, using second photoetching offset plate figure as mask
And second of etching is carried out to second interlayer film as stop-layer using the etching groove stop-layer and obtains the top layer gold
Belong to layer groove；The through-hole is located at the bottom of the top layer metallic layer groove, and NDC layers of the thickness is in the primary etching
It can be consumed in being etched with described second and the thickness consumed makes described second less than the second thickness after the completion of etching
The bottom of the through-hole still remains with the NDC layers of segment thickness.
Step 6: removing the NDC layers of the via bottoms reservation and exposing the corresponding bottom metal layers, shape
At the double damask structure being formed by stacking by the through-hole and the top layer metallic layer groove.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the material of the bottom metal layer is copper.
A further improvement is that before forming first photoetching offset plate figure further including in the second layer in step 4
Between film surface formed darc layer the step of；The darc layer removes after first photoetching offset plate figure removal.
A further improvement is that the material of the darc layer is SiON.
A further improvement is that the material of first interlayer film is oxidation film.
A further improvement is that first interlayer film is formed using pecvd process.
A further improvement is that the material of second interlayer film is oxidation film.
A further improvement is that second interlayer film is formed using pecvd process.
A further improvement is that the material of the etching groove stop-layer is silicon nitride.
A further improvement is that the thickness of the etching groove stop-layer is
A further improvement is that the thickness of first interlayer film is
A further improvement is that the thickness of second interlayer film is
A further improvement is that the first thickness isThe second thickness is
A further improvement is that further including being formed simultaneously institute in double damask structure filling metal after step 6
Via metal and metal layer at top are stated, the via metal realizes the company between the metal layer at top and the bottom metal layers
It connects.
By having done special setting to NDC layers of thickness, NDC layer thickness not only more meets described in conduct the present invention
The barrier layer i.e. first thickness of required thickness that bottom metal layer diffuses up is configured, and is the base in first thickness
Increased on plinth, and the second thickness after increase is more than follow-up etching for the first time i.e. via etch and second of etching i.e. top
The thickness that layer metal layer groove consumes in the process, namely NDC layers of the invention are simultaneously also as the etching resistance in second of etching
Barrier is thus avoided that the etching resistance for being independently formed in being etched at second and through-hole bottom metal layer being protected not influenced by etching
Barrier, so namely be avoided that using independently forming required process time and process costs when etching barrier layer, technique at
This includes then raw materials technology cost and in order to complete the corresponding required equipment cost of technique, the process time also belong to technique at
This part；The etching barrier layer usually independently formed is to return the process shape carved using photoresist coating plus photoresist
At the present invention can save photoresist coating simultaneously in this way and photoresist returns and carves this twice technique, so as to reduce process costs
With the saving process time.In short, the present invention can simplification of flowsheet, saving process costs and process time.
The present invention need not form in second of etching etching barrier layer in through-hole using the lithography and etching of photoresist；
So hedge defect caused by the lithography and etching of photoresist can also be eliminated.
The present invention can be suitably used in 8 times of dual damascene (8XDD) techniques.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Figure 1A-Fig. 1 F are the structure charts in each step of existing dual damascene process method；
Fig. 2 is the flow chart of present invention method；
Fig. 3 A- Fig. 3 D are the device junction compositions in each step of present invention method.
Specific implementation mode
As shown in Fig. 2, being the flow chart of present invention method；It is the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 D
Device junction composition in each step of method, dual damascene process method of the embodiment of the present invention include the following steps：
Step 1: as shown in Figure 3A, providing semi-conductive substrate, being formed with bottom metal layer on the semiconductor substrate
1, between the bottom metal layer 1 isolation have bottom dielectric film 2.
The semiconductor substrate is silicon substrate.
The material of the bottom metal layer 1 is copper.The material of the bottom dielectric film 2 can as needed selective oxidation layer or
Nitration case or other medium with low dielectric constant.
Step 2: as shown in Figure 3A, forming NDC layers 3, following setting being done to the thickness of the NDC layers 3：
The thickness of the NDC layers 3 is more than the first thickness needed for the barrier layer diffused up as the bottom metal layer 1
Degree.
Second thickness after the thickness of the NDC layers 3 increases and increases on the basis of first thickness is more than follow-up first
The thickness consumed in secondary etching and second of etching process.
Step 3: as shown in Figure 3A, the first interlayer film 4, etching groove stopping are sequentially formed on the surface of the NDC layers 3
Layer 5 and the second interlayer film 6.
In the embodiment of the present invention, the material of first interlayer film 4 is oxidation film.First interlayer film 4 uses PECVD
Technique is formed.The material of second interlayer film 6 is oxidation film.Second interlayer film 6 is formed using pecvd process.It is described
The material of etching groove stop-layer 5 is silicon nitride.
For better illustrate the embodiment of the present invention, some design parameters are as follows, but these parameters are not constituted
Limitation to the embodiment of the present invention：The thickness of the etching groove stop-layer 5 isThe thickness of first interlayer film 4 isThe thickness of second interlayer film 6 isThe first thickness isThe second thickness is
Step 4: as shown in Figure 3A, carrying out first time photoetching process and forming the first photoetching offset plate figure 8, first photoetching
Glue pattern 8 defines the forming region of through-hole 9.
Further include in second interlayer film 6 before forming first photoetching offset plate figure 8 in the embodiment of the present invention
Surface forms the step of darc layer 7；The darc layer 7 removes after first photoetching offset plate figure 8 removal.The darc layer
7 material is SiON.The thickness of the darc layer 7 is
As shown in Figure 3B, with first photoetching offset plate figure 8 be mask successively to second interlayer film 6, the groove
Etching stop layer 5 and first interlayer film 4 carry out etching for the first time and form the through-hole 9, and the bottom of the through-hole 9 is located at pair
In the bottom metal layers answered.NDC layers 3 can be consumed segment thickness described in the first time etching.
Step 5: as shown in Figure 3 C, removing first photoetching offset plate figure 8, carries out second of photoetching process and form second
Photoetching offset plate figure 10, second photoetching offset plate figure 10 define the forming region of the top layer metallic layer groove 11.
As shown in Figure 3D, with second photoetching offset plate figure 10 be mask and with the etching groove stop-layer 5 be stop
Only layer carries out second of etching to second interlayer film 6 and obtains the top layer metallic layer groove 11；The through-hole 9 is located at described
The thickness of the bottom of top layer metallic layer groove 11, the NDC layers 3 understands quilt in the primary etching and in etching for described second
The thickness of consumption and consumption, which is less than the second thickness, makes the bottom of the through-hole 9 after the completion of etching still retain described second
There are the NDC layers 3 of segment thickness.
Step 6: remove the NDC layers 3 of 9 bottom of through-hole reservation and expose the corresponding bottom metal layers,
Form the double damask structure being formed by stacking by the through-hole 9 and the top layer metallic layer groove 11.
Further include being formed simultaneously the via metal and top in double damask structure filling metal after step 6
Portion's metal layer, the via metal realize the connection between the metal layer at top and the bottom metal layers.
The embodiment of the present invention has done special setting by the thickness to NDC layers 3, and 3 thickness of NDC layers not only more meets
The barrier layer i.e. first thickness of required thickness diffused up as the bottom metal layer 1 is configured, and is
Increased on the basis of one thickness, and it is the etching of through-hole 9 and that the second thickness after increasing, which is more than follow-up etching for the first time,
The thickness consumed during secondarily etched i.e. top layer metallic layer groove 11, namely the NDC layers 3 of the present invention are also used as second simultaneously
Etching barrier layer in etching, be thus avoided that in being etched second independently form protect 9 bottom metal layer 1 of through-hole not by
Etch the etching barrier layer influenced, so namely be avoided that using independently form when etching barrier layer the required process time and
Process costs, process costs include then raw materials technology cost and in order to complete the corresponding required equipment cost of technique, technique
Time also belongs to a part for process costs；The etching barrier layer usually independently formed is returned using photoresist coating plus photoresist
The process at quarter is formed, and such embodiment of the present invention can save photoresist coating simultaneously and photoresist returns and carves this twice work
Skill, so as to reduce process costs and save the process time.In short, energy simplification of flowsheet of the embodiment of the present invention, saves technique
Cost and process time.
The embodiment of the present invention need not be etched to be formed in second of etching in through-hole using the lithography and etching of photoresist
Barrier layer；So hedge defect caused by the lithography and etching of photoresist can also be eliminated.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of dual damascene process method, which is characterized in that include the following steps：
Step 1: providing semi-conductive substrate, it is formed with bottom metal layer, the bottom metal layer on the semiconductor substrate
Between isolation have bottom dielectric film；
Step 2: forming NDC layers, following setting is done to NDC layers of the thickness：
NDC layers of the thickness is more than the first thickness needed for the barrier layer diffused up as the bottom metal layer；
Second thickness after NDC layers of the thickness increases and increases on the basis of first thickness is more than follow-up etching for the first time
With the thickness consumed in second of etching process；
Step 3: sequentially forming the first interlayer film, etching groove stop-layer and the second interlayer film on NDC layers of the surface；
Step 4: carrying out first time photoetching process forms the first photoetching offset plate figure, first photoetching offset plate figure defines through-hole
Forming region, be mask successively to second interlayer film, the etching groove stop-layer using first photoetching offset plate figure
Etching for the first time is carried out with first interlayer film and forms the through-hole, and the bottom of the through-hole is located at the corresponding bottom gold
Belong on layer；
Step 5: removal first photoetching offset plate figure, carries out second of photoetching process and form the second photoetching offset plate figure, described the
Two photoetching offset plate figures define the forming region of the top layer metallic layer groove, using second photoetching offset plate figure as mask and
Second of etching is carried out to second interlayer film as stop-layer using the etching groove stop-layer and obtains the top layer metallic layer
Groove；The through-hole is located at the bottom of the top layer metallic layer groove, and NDC layers of the thickness is in the primary etching and institute
State can be consumed in second of etching and the thickness that consumes be less than the second thickness make it is described after the completion of second of etching
The bottom of through-hole still remains with the NDC layers of segment thickness；
Step 6: remove the NDC layer that the via bottoms retain and will the corresponding bottom metal layers exposure, formation by
The double damask structure that the through-hole and the top layer metallic layer groove are formed by stacking.
2. dual damascene process method as described in claim 1, it is characterised in that：The semiconductor substrate is silicon substrate.
3. dual damascene process method as described in claim 1, it is characterised in that：The material of the bottom metal layer is
Copper.
4. dual damascene process method as described in claim 1, it is characterised in that：First light is being formed in step 4
Further include the steps that forming darc layer on the surface of second interlayer film before photoresist figure；The darc layer is described first
It is removed after photoetching offset plate figure removal.
5. dual damascene process method as claimed in claim 4, it is characterised in that：The material of the darc layer is SiON.
6. dual damascene process method as described in claim 1, it is characterised in that：The material of first interlayer film is oxygen
Change film.
7. dual damascene process method as claimed in claim 6, it is characterised in that：First interlayer film uses PECVD
Technique is formed.
8. dual damascene process method as described in claim 1, it is characterised in that：The material of second interlayer film is oxygen
Change film.
9. dual damascene process method as claimed in claim 8, it is characterised in that：Second interlayer film uses PECVD
Technique is formed.
10. dual damascene process method as described in claim 1, it is characterised in that：The material of the etching groove stop-layer
Material is silicon nitride.
11. dual damascene process method as claimed in claim 10, it is characterised in that：The thickness of the etching groove stop-layer
Degree is
12. dual damascene process method as claimed in claim 6, it is characterised in that：The thickness of first interlayer film is
13. dual damascene process method as claimed in claim 8, it is characterised in that：The thickness of second interlayer film is
14. dual damascene process method as described in claim 1, it is characterised in that：The first thickness is It is described
Second thickness is
15. dual damascene process method as described in claim 1, it is characterised in that：Further include described after step 6
Double damask structure filling metal is formed simultaneously the via metal and metal layer at top, and the via metal realizes the top
Connection between portion's metal layer and the bottom metal layers.
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| CN201810270881.7A CN108538779A (en) | 2018-03-29 | 2018-03-29 | Dual damascene process method |
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| CN201810270881.7A CN108538779A (en) | 2018-03-29 | 2018-03-29 | Dual damascene process method |
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ID=63482435
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112435923A (en) * | 2020-11-27 | 2021-03-02 | 华虹半导体(无锡)有限公司 | Etching process method for multi-product mixed production |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044487A (en) * | 2009-10-22 | 2011-05-04 | 上海华虹Nec电子有限公司 | Tungsten dual-damascene process |
| CN102610563A (en) * | 2012-04-06 | 2012-07-25 | 上海集成电路研发中心有限公司 | Method for preparing copper dual damascene structure |
| CN103066013A (en) * | 2012-11-02 | 2013-04-24 | 上海华力微电子有限公司 | Method of improving etching morphology of dual damascene structure dielectric film |
| CN105742227A (en) * | 2014-12-08 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for improving profiles of through hole and trench in dielectric layer |
-
2018
- 2018-03-29 CN CN201810270881.7A patent/CN108538779A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044487A (en) * | 2009-10-22 | 2011-05-04 | 上海华虹Nec电子有限公司 | Tungsten dual-damascene process |
| CN102610563A (en) * | 2012-04-06 | 2012-07-25 | 上海集成电路研发中心有限公司 | Method for preparing copper dual damascene structure |
| CN103066013A (en) * | 2012-11-02 | 2013-04-24 | 上海华力微电子有限公司 | Method of improving etching morphology of dual damascene structure dielectric film |
| CN105742227A (en) * | 2014-12-08 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for improving profiles of through hole and trench in dielectric layer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112435923A (en) * | 2020-11-27 | 2021-03-02 | 华虹半导体(无锡)有限公司 | Etching process method for multi-product mixed production |
| CN112435923B (en) * | 2020-11-27 | 2022-08-16 | 华虹半导体(无锡)有限公司 | Etching process method for multi-product mixed production |
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