CN108538725A - Thin film transistor (TFT) and its manufacturing method - Google Patents
Thin film transistor (TFT) and its manufacturing method Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 81
- 239000010408 film Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 238000012545 processing Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 243
- 239000012212 insulator Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000010276 construction Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 description 32
- 239000002184 metal Substances 0.000 description 32
- 150000002739 metals Chemical class 0.000 description 17
- 230000008569 process Effects 0.000 description 14
- 230000007704 transition Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 238000012216 screening Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000009194 climbing Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229910016027 MoTi Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The application is to be related to the technical field of thin film transistor (TFT) about a kind of thin film transistor (TFT) and its manufacturing method.The technical solution mainly used for：Method for fabricating thin film transistor comprising：Active layer, gate insulating layer and grid layer are sequentially formed on substrate；Photoresist and photoetching are coated on grid layer, and processing is patterned to grid layer and gate insulating layer, obtains grid；Stripping photoresist sputters to form conductive film layer, and carries out graphical treatment using the autoregistration of grid to gate patterns surface and active layer surface；Eventually form protection film layer, and opening contact hole.Present application addresses the problems that grid is easy to happen oxidation and active layer conductorization difficulty.
Description
Technical field
This application involves the technical fields of thin film transistor (TFT), more particularly to a kind of thin film transistor (TFT) and its manufacturing method.
Background technology
Thin film transistor (TFT) (Thin Film Transistor, TFT) is the important component of panel display apparatus.Film
Transistor may be formed on glass substrate or plastic base, and such as LCD, OLED are used in usually as switch block and driving part
On equal panel display apparatus.Wherein, the thin film transistor (TFT) of top-gated coplanar structure has compared to the thin film transistor (TFT) of traditional structure
There is relatively small parasitic capacitance, the main function elements of large scale OLED can be used as.
But there are certain defects during manufacture for the thin film transistor (TFT) of above structure, firstly, there are grid oxygen
The problem of change, needs to use vapor deposition mode and high-temperature technology, grid is caused to hold that is, when gate upper surface deposits protective layer
Oxidizable, the especially Cu oxidations of grid cause the risk that there is broken string in SD metal routings and Gate cabling cross-lines region, make
Backboard yield is obtained to decline；Secondly there are the problem of active layer conductorization difficulty, needed in the prior art using gas such as He, Ar, H2
The plasma of body carries out active layer conductor under relatively high power, and technology difficulty is big, and in follow-up PECVD and high annealing work
There are certain declines for conductor effect after skill, therefore the regions S/D may still have larger dead resistance, lead to device
Ion and field-effect mobility reduce.
So needing further to improve in view of the above technical problems.
Invention content
The main purpose of the application is, provides a kind of new structural thin film transistor (TFT) and its manufacturing method, to be solved
Certainly the technical issues of is can to solve the problems, such as that grid is easy to happen oxidation and active layer conductorization is difficult.
The purpose of the application and its technical problem is solved using following technical scheme to realize.It is proposed according to the application
A kind of method for fabricating thin film transistor comprising step：
Active layer, gate insulating layer and grid layer are sequentially formed on substrate；
Photoresist and photoetching are coated on grid layer, and processing is patterned to grid layer and gate insulating layer, obtains grid
Pole；
Stripping photoresist sputters to form conductive film using the autoregistration of grid to gate patterns surface and active layer surface
Layer, and carry out graphical treatment；
Eventually form protection film layer, and opening contact hole.
It the purpose of the application and solves its technical problem following technical measures also can be used to further realize.
Preferably, method for fabricating thin film transistor above-mentioned utilizes the autoregistration of grid wherein carrying out stripping photoresist
It sputters to form conductive film layer to gate patterns surface and active layer surface, and before carrying out graphical treatment, the method is also wrapped
It includes：
Over etching is carried out to the gate insulating layer, by the gate insulating layer below the grid to the grid
The 1/5-1/3 distances for carving the grid length are crossed in pole lower central position.
Preferably, method for fabricating thin film transistor above-mentioned, wherein crossing the distance carved is equal to the 1/4 of the grid length.
Preferably, method for fabricating thin film transistor above-mentioned utilizes the autoregistration of grid wherein carrying out stripping photoresist
It sputters to form conductive film layer to gate patterns surface and active layer surface, and after carrying out graphical treatment, the method is also wrapped：
Organic insulation is integrally coated on the surface being made of the gate insulating layer, grid and the conductive film layer
Layer；And it is exposed development using the grid as mask.
Preferably, method for fabricating thin film transistor above-mentioned, wherein the grid layer is MoNb layers, Cu layers and MoNb layers
The laminated construction of lamination setting successively.
Preferably, method for fabricating thin film transistor above-mentioned is set wherein the grid layer stacks gradually for MoNb layers, Cu layers
The laminated construction set, described Cu layers relative to MoNb layers far from the active layer.
Preferably, method for fabricating thin film transistor above-mentioned, wherein described formed at protection film layer by the method for coating；
Or, the protection film layer is formed by the method for deposition.
Preferably, method for fabricating thin film transistor above-mentioned, wherein being formed before active layer on substrate, the method is also
Including：
Light shield layer and insulating layer are sequentially formed on substrate.
In addition, the purpose of the application and solving its technical problem and also being realized using following technical scheme.According to the application
A kind of thin film transistor (TFT) proposed comprising：
It is counted from substrate, includes active layer, gate insulating layer, grid successively；
Conductive film layer, the conductive film layer overlays on the gate surface, and is thrown positioned at the grid lower gate figure
The active layer surface of shadow both sides；
Protection film layer, the protection film layer are constituted the active layer, gate insulating layer, grid and conductive film layer
Whole covering.
It the purpose of the application and solves its technical problem following technical measures also can be used to further realize.
Preferably, thin film transistor (TFT) above-mentioned further includes：
Organic insulator, the organic insulator are arranged in the lower section that the grid projects, and are located at the gate insulating layer
Between conductive film layer.
By above-mentioned technical proposal, the application thin film transistor (TFT) and its manufacturing method at least have following advantages：
Include using method for fabricating thin film transistor provided by the present application：" using the autoregistration of gate patterns to grid figure
Shape surface and active layer surface sputter to form conductive film layer, and carry out graphical treatment " the step for, which can be in grid
The conductive film layer of formation is sputtered under the self aligned mode of figure, can directly be formed S/D figures, that is, be formed signal line graph,
And then the step of saving this complex process of active layer conductorization, and can effectively reduce LDD region domain, that is, it reduces in raceway groove
In near drain electrode the low-doped drain region that is arranged, and then dead resistance can be reduced, improve ON state current, and electric current is not
It can decay because of subsequent high temperature processes；And since S/D figures are that gate patterns are utilized as mask, pass through autoregistration
It is formed, it is thus eliminated that due to the regions Offset that the gate insulating layer etching angle of gradient generates, that is, offsets region, improve ON state
Electric current, and remain the small advantage of the coplanar thin film transistor (TFT) parasitic capacitance of top-gated；In addition, being existed using this method step deposition
The conductive film layer in the regions S/D, can be used with transition zone, that is, is retained subsequent making S/D metal shape processes, deposited in this way
S/D metals shape can with the good Ohmic contact of the transition zone, avoid S/D metals and active layer be in direct contact and generate compared with
Big contact resistance, and stability is preferable；Finally, this method step makes the top of grid cover one layer of conductive film layer, can keep away
The both sides for exempting from gate metal aoxidize in subsequent high temperature processes, and when preventing the etching through hole above gate patterns due to
Spending quarter makes the metal of grid be exposed, such as Cu metals are exposed, and aoxidize.So using method provided by the present application
The yield of thin film transistor (TFT) can be improved to manufacture thin film transistor (TFT), while this method can also have as manufacture backboard, same energy
Enough improve the yield of backboard.
Above description is only the general introduction of technical scheme, in order to better understand the technological means of the application,
And can be implemented in accordance with the contents of the specification, below with the preferred embodiment of the application and coordinate attached drawing be described in detail as after.
Description of the drawings
Fig. 1 is a kind of flow diagram for method for fabricating thin film transistor that embodiments herein one provides；
Fig. 2 is the flow diagram for another method for fabricating thin film transistor that embodiments herein one provides；
Fig. 3 is a kind of thin-film transistor structure schematic diagram that embodiments herein provides；
Fig. 4 is a kind of another thin-film transistor structure schematic diagram that embodiments herein provides；
Fig. 5 is a kind of another thin-film transistor structure schematic diagram that embodiments herein provides；
Fig. 6 is a kind of another thin-film transistor structure schematic diagram that embodiments herein provides；.
Specific implementation mode
Further to illustrate that the application is to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Attached drawing and preferred embodiment, to the thin film transistor (TFT) and its manufacturing method proposed according to the application, specific implementation mode, knot
Structure, feature and its effect are described in detail as after.In the following description, what different " embodiment " or " embodiment " referred to differs
Surely it is the same embodiment.In addition, the special characteristic, structure or feature in one or more embodiments can be by any suitable form group
It closes.
Embodiment one
As shown in Figure 1, a kind of method for fabricating thin film transistor that embodiments herein one proposes, step include：
101, active layer, gate insulating layer and grid layer are sequentially formed on substrate.
Specifically, glass substrate, which may be used, in substrate can also use transparent plastic substrate, i.e. thin film transistor (TFT) can be
It is formed on substrate, the material of active layer can include a-IGZO, ZnON, IZTO, a-Si, p-Si, wait various common used materials, active
Layer can pass through physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) method, plasma enhanced chemical
Vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method or use ion splash
It penetrates coating method to shape on substrate, active layer can be patterned by one of mask technique, form scheduled figure in base
In plate surface；Gate insulating layer can directly use thin film transistor (TFT) in common insulating materials, can by deposition or
The mode of coating is formed, and the thickness of gate insulating layer can need to be configured according to specific performance；Grid layer can be packet
Grid layer containing Cu metals or AI metals, such as can be the grid layer of laminated construction, i.e., it is carried out by Cu and Mo or MoNB
Lamination is arranged, and can also be that Al and AlNd or MoTi carries out lamination setting.
102, photoresist and photoetching are coated on grid layer, and processing is patterned to grid layer and gate insulating layer, is obtained
To grid.
Specifically, grid layer and gate insulating layer can carry out mask techniques by using gate patterns as mask, i.e.,
The graphical of grid and gate insulating layer is carried out by mask techniques, and then obtains grid and between active layer and grid
Gate insulating layer structure, wherein mask techniques are more ripe technique, and the application does not repeat.
103, stripping photoresist sputters to be formed to gate patterns surface and active layer surface using the autoregistration of gate patterns
Conductive film layer, and carry out graphical treatment.
Specifically, after stripping photoresist, gate patterns all appear, and are carried out by way of being directed at gate patterns at this time
Conductive film layer is sputtered, such conductive film layer is molded over the surface of grid, and is molded over gate patterns and is projected in after active layer
The position of both sides is projected, i.e. gate surface covers conductive film layer, the regions S/D of active layer, and the conduction at above-mentioned two position
Film layer is not connected to, so can play the purpose of protection gate metal positioned at the conductive film layer of gate surface, and is located at active layer
The conductive film layer in the regions S/D can be used as S/D metals, i.e., used as signal wire；In addition, material packet used in conductive film layer
Include but be not limited to common metal material, such as Ag, Cu, Al, Mo etc. or multiple layer metal such as Mo/Cu/Mo etc. or above-mentioned metal
Alloy material, such as AlNd, MoNb or various TCO materials such as ITO, AZO, IFO etc. can also be the heap that metal and TCO are formed
Stack architecture such as ITO/Ag/ITO etc.；The thickness of conductive film layer can need specifically to be arranged according to specific performance；And it should
Step can be used in existing production technology, i.e., regard the conductive film layer being arranged by the application step 103 as transition zone,
As the connecting material for being subsequently formed S/D metals, the S/D metals manufactured by existing production technology is made to avoid directly and active layer
Contact, reduces contact resistance between the two.
104, protection film layer, and opening contact hole are eventually formed.
Specifically, the step is to be formed by the entire outer surface covering layer protecting film of thin film transistor (TFT) in above-mentioned steps
Layer, the protection film layer can be PVX or ILD layer, and the thickness of this layer can require specifically to be set according to specific protection class
It sets；Contact hole can be specifically arranged according to the structural requirement of thin film transistor (TFT).
Include using method for fabricating thin film transistor provided by the present application：" using the autoregistration of gate patterns to grid figure
Shape surface and active layer surface sputter to form conductive film layer, and carry out graphical treatment " the step for, which can be in grid
The conductive film layer of formation is sputtered under the self aligned mode of figure, can directly be formed S/D figures, that is, be formed signal line graph,
And then the step of saving this complex process of active layer conductorization, and can effectively reduce LDD region domain, that is, it reduces in raceway groove
In near drain electrode the low-doped drain region that is arranged, and then dead resistance can be reduced, improve ON state current, and electric current is not
It can decay because of subsequent high temperature processes；And since S/D figures are that gate patterns are utilized as mask, pass through autoregistration
It is formed, it is thus eliminated that due to the regions Offset that the gate insulating layer etching angle of gradient generates, that is, offsets region, improve ON state
Electric current, and remain the small advantage of the coplanar thin film transistor (TFT) parasitic capacitance of top-gated；In addition, being existed using this method step deposition
The conductive film layer in the regions S/D, can be used with transition zone, that is, is retained subsequent making S/D metal shape processes, deposited in this way
S/D metals shape can with the good Ohmic contact of the transition zone, avoid S/D metals and active layer be in direct contact and generate compared with
Big contact resistance, and stability is preferable；Finally, this method step makes the top of grid cover one layer of conductive film layer, can keep away
The both sides for exempting from gate metal aoxidize in subsequent high temperature processes, and when preventing the etching through hole above gate patterns due to
Spending quarter makes the metal of grid be exposed, such as Cu metals are exposed, and aoxidize.So using method provided by the present application
The yield of thin film transistor (TFT) can be improved to manufacture thin film transistor (TFT), while this method can also have as manufacture backboard, same energy
Enough improve the yield of backboard.
Above-mentioned method provided by the present application can also be used to manufacture backboard.The thin film transistor (TFT) that the above method manufactures
Structure is as shown in figure 3, the corresponding number of wherein each structure is：Substrate 1, active layer 2, gate insulating layer 3, grid 4, conductive film layer
5, protection film layer 6.
As shown in Fig. 2, a kind of method for fabricating thin film transistor that another embodiment of the application proposes, step packet
It includes：
201, active layer, gate insulating layer and grid layer are sequentially formed on substrate.
202, photoresist and photoetching are coated on grid layer, and processing is patterned to grid layer and gate insulating layer, is obtained
To grid.
Specifically, the explanation of step 201 and step 202 can refer to the step 101 of the above method and step 102 carries out,
Details are not described herein again.
203, over etching is carried out to the gate insulating layer, by the gate insulating layer below the grid to institute
It states grid lower central position and crosses the 1/5-1/3 distances for carving the grid length.
Specifically, the lower section of grid was carried out quarter for realizing grid and the gate insulating layer of active layer insulated separation
Erosion, and crossing for gate insulating layer is carried out by wet-etching technique and is carved, the gate insulating layer crossed after carving is retracted to the center of gate bottom,
The distance of retraction was to carve distance to need to control the 1/5-1/3 distances in grid length, to ensure the gate insulating layer after carving
Grid can be effectively supported, the optimum distance that wherein it's quarter pasts gate insulating layer is the 1/4 of the grid length.
204, stripping photoresist sputters to be formed to gate patterns surface and active layer surface using the autoregistration of gate patterns
Conductive film layer, and carry out graphical treatment.
It is carried out specifically, the step can refer to above method step 103, details are not described herein again.
205, it is integrally coated on the surface being made of the gate insulating layer, grid and the conductive film layer organic exhausted
Edge layer；And it is exposed development using the grid as mask.
Specifically, the step needs to ensure that organic insulator is carried out by coating method in force, it is organic in this way
Coating can enter gate insulating layer and cross the space carved and generated later, this is spatially located at below grid, gate insulating layer, conduction
The space that film layer and active layer are constituted.
206, protection film layer, and opening contact hole are eventually formed.
Specifically, the step is to be formed by the entire outer surface covering layer protecting film of thin film transistor (TFT) in above-mentioned steps
Layer, the protection film layer can be PVX or ILD layer, and the thickness of this layer can require specifically to be set according to specific protection class
It sets；Contact hole can be specifically arranged according to the structural requirement of thin film transistor (TFT).
Include using method for fabricating thin film transistor provided by the present application：" using the autoregistration of gate patterns to grid figure
Shape surface and active layer surface sputter to form conductive film layer, and carry out graphical treatment " the step for, which can be in grid
The conductive film layer of formation is sputtered under the self aligned mode of figure, can directly be formed S/D figures, that is, be formed signal line graph,
And then the step of saving this complex process of active layer conductorization, and can effectively reduce LDD region domain, that is, it reduces in raceway groove
In near drain electrode the low-doped drain region that is arranged, and then dead resistance can be reduced, improve ON state current, and electric current is not
It can decay because of subsequent high temperature processes；And since S/D figures are that gate patterns are utilized as mask, pass through autoregistration
It is formed, it is thus eliminated that due to the regions Offset that the gate insulating layer etching angle of gradient generates, that is, offsets region, improve ON state
Electric current, and remain the small advantage of the coplanar thin film transistor (TFT) parasitic capacitance of top-gated；In addition, being existed using this method step deposition
The conductive film layer in the regions S/D, can be used with transition zone, that is, is retained subsequent making S/D metal shape processes, deposited in this way
S/D metals shape can with the good Ohmic contact of the transition zone, avoid S/D metals and active layer be in direct contact and generate compared with
Big contact resistance, and stability is preferable；Finally, this method step makes the top of grid cover one layer of conductive film layer, can keep away
The both sides for exempting from gate metal aoxidize in subsequent high temperature processes, and when preventing the etching through hole above gate patterns due to
Spending quarter makes the metal of grid be exposed, such as Cu metals are exposed, and aoxidize.So using method provided by the present application
The yield of thin film transistor (TFT) can be improved to manufacture thin film transistor (TFT), while this method can also have as manufacture backboard, same energy
Enough improve the yield of backboard.
In addition, further including using method for fabricating thin film transistor provided by the present application：Step " to the gate insulating layer into
The gate insulating layer below the grid is crossed to grid lower central position and carves the grid by row over etching
The 1/5-1/3 distances of length " and step are " on the surface being made of the gate insulating layer, grid and the conductive film layer
Whole coating organic insulator；And it is exposed development using the grid as mask." by set by above-mentioned two step
Organic insulator, follow-up setting protection film layer can be improved in the climbing pattern for crossing quarter place, reduce at this broken string with it is short
The probability on road；In addition, it can be opaque or coloured light screening material that filling gate insulating layer, which crosses the organic insulating material at quarter,
It can play the role of improving active layer shading the back bias voltage light durability (NBIS) of thin film transistor (TFT).
Above-mentioned method provided by the present application can also be used to manufacture backboard.The thin film transistor (TFT) that the above method manufactures
Structure is as shown in figure 4, the corresponding number of wherein each structure is：Substrate 1, active layer 2, gate insulating layer 3, grid 4, conductive film layer
5, protection film layer 6, organic insulator 7.
In the above method is embodied, the grid layer can be MoNb layers, Cu layers and MoNb layers successively lamination set
The laminated construction set；Alternatively, the grid layer is MoNb layers, the Cu layers of laminated construction being cascading, described Cu layers opposite
In MoNb layers far from the active layer.
Further, described to be formed by the method for coating at protection film layer；Or, the side that the protection film layer passes through deposition
Method is formed.
Specifically, the specific of protection film layer can be selected at mode according to the different situations of above two embodiment,
The wherein coating of main body and deposition modeling mode can refer to the prior art, be not repeated herein.
In specific implementation, it is formed before active layer on substrate, the method further includes：Screening is sequentially formed on substrate
Photosphere and insulating layer.
Specifically, this method and step can be arranged in above-mentioned two specific embodiment in any one, and the above method
It is used directly for manufacture backboard, so the setting of light shield layer can increase the display effect of backboard.
Wherein, the structure of the thin film transistor (TFT) manufactured by this method is as shown in Figure 5 or Figure 6, wherein each structure pair
The number answered is：Substrate 1, gate insulating layer 3, grid 4, conductive film layer 5, protection film layer 6, organic insulator 7, hides active layer 2
Photosphere 8, insulating layer 9.
Embodiment two
As shown in figure 3, a kind of thin film transistor (TFT) that embodiments herein two proposes, which is characterized in that it includes：From base
Plate 1 is counted, and includes active layer 2, gate insulating layer 3, grid 4 successively；Conductive film layer 5, the conductive film layer 5 overlay on the grid
4 surfaces, and 2 surface of the active layer positioned at 4 lower gate graphic projection both sides of the grid；Protection film layer 6, the guarantor
The whole covering that cuticular layer 6 is constituted the active layer 2, gate insulating layer 3, grid 4 and conductive film layer 5.
Specifically, the film that the offer of above-described embodiment one can be used directly in the thin film transistor (TFT) described in the present embodiment two is brilliant
Body pipe manufacturing method is manufactured.
Thin film transistor (TFT) disclosed in the present application, conductive film layer can directly form S/D figures, that is, form signal line chart
Shape, and then the step of saving this complex process of active layer conductorization, and can effectively reduce LDD region domain, that is, it reduces
The low-doped drain region being arranged near drain electrode in raceway groove, and then dead resistance can be reduced, improve ON state current, and electricity
Stream will not decay because of subsequent high temperature processes；And conductive film layer its can be used with transition zone, make subsequent making
S/D metals can avoid S/D metals and be in direct contact and generate larger with active layer with the good Ohmic contact of the transition zone
Contact resistance, and stability is preferable；Finally, conductive film layer is arranged in the top of grid, can avoid the both sides of gate metal
It is aoxidized in high-temperature technology, and prevents from making the metal of grid expose due to crossing to carve when the etching through hole above gate patterns
Out, such as Cu metals are exposed, and aoxidize.
As shown in figure 4, in specific implementation, the thin film transistor (TFT) further includes：Organic insulator 7, the organic insulation
Layer 7 is arranged in the lower section that the grid 4 projects, between the gate insulating layer 3 and conductive film layer 5.
Specifically, the setting of organic insulator, can improve protection film layer and cross the climbing pattern at quarter, reduce at this
The probability of place broken string and short circuit；In addition, it can be opaque or coloured that filling gate insulating layer, which crosses the organic insulating material at quarter,
Light screening material, the back bias voltage light durability (NBIS) that thin film transistor (TFT) is improved to active layer shading can be played the role of.
The above is only the preferred embodiment of the application, not made any form of restriction to the application, according to
According to the technical spirit of the application to any simple modification, equivalent change and modification made by above example, this Shen is still fallen within
It please be in the range of technical solution.
Claims (10)
1. a kind of method for fabricating thin film transistor, which is characterized in that it includes step：
Active layer, gate insulating layer and grid layer are sequentially formed on substrate；
Photoresist and photoetching are coated on grid layer, and processing is patterned to grid layer and gate insulating layer, obtains grid；
Stripping photoresist sputters to form conductive film using the autoregistration of gate patterns to gate patterns surface and active layer surface
Layer, and carry out graphical treatment；
Eventually form protection film layer, and opening contact hole.
2. method for fabricating thin film transistor according to claim 1, which is characterized in that carrying out stripping photoresist, utilizing
The autoregistration of gate patterns sputters to form conductive film layer to gate patterns surface and active layer surface, and carry out graphical treatment it
Before, the method further includes：
Over etching is carried out to the gate insulating layer, by the gate insulating layer below the grid under the grid
The 1/5-1/3 distances for carving the grid length are crossed in square center.
3. method for fabricating thin film transistor according to claim 2, which is characterized in that
It crosses the distance carved and is equal to the 1/4 of the grid length.
4. method for fabricating thin film transistor according to claim 2, which is characterized in that carrying out stripping photoresist, utilizing
The autoregistration of gate patterns sputters to form conductive film layer to gate patterns surface and active layer surface, and carry out graphical treatment it
Afterwards, the method is also wrapped：
Organic insulator is integrally coated on the surface being made of the gate insulating layer, grid and the conductive film layer；And
It is exposed development using the grid as mask.
5. method for fabricating thin film transistor according to claim 1, which is characterized in that
The grid layer is MoNb layers, the Cu layers and MoNb layers laminated construction that lamination is arranged successively.
6. method for fabricating thin film transistor according to claim 1, which is characterized in that
The grid layer is MoNb layers, the Cu layers of laminated construction being cascading, and described Cu layers relative to MoNb layers far from institute
State active layer.
7. method for fabricating thin film transistor according to claim 1, which is characterized in that
It is described to be formed by the method for coating at protection film layer；
Or, the protection film layer is formed by the method for deposition.
8. method for fabricating thin film transistor according to claim 1, which is characterized in that on substrate formed active layer it
Before, the method further includes：
Light shield layer and insulating layer are sequentially formed on substrate.
9. a kind of thin film transistor (TFT), which is characterized in that it includes：
It is counted from substrate, includes active layer, gate insulating layer, grid successively；
Conductive film layer, the conductive film layer overlays on the gate surface, and is located at grid lower gate graphic projection two
The active layer surface of side；
Protection film layer, the entirety that the protection film layer is constituted the active layer, gate insulating layer, grid and conductive film layer
Covering.
10. thin film transistor (TFT) according to claim 9, which is characterized in that further include：
Organic insulator, the organic insulator are arranged in the lower section that the grid projects, positioned at the gate insulating layer and lead
Between electrolemma layer.
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