CN108538266A - LVDS signals turn the conversion equipment of optional LCOS interface formats signal - Google Patents
LVDS signals turn the conversion equipment of optional LCOS interface formats signal Download PDFInfo
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- CN108538266A CN108538266A CN201810336954.8A CN201810336954A CN108538266A CN 108538266 A CN108538266 A CN 108538266A CN 201810336954 A CN201810336954 A CN 201810336954A CN 108538266 A CN108538266 A CN 108538266A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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Abstract
The present invention relates to the conversion equipment that a kind of LVDS signals turn optional LCOS interface formats signal, the selection signal that the searching module of the device is generated according to toggle switch exports corresponding time sequence configuration information and frame structure configuration information to generation module；Generation module generates the clock signal and the setting new data frame structure to be generated for being suitable for driving the corresponding LCOS chip in rear end according to the time sequence configuration information and frame structure configuration information of reception, then clock signal and three primary colours sub-frame data are fitted into new data frame, along with frame useful signal, the drive signal suitable for driving the corresponding LCOS chip in rear end is ultimately produced.The present invention can carry out selection driving to the LCOS chip of different frame rates and resolution ratio, improve the application of invention；Selection signal is generated by external toggle switch, and coding information is simple, and construction is convenient, can enhance the interactivity of design to selecting the digit of information to be increased or deleted.
Description
Technical field
The invention belongs to signal format switch technology fields, turn optional LCOS interfaces lattice more particularly to a kind of LVDS signals
The chromacoder of formula signal.
Background technology
LVDS (Low-Voltage Differential Signaling, low-voltage differential signal) has high-speed, low
The advantages that noise, low cost, strong anti-electromagnetic interference capability, is widely applied, and is especially applied in terms of transmission of video images
Extensively, LCOS (Liquid Crystal on Silicon, liquid crystal on silicon) is a kind of semiconductor technology and LCD technology phase
In conjunction with core display device, its advantage is that high resolution, low in energy consumption, small, light-weight, existing LVDS signals are converted to
The conversion method of LCOS signals comes with some shortcomings, and conversion method cannot adjust the driver' s timing and frame knot of generation as needed
Structure must re-start information configuration after replacing chip, complicated for operation, can not carry out selection driving to different LCOS chips,
Design method is single, so a kind of effective signal conversion method is necessary.
Invention content
The technical problem to be solved in the present invention is to provide a kind of different LCOS chips that can be accessed to rear end to select
Driving, the good LVDS signals of versatility turn the conversion equipment of optional LCOS interface formats signal.
In order to solve the above-mentioned technical problem, LVDS signals of the invention turn the conversion equipment of optional LCOS interface formats signal
Including signal conversion unit；External LVDS signals are converted to R, G, B sub-frame data through signal conversion unit and carry out gamma to it
The three primary colours sub-frame data corrected；Characterized by further comprising toggle switch, generation module, searching modules；Dial-up
Switch is connected with searching module；The selection signal that toggle switch generates is input to searching module；The searching module is by looking into
Unit and dispensing unit is looked for constitute；Searching unit receives the selection information of toggle switch transmission and searches corresponding address information,
Then the address information found is inputted into dispensing unit；Sequential corresponding with each LCOS chip in outside is stored in dispensing unit to match
Information table and frame structure configuration information table are set, after receiving address information, dispensing unit will be corresponding according to the address information
Time sequence configuration information and frame structure configuration information are exported to generation module；Generation module is by sequential generation unit, frame generation unit
It is constituted with control unit；After generation module receives time sequence configuration information and frame structure configuration information, control unit matches sequential
Confidence ceases and frame structure configuration information is respectively fed to sequential generation unit and frame generation unit；Sequential generation unit configures sequential
Information carries out data bit intercepting process, obtains corresponding to the clocking value of transition status in state machine and is cached in corresponding post respectively
In storage, before starting three primary colours sub-frame data and reading, first by the corresponding timer of transition status in sequential generation unit
Original initial value is compared with the clocking value of corresponding register cache, if the two is different, by each register cache
Clocking value is assigned to corresponding timer；If the two is identical, each timer keeps initial value constant；Sequential generation unit later
The three primary colours sub-frame data of signal conversion unit output is read out, frame length, the line number etc. of three primary colours sub-frame data are scanned
Frame information generates the sequential letter for being suitable for driving the corresponding LCOS chip in rear end according to frame information by the way of finite state machine
Number；The timing information that sequential generation unit generates and three primary colours sub-frame data are sent into frame generation unit by control unit together,
Frame generation unit sets the new data frame structure to be generated according to the frame structure configuration information of reception, then by time series data and
Three primary colours sub-frame data is fitted into new data frame, adds frame useful signal, is ultimately produced corresponding suitable for driving rear end
The drive signal of LCOS chip.
The signal conversion unit includes receiving module, clock module, conversion module, memory module；External LVDS letters
Number it is input to receiving module；LVDS signals are sent to clock module by receiving module, clock module extract in LVDS signals when
Clock signal simultaneously carries out frequency multiplication generation sampled signal, and the multiple of frequency multiplication is equal to the serialization factor；Clock module believes the sampling of generation
Number it is recycled to receiving module, while system clock is provided for conversion module, memory module, generation module and searching module；It receives
Module samples LVDS signals by sampled signal, and then carrying out serioparallel exchange to the serial data that sampling obtains obtains simultaneously
Row data, send parallel data into conversion module later；Conversion module is under the control of system clock by the parallel data of reception
It is converted to R, G, B sub-frame data and gamma correction is carried out to it, the three primary colours sub-frame data corrected is simultaneously deposited into storage
In module.
The searching module uses Content Addressable Memory (CAM).
The memory module is made of storage unit and read-write control unit, and wherein storage unit is made of dual port RAM；
Storage unit is configured by read-write control unit, to three primary colours of conversion module output under the action of read-write control unit
Frame data carry out Pingpang Memory operation；When read-write control unit, which receives the request that conversion module is sent, stores signal, judge to deposit
Whether the memory space of storage unit is full, if non-full, receive the write address that read-write control unit provides, and by three bases of reception
Dice frame data are stored in the corresponding write address of storage unit；When read-write control unit detects the read request that generation module is sent
When signal, state of memory cells is detected, if storage unit reads the three primary colours subframe for normally controlling storage unit output storage
Data control storage unit and stop receiving the three primary colours sub-frame data that conversion module is sent if storage unit reads exception, etc.
Unit to be stored restores normal.
The beneficial effects of the invention are as follows：
1. the searching module of the present invention includes time sequence configuration information and the frame structure configuration suitable for a variety of LCOS chips
Information can carry out selection driving to the LCOS chip of different frame rates and resolution ratio, improve the application of invention.
2. the searching module of the present invention can modify according to the needs that LCOS chip drives, to be adapted to new LCOS chip
Drive control, increase the validity of design.
3. the present invention can adjust the frame data structure generated according to the time sequence configuration information and frame structure configuration information of configuration,
So that signal can effectively drive corresponding LCOS chip.
4. the searching module of the present invention is the Content Addressable Memory (CAM) that FPGA is constituted, search speed is fast, can be right
The selection information of input carries out quickly selection and searches.
5. the selection signal of the present invention is generated by external toggle switch, coding information is simple, and construction is convenient, can believe selection
The digit of breath is increased or is deleted, and the interactivity of design is enhanced.
6. the resource that FPGA can be used in the present invention is designed realization so that the processing capacity of data-signal further increases
By force, data transition rate is substantially improved, and overall performance is improved.
Description of the drawings
Invention is further described in detail with reference to the accompanying drawings and detailed description.
Fig. 1 is that the LVDS signals of the present invention turn the conversion device structure block diagram of optional LCOS interface formats signal.
Fig. 2 is time sequence configuration information schematic diagram.
Specific implementation mode
As shown in Figure 1, the converting system that the LVDS signals of the present invention turn optional LCOS interface formats signal includes that dial-up is opened
Pass, receiving module, clock module, conversion module, memory module, searching module, generation module；Wherein receiving module, clock mould
Block, conversion module, memory module, searching module, generation module can be realized by FPGA；Toggle switch is connected with searching module
It connects；The selection signal of toggle switch is input to searching module.
Clock module：Whether detection receiving module sends request signal, if there is request signal, is received from receiving module
LVDS signals simultaneously extract clock signal therein, and carrying out frequency multiplication to clock signal generates sampled signal；The multiple of frequency multiplication is by LVDS
The serialization factor of signal determines, if the serialization factor is 7, the multiple of frequency multiplication is 7.Then clock module is by the sampling of generation
Signal is recycled to receiving module, while generating clock by the calling of clock IP kernel in FPGA, be conversion module, memory module,
Generation module and searching module provide system clock, ensure that whole flow process synchronizes orderly progress.
Receiving module：It is made of recovery unit and serioparallel exchange unit；Recovery unit sends request signal to clock first
Module, then by LVDS signals be sent into clock module, later again by the sampled signal of clock module loopback to LVDS signals into
Row sampling, the serial data that sampling is obtained are sent into serioparallel exchange unit；Serioparallel exchange unit is unstringed by the LVDS in FPGA
Device is constituted, and the serial data of reception is converted to parallel data by LVDS deserializers；Serioparallel exchange unit is sent out to conversion module later
A convert requests signal is sent, the parallel data of serioparallel exchange unit output is sent into conversion module.
Conversion module：It is made of data cell and correction unit；Data cell receives turn that serioparallel exchange unit is sent
After changing request signal, parallel data is then received, R, G, B number of sub frames are converted parallel data under the control of system clock
According to, then transformed R, G, B sub-frame data is sent into correction unit and carries out the three primary colours number of sub frames after gamma correction is corrected
According to so that image data, which is shown, to be more clear；It corrects unit and sends a request storage signal to memory module again, then by three
Primary color sub-frames data are stored in memory module.
Memory module：It is made of storage unit and read-write control unit, wherein storage unit is made of dual port RAM, is constituted
Pingpang Memory operates so that three primary colours sub-frame data can carry out continuously storing read operation.Storage unit is by Read-write Catrol
Unit is configured, and is stored to the three primary colours sub-frame data of conversion module output under the action of read-write control unit.
When read-write control unit, which receives the request that conversion module sends, stores signal, judge storage unit memory space whether be
It is full, if non-full, receiving the write address that read-write control unit provides, and the three primary colours sub-frame data of reception is stored in storage unit
In corresponding write address.The reading request signal that read-write control unit detection generation module is sent detects if there is reading request signal
State of memory cells, if storage unit reads the three primary colours sub-frame data for normally controlling storage unit output storage, if storage
Unit reads exception, then controls storage unit and stop receiving the three primary colours sub-frame data that correction unit is sent, wait for storage unit
Restore normal.
Searching module is made of searching unit and dispensing unit, and searching unit is to be realized using SRL16 shift registers
The selection information that toggle switch transmits is compared in 4bit Content Addressable Memories, searching unit.One selection information pair
Answer a LCOS chip, it includes two parts data to select information, high two be correspondence time sequence configuration information selection data, low two
Position is the selection data of corresponding frame configuration information, and the two synthesizes in one four selection information inputs to searching unit, each
A selection information is all corresponding with an address in searching unit, and corresponding address information is sent into configuration list after comparing successfully
In member.Each address in dispensing unit both points to two look-up tables, two look-up tables be respectively time sequence configuration information table and
Frame structure configuration information table has separately included time sequence configuration information and frame structure configuration information, when searching unit output address is believed
After breath to dispensing unit, dispensing unit just exports time sequence configuration information corresponding with the address and frame structure configuration information.
In dispensing unit, what time sequence configuration information table included is that 9 transition status in finite state machine are corresponding
Timer Configuration Values, the wherein finite state machine in generation module totally 11 states, including beginning state, terminates state and 9
A transition status relates only to 9 transition status in state machine, wherein the clocking value of 9 transition status includes here：
The reading data counts value rd_data_cnt that READ_DATA states include
The scan data latch clock clocking value lthclk_cnt that LTHCLK_GEN states include
The row that ROW_WAIT0 states include waits for clocking value row_wait_cnt
The row digital independent count value rd_row_cnt that ROW_WAIT1 states include
The pixel capacitance drop-down clocking value pulldow_cnt that PULLDOW_S states include
The pixel capacitance pull-up clocking value pullup_cnt that PULLUP_S states include
The pixel capacitance charges clocking value read_s_cnt that READ_S states include
The frame that FRAME_WAIT0 states include waits for clocking value frame_wait_cnt
The frame idle waiting clocking value frame_idle_cnt that FRAME_IDLE states include
9 transition status all corresponding configurations, one timer is counted, and matches confidence according to sequential in generation module
Breath is pre-configured the timer value of each state.Frame structure configuration information table includes then digit information, the timing information of frame
Number, image data way information and the digit information for including per road.Corresponding two of each address is searched in dispensing unit
The configuration information of table is that the characteristic progress of the LCOS chip accessed according to rear end is pre-set, so that generation module can generate
The drive signal of effect.
Generation module is made of sequential generation unit, frame generation unit and control unit, and generation module receives dispensing unit
The configuration information sent, configuration information include the time sequence configuration information and frame for the external LCOS chip driving for being suitable for accessing at this time
Time sequence configuration information is sent into sequential generation unit by structure configuration information, control unit, and frame structure configuration information is sent into frame life
At unit.After sequential generation unit receives time sequence configuration information, data bit intercepting process is carried out to time sequence configuration information, is obtained pair
9 registers for being used for data buffer storage, the meter that data intercept position is obtained should be then defined in the clocking value of 9 transition status
Duration is assigned to corresponding register and is cached respectively, before starting three primary colours sub-frame data and reading, carries out timing first
The initial value of each timer in sequential generation unit is compared with the clocking value of corresponding register cache for the comparison of value,
If the two is different, the clocking value of each register cache is assigned to corresponding timer；If the two is identical, original timing is kept
Device initial value is constant.Sequential generation unit carries out the generation of sequential by the way of finite state machine, state machine totally 11 states,
Respectively IDLE, READ_DATA, LTHCLK_GEN, ROW_WAIT0, ROW_WAIT1, PULLDOW_S, PULLUP_S, READ_
S, FRAME_WAIT0, FRAME_WAIT1, FRAME_IDLE state, wherein IDLE are beginning state, and FRAME_IDLE is to terminate
State, remaining 9 are transition status.Sequential generation unit sends a reading request signal to memory module, memory module in advance
Three primary colours sub-frame data, the three primary colours sub-frame data that sequential generation unit exports memory module are exported after receiving request signal
It is read out, scans the frame informations such as frame length, the line number of three primary colours sub-frame data received, state machine is carried out according to frame information
State conversion, state machine is often transformed into a new state, that is, starts the corresponding timer of corresponding state, when the counting of timer
When value is identical as Configuration Values, state machine is switched to NextState from current state.Sequential generation unit passes through detecting state machine
Current state and different timers clocking value, assignment operation is carried out to different clock signal, is suitable for driving to generate
The clock signal of dynamic LCOS chip, the clock signal that sequential generation unit generates totally 10 signals, respectively field sync signal VS,
Line synchronising signal HS, pixel capacitance pulldown signal PULLDOW, pixel capacitance pull up signal PULLUP, pixel capacitance charges signal
READ, public electrode energizing signal VCOM, top scan data clock CPNT, bottom scan data clock CPNB, top scan data lock
Clock LTHCLKT, bottom scan data latch clock LTHCLKB are deposited, is later sent into clock signal under the action of control unit
Frame generation unit.
The timing information of generation and three primary colours sub-frame data are sent into frame generation unit by control unit together, and frame generates single
Member sets the structure of data frame to be generated according to the frame structure configuration information of reception, including the digit that setting includes per frame, when
The number of sequence information, the way of image data and the digit for including per road, then all by timing information and three primary colours sub-frame data
It is fitted into new data frame, adds frame useful signal, ultimately produce the drive signal suitable for driving rear end LCOS chip.
Drive example：It is 256X256 pixels to drive a resolution ratio, and frame per second 8KHz, the parallel 10bit in four tunnels are inputted
LCOS chip, by advance design, respectively obtains the timer value in 9 states, so in the case of known chip attribute
Configure the rd_data_cnt in timing information allocation list to 6 ' df afterwards, lthclk_cnt is configured to 4 ' h9, row_wait_cnt
3 ' h4 are configured to, rd_row_cnt is configured to 8 ' hff, and pulldow_cnt is configured to 6 ' d39, and pullup_cnt is configured to 6 '
D39, read_s_cnt are configured to 9 ' d399, and frame_wait_cnt is configured to 12 ' d4078, and frame_idle_cnt is configured to
15 ' d24999 are learnt the frame structure information of drive signal by LCOS chip attribute, will be per frame packet in frame structure information allocation list
The digit contained is set as 64, and the number of timing information is configured to 10, and image data way is configured to four tunnels, includes per road
Digit is configured to 10bit, is eventually adding frame useful signal to highest order, constitutes complete frame data.
Present invention improves over can only simplify hardware configuration for the deficiency that single LCOS chip is driven, make in the past
It obtains engineering efficiency to greatly improve, improves the applicability of invention.LVDS signals turn the realization side of optional LCOS interface formats signal
Method, by being improved sequence configuration method, using Content Addressable Memory so that search speed is quicker, and can root
Configuration information is designed and is changed according to the attribute information of LCOS chip, to generate the drive signal suitable for access chip,
Selection information is generated by toggle switch, and the different chips that can be accessed to rear end carry out selection driving, and improving in the past can only needle
To the deficiency that single LCOS chip is driven, hardware configuration is simplified so that engineering efficiency greatly improves, and improves invention
Applicability.
Claims (4)
1. a kind of LVDS signals turn the conversion equipment of optional LCOS interface formats signal, including signal conversion unit；External LVDS
Signal is converted to R, G, B sub-frame data through signal conversion unit and carries out the three primary colours number of sub frames that gamma correction is corrected to it
According to；Characterized by further comprising toggle switch, generation module, searching modules；Toggle switch is connected with searching module；Dial-up is opened
It closes the selection signal generated and is input to searching module；The searching module is made of searching unit and dispensing unit；It searches single
Member receives the selection information of toggle switch transmission and searches corresponding address information, then inputs the address information found and configures
Unit；Time sequence configuration information table corresponding with each LCOS chip in outside and frame structure configuration information table are stored in dispensing unit,
After receiving address information, dispensing unit is according to the address information by corresponding time sequence configuration information and frame structure configuration information
It exports to generation module；Generation module is made of sequential generation unit, frame generation unit and control unit；Generation module receives
After time sequence configuration information and frame structure configuration information, time sequence configuration information and frame structure configuration information are respectively fed to by control unit
Sequential generation unit and frame generation unit；Sequential generation unit carries out data bit intercepting process to time sequence configuration information, obtains pair
It the clocking value of transition status and should respectively be cached in corresponding register in state machine, read starting three primary colours sub-frame data
Before taking, first by the original initial value of the corresponding timer of transition status in sequential generation unit and corresponding register cache
Clocking value be compared, if the two is different, the clocking value of each register cache is assigned to corresponding timer；If the two
Identical, then each timer keeps initial value constant；The three primary colours subframe that sequential generation unit exports signal conversion unit later
Data are read out, and scan the frame informations such as frame length, the line number of three primary colours sub-frame data, and finite state machine is used according to frame information
Mode generate the clock signal for being suitable for driving the corresponding LCOS chip in rear end；Control unit by sequential generation unit generate when
Sequence information and three primary colours sub-frame data are sent into together in frame generation unit, and frame generation unit is according to the frame structure configuration information of reception
It sets the new data frame structure to be generated, then time series data and three primary colours sub-frame data is fitted into new data frame, then
In addition frame useful signal, ultimately produces the drive signal suitable for driving the corresponding LCOS chip in rear end.
2. LVDS signals according to claim 1 turn the conversion equipment of optional LCOS interface formats signal, it is characterised in that
The signal conversion unit includes receiving module, clock module, conversion module, memory module；External LVDS signals are input to
Receiving module；LVDS signals are sent to clock module by receiving module, and clock module extracts the clock signal in LVDS signals simultaneously
It carries out frequency multiplication and generates sampled signal, the multiple of frequency multiplication is equal to the serialization factor；The sampled signal of generation is recycled to by clock module
Receiving module, while providing system clock for conversion module, memory module, generation module and searching module；Receiving module passes through
Sampled signal samples LVDS signals, and then carrying out serioparallel exchange to the serial data that sampling obtains obtains parallel data,
Parallel data is sent into conversion module later；Conversion module under the control of system clock by the parallel data of reception be converted to R,
G, B sub-frame datas and gamma correction is carried out to it, the three primary colours sub-frame data corrected is simultaneously deposited into memory module.
3. LVDS signals according to claim 1 turn the conversion equipment of optional LCOS interface formats signal, it is characterised in that
The searching module uses Content Addressable Memory.
4. LVDS signals according to claim 2 turn the conversion equipment of optional LCOS interface formats signal, it is characterised in that
The memory module is made of storage unit and read-write control unit, and wherein storage unit is made of dual port RAM；Storage unit
Configured by read-write control unit, under the action of read-write control unit to conversion module output three primary colours sub-frame data into
Row Pingpang Memory operates；When read-write control unit, which receives the request that conversion module is sent, stores signal, storage unit is judged
Whether memory space is full, if non-full, receive the write address that read-write control unit provides, and by the three primary colours number of sub frames of reception
According in the deposit corresponding write address of storage unit；When read-write control unit detects the reading request signal that generation module is sent,
State of memory cells is detected, if storage unit reads the three primary colours sub-frame data for normally controlling storage unit output storage, if
Storage unit reads exception, then controls storage unit and stop receiving the three primary colours sub-frame data that conversion module is sent, wait to be stored
Unit restores normal.
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| CN201810336954.8A CN108538266B (en) | 2018-04-16 | 2018-04-16 | Conversion device for converting LVDS signal into LCOS interface format signal |
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