CN108520765B - System and method for measuring bit line parasitic parameters in phase change memory array - Google Patents
System and method for measuring bit line parasitic parameters in phase change memory array Download PDFInfo
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- CN108520765B CN108520765B CN201810304264.4A CN201810304264A CN108520765B CN 108520765 B CN108520765 B CN 108520765B CN 201810304264 A CN201810304264 A CN 201810304264A CN 108520765 B CN108520765 B CN 108520765B
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
Abstract
The invention provides a system and a method for measuring bit line parasitic parameters in a phase change memory array, which comprises the following steps: a plurality of word lines arranged in parallel at intervals; a plurality of bit lines arranged in parallel at intervals; a phase change memory array; a drive circuit connected to each bit line; at least one test structure including a driving circuit, a variable resistor, a variable capacitor, and a second phase change memory cell; one end of a series circuit formed by connecting the variable resistor and the variable capacitor in series is connected with the driving circuit, and the other end of the series circuit is connected with the second phase change memory unit; the structure of the second phase change memory cell is the same as the structure of the first phase change memory cell. The invention can simply and conveniently obtain the bit line parasitic parameters in the phase change memory array, provides a basis for each phase change memory unit in the phase change memory array to be fully operated to make up for energy loss, and provides a basis for obtaining more consistent resistance distribution and improving the working reliability of the phase change memory chip.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a system and method for measuring parasitic parameters of bit lines in a phase change memory array.
Background
Phase Change Memory (PCM) is a new type of resistive nonvolatile semiconductor Memory, which uses chalcogenide material as a storage medium and uses the different resistance states of nano-sized Phase Change material in crystalline state (material in low resistance state) and amorphous state (material in high resistance state) to realize data storage. The phase change memory has the obvious advantages of non-volatility, high speed, high density, low power consumption, high reliability, good compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, and is considered as a novel non-volatile memory which is most likely to replace a flash memory to become a mainstream product in the future memory market by the international association of semiconductor industry.
The working mechanism of the phase change memory is that the phase change material is reversibly transformed from a crystalline state to an amorphous state under the action of different electric pulses, and the resistance difference of the phase change material in different states is utilized to store data. The basic operation of the phase change memory is three: when a narrow and strong electric pulse is applied to the phase change region, a large amount of joule heat is generated in the phase change region, so that the temperature of the phase change region is raised to the melting temperature, and after rapid annealing, the crystalline long-range ordered structure is destroyed, the phase change region becomes an amorphous state, the resistance value is very high and is marked as a logic value of 0, and the process is called as a writing (RESET) process; when a long and moderate electric pulse is applied to the amorphous phase change memory, the generated joule heat raises the temperature of a phase change area to be higher than the crystallization temperature and lower than the melting temperature, so that the material is finally crystallized, the resistance value is reduced and is marked as logic '1', and the process is an erasing (SET) process; in addition, the phase change memory also has read operation, and weak electric pulse is applied to make the material below the crystallization temperature, so that the aim of measuring the resistance value of the phase change memory is achieved under the condition of not influencing the logic state of the phase change memory.
Through the development of more than 20 years, the phase change memory can be produced in large scale and is advanced on the industrialization road. Since a phase change memory test chip with the capacity of 4Mb based on a 0.18 mu m standard Complementary Metal Oxide Semiconductor (CMOS) process is introduced in 2002, the capacity of the phase change memory chip is continuously increased, the process technology is continuously improved, a 64Mb phase change memory chip is successfully developed by Samsung in 2004, an 8Gb phase change memory chip is manufactured in 2016, and the process node is rapidly reduced to 20nm from 0.18 mu m. In 2012, the 1Gb memory chip based on the phase change memory technology for the mobile phone was produced in mass production in beautiful light, and the industrialization of the phase change memory chip was realized. In 7 months in 2015, the phase change memory chip is revolutionarily broken in speed, service life and capacity by the 3D Xpoint technology based on the phase change memory jointly issued by intel corporation and meiguang corporation, and a large number of memory chips based on the 3D Xpoint are predicted to be produced in 2017, so that the mainstream FLASH memory market is greatly impacted. Even so, the phase change memory still cannot replace the FLASH memory at present, and the operational reliability of the phase change memory chip is an important factor restricting the development of the phase change memory chip. With the continuous improvement of process technology and the continuous increase of capacity of phase change memory, the problem of energy loss on bit lines in memory arrays is increasingly prominent. Therefore, on the basis of the reality of the current manufacturing process, it is worth to examine how to measure the parasitic parameters of the bit lines on the phase change memory array.
Based on the above reasons, the resistance values of the phase change memory chip after the write and erase operations are read, and it is found that as the capacity of the phase change memory array increases, the number of the phase change memory cells connected on the same bit line increases, and after the driving circuit generates the excitation signal, the parasitic parameters such as the parasitic capacitance and the distributed resistance on the bit line consume the energy of the excitation signal, so that the phase change memory cells farther from the driving circuit on the bit line cannot be fully operated. With the increase of the chip capacity, the resistance value difference of the operated phase change memory unit is more obvious, and the working reliability of a large-capacity phase change memory chip is seriously influenced, so that the measurement of the bit line parasitic parameters in the phase change memory array has a practical significance, and no method for effectively measuring the parasitic parameters on the bit line in the phase change memory array exists at present.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a system and a method for measuring parasitic parameters of bit lines in a phase change memory array, which are used to solve the problem that the prior art cannot effectively measure parasitic parameters of bit lines in a phase change memory array.
To achieve the above and other related objects, the present invention provides a system for measuring parasitic parameters of bit lines in a phase change memory array, the system at least comprising:
a plurality of word lines arranged in parallel at intervals;
the bit lines are arranged in parallel at intervals, and the extending direction of the bit lines and the extending direction of the word lines have a preset angle;
the phase change memory array comprises a plurality of phase change memories which are arranged in rows and columns at intervals; along the extending direction of the bit lines, the phase change memories and the word lines are alternately arranged in sequence at intervals; along the extending direction of the word line, the phase change memories and the bit lines are arranged in sequence at intervals; each phase change memory comprises an MOS tube and a first phase change memory unit, in each phase change memory, the grid electrode of the MOS tube is connected with the word line adjacent to the MOS tube, the drain electrode of the MOS tube is connected with the bit line adjacent to the MOS tube through the first phase change memory unit, and the source electrode of the MOS tube is grounded;
a driving circuit connected to each of the bit lines;
at least one test structure including the driving circuit, a variable resistor, a variable capacitor, and a second phase change memory cell; wherein a series circuit in which the variable resistor and the variable capacitor are connected in series has one end connected to the drive circuit and the other end connected to the second phase change memory cell; the structure of the second phase change memory cell is the same as the structure of the first phase change memory cell.
As a preferable aspect of the system for measuring the parasitic parameter of the bit line in the phase change memory array according to the present invention, the MOS transistor includes an NMOS transistor.
As a preferred scheme of the system for measuring the parasitic parameters of the bit lines in the phase change memory array, the number of the word lines is n, the number of the bit lines is m, and a plurality of the phase change memories are arranged at intervals of n rows and m columns; the grid electrode of the MOS tube in the ith row of the phase change memory is connected with the ith word line, and the drain electrode of the MOS tube in the jth column of the phase change memory is connected with the jth bit line; wherein i is an integer greater than 0 and less than or equal to n, j is an integer greater than 0 and less than or equal to m, and m and n are both integers greater than 0.
As a preferable aspect of the system for measuring a parasitic parameter of a bit line in the phase change memory array of the present invention, the driving circuit includes:
a first driving circuit connected to each of the bit lines for providing a first driving signal to the first phase change memory cell;
a second drive circuit connected to a series circuit of the variable resistor and the variable capacitor in series for supplying a second pumping signal identical to the first pumping signal to the second phase change memory cell; the second driver circuit and the variable resistor, the variable capacitor and the second phase change memory cell together constitute the test structure.
As a preferable aspect of the system for measuring parasitic parameters of bit lines in the phase change memory array of the present invention, the system for measuring parasitic parameters of bit lines in the phase change memory array further includes:
a bit line selector connected to the first driving circuit and each of the bit lines;
an address buffer;
a word line decoder connected to the address buffer and each of the word lines;
and the bit line decoder is connected with the address buffer and the bit line selector.
As a preferable aspect of the system for measuring parasitic parameters of bit lines in the phase change memory array of the present invention, the system for measuring parasitic parameters of bit lines in the phase change memory array further includes:
a bit line selector connected to the driving circuit and each of the bit lines;
an address buffer;
a word line decoder connected to the address buffer and each of the word lines;
and the bit line decoder is connected with the address buffer and the bit line selector.
As a preferable aspect of the system for measuring the parasitic parameter of the bit line in the phase change memory array of the present invention, the system for measuring the parasitic parameter of the bit line in the phase change memory array includes a plurality of the test structures.
As a preferable embodiment of the system for measuring the bit line parasitic parameter in the phase change memory array of the present invention, the test structure further includes an oscilloscope, and the oscilloscope is connected in parallel with the second phase change memory unit.
The invention also provides a method for measuring the bit line parasitic parameters in the phase change memory array, which comprises the following steps:
1) providing a system for measuring parasitic parameters of bit lines in a phase change memory array as described in any of the above aspects;
2) sending out the same excitation signal to the first phase change memory unit and the second phase change memory unit;
3) measuring the resistance value of any one first phase change memory unit in the phase change memory array;
4) adjusting the resistance value of the variable resistor and the capacitance value of the variable capacitor until the difference between the resistance value of the second phase change memory cell and the resistance value of the first phase change memory cell is within an error tolerance range;
5) determining the parasitic resistance on the bit line in the phase change memory array according to the resistance value of the variable resistor obtained in the step 4), and determining the parasitic capacitance on the bit line in the phase change memory array according to the capacitance value of the variable capacitor obtained in the step 4).
As a preferable aspect of the method for measuring the parasitic parameter of the bit line in the phase change memory array of the present invention, in step 3), the resistance value of the first phase change memory cell farthest from the driving circuit in the phase change memory array is measured.
As a preferable solution of the method for measuring the bit line parasitic parameter in the phase change memory array of the present invention, in step 3), the resistance value of the first phase change memory cell after the write operation and the resistance value of the first phase change memory cell after the erase operation are measured;
in step 4), adjusting the resistance value of the variable resistor and the capacitance value of the variable capacitor until the difference between the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range, and recording the resistance value of the variable resistor and the capacitance value of the variable capacitor at the moment; continuously adjusting the resistance value of the variable resistor and the capacitance value of the variable capacitor until the difference between the resistance value of the second phase change memory unit after the erasing operation and the resistance value of the first phase change memory unit after the erasing operation is within an error allowable range, and recording the resistance value of the variable resistor and the capacitance value of the variable capacitor at the moment;
in step 5), if the difference value between the two resistance values of the variable resistor obtained in step 4) is within a preset range, taking the average value of the two resistance values of the variable resistor as the parasitic resistance on the bit line in the phase change memory array; if the difference value of the two resistance values of the variable resistor obtained in the step 4) is beyond a preset range, taking the resistance value of the variable resistor obtained when the difference value of the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range as a parasitic resistance on a bit line in the phase change memory array; if the difference value of the two capacitance values of the variable capacitor obtained in the step 4) is within a preset range, taking the average value of the two capacitance values of the variable capacitor as the parasitic capacitance on the bit line in the phase change memory array; if the difference between the two capacitance values of the variable capacitor obtained in the step 4) is beyond a preset range, the capacitance value of the variable capacitor obtained when the difference between the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range is used as the parasitic capacitance on the bit line in the phase change memory array.
As a preferable scheme of the method for measuring the parasitic parameter of the bit line in the phase change memory array, the method further comprises the following steps after the step 5): obtaining a real excitation signal waveform applied to the first phase change memory unit according to the parasitic resistance and the parasitic capacitance obtained in the step 5).
As a preferred embodiment of the method for measuring the bit line parasitic parameter in the phase change memory array of the present invention, a true current value flowing through the first phase change memory cell is obtained according to the parasitic resistance, a delay of a rising edge and a falling edge of the driving signal applied to the first phase change memory cell is obtained according to the parasitic capacitance, and a true driving signal waveform applied to the first phase change memory cell is obtained according to the true current value and the delay of the rising edge and the falling edge of the driving signal.
As a preferred embodiment of the method for measuring the bit line parasitic parameter in the phase change memory array of the present invention, a real stimulus signal waveform applied to the second phase change memory cell is acquired by an oscilloscope connected in parallel with the second phase change memory cell, and the acquired real stimulus signal waveform is the real stimulus signal waveform applied to the first phase change memory cell.
As described above, the system and method for measuring parasitic parameters of bit lines in a phase change memory array according to the present invention have the following advantages: the invention provides a measuring system and a measuring method capable of measuring parasitic parameters on bit lines in a phase change memory, wherein the parasitic parameters of the bit lines in the phase change memory array can be simply and conveniently obtained by combining a testing structure with the phase change memory array, a basis is provided for each phase change memory unit in the phase change memory array to be fully operated to make up for energy loss, and a basis is provided for obtaining relatively consistent resistance distribution and improving the working reliability of a phase change memory chip; the measuring system of the invention has simple structure and higher reliability.
Drawings
Fig. 1 and 2 are block diagrams illustrating a system for measuring parasitic parameters of bit lines in a phase change memory array according to an embodiment of the invention.
FIG. 3 is a block diagram of a test structure in a system for measuring parasitic parameters of bit lines in a phase change memory array according to an embodiment of the invention.
FIG. 4 is a simplified circuit schematic diagram of the first phase change memory cell A of FIGS. 1 and 2.
Fig. 5 shows the distribution of resistance values of the first phase change memory cell a and the first phase change memory cell B in fig. 1 and 2 after a write operation and an erase operation.
FIG. 6 is a flowchart illustrating a method for measuring parasitic parameters of bit lines in a phase change memory array according to a second embodiment of the present invention.
Description of the element reference numerals
1 phase change memory
11 MOS tube
12 first phase change memory cell
2 drive circuit
3 test structure
31 variable resistor
32 variable capacitor
33 second phase change memory cell
34 oscilloscope
4 bit line selector
5 address buffer
6 word line decoder
7 bit line decoder
Parasitic resistance of MOS transistor with R1 connected with first phase change memory unit A
Parasitic capacitance of MOS transistor connected with C1 and first phase change memory unit A
Parasitic resistance in R2 first phase change memory cell A
Parasitic capacitance in C2 first phase change memory cell A
Parasitic resistance of bit line R3 connected to first phase change memory cell A
Parasitic capacitance of bit line C3 connected to first phase change memory cell A
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 3, the present invention provides a system for measuring parasitic parameters of bit lines in a phase change memory array, the system for measuring parasitic parameters of bit lines in a phase change memory array at least comprising: a plurality of word lines WL arranged in parallel at intervals; the bit lines BL are arranged in parallel at intervals, and the extending direction of the bit lines BL and the extending direction of the word lines WL have preset angles; the phase change memory array comprises a plurality of phase change memories 1 which are arranged in rows and columns at intervals; along the extending direction of the bit line BL, the phase change memories 1 and the word lines WL in each row are alternately arranged at intervals in sequence; along the extending direction of the word line WL, the phase change memories 1 and the bit lines BL in each row are alternately arranged in sequence at intervals; each phase change memory 1 comprises an MOS tube 11 and a first phase change memory unit 12, in each phase change memory 1, a gate of the MOS tube 11 is connected with the word line WL adjacent to the MOS tube 11, a drain of the MOS tube 11 is connected with the bit line BL adjacent to the MOS tube 11 through the first phase change memory unit 12, and a source of the MOS tube 11 is grounded; a drive circuit 2, the drive circuit 2 being connected to each of the bit lines BL; at least one test structure 3, the test structure 3 comprising the driving circuit 2, a variable resistor 31, a variable capacitor 32 and a second phase change memory cell 33; wherein a series circuit in which the variable resistor 31 and the variable capacitor 32 are connected in series has one end connected to the drive circuit 2 and the other end connected to the second phase change memory unit 33; the structure of the second phase change memory cell 33 is the same as the structure of the first phase change memory cell 12.
As an example, continuing to refer to fig. 1 and fig. 2, the number of the word lines WL is n, the number of the bit lines BL is m, that is, the word lines WL include n word lines of word lines WL1 and WL2 … WLn arranged in parallel at intervals, the bit lines BL include m bit lines of bit lines BL1 and BL2 … BLm arranged in parallel at intervals, and the extending directions of the n word lines WL (i.e., the length direction of the word lines WL) and the m bit lines BL (i.e., the length direction of the bit lines BL) may be, but are not limited to, perpendicular; the phase change memories 1 are arranged in n rows and m columns at intervals to form the phase change memory array; the grid electrode of the MOS tube 11 in the phase change memory 1 in the ith row is connected with the ith word line WLi, and the drain electrode of the MOS tube 11 in the phase change memory 1 in the jth column is connected with the jth bit line BLj; wherein i is an integer greater than 0 and less than or equal to n, j is an integer greater than 0 and less than or equal to m, and m and n are both integers greater than 0.
It should be noted that the driving circuit 2 in the test structure 3 shown in fig. 3 may be the driving circuit 2 connected to each bit line BL in the phase change memory array shown in fig. 1; of course, the driving circuit 2 in the test structure 3 may also be different from the driving circuit 2 connected to each bit line BL in the phase change memory array as shown in fig. 2, in which case, the driving circuit 2 includes a series circuit connected to each bit line WL for providing a first driving signal to the first phase change memory cell 12 (i.e., the driving circuit 2 connected to each bit line WL in fig. 2) and the variable resistor 31 and the variable capacitor 32 are connected in series, a second driving circuit (i.e., the driving circuit 2 shown in fig. 3) for providing a second driving signal identical to the first driving signal to the second phase change memory cell 33, that is, the driving circuit 2 in fig. 2 and the driving circuit 2 in fig. 3 may be two different driving circuits, however, although the driving circuit 2 in fig. 2 and the driving circuit 2 in fig. 3 are two different driving circuits, they need to send out the same driving signal, for example, the driving signal may be, but not limited to, a current square wave pulse signal of 1mA/100 ns. It should be further noted that the driving circuit 2 in the test structure 1 in fig. 1 is the driving circuit 2 connected to each bit line BL, and for convenience of illustration and description, the test structure 3 in fig. 1 is only shown in a manner connected to the driving circuit 2.
As an example, the MOS transistor 11 is used as a gate transistor, and the MOS transistor 11 may be a PMOS transistor or an NMOS transistor, and preferably, in this embodiment, the MOS transistor 11 is preferably an NMOS transistor.
As an example, with continuing reference to fig. 1 and 2, the system for measuring parasitic parameters of bit lines in the phase change memory array further includes: a bit line selector 4, the bit line selector 4 being connected to the driver circuit 2 connected to each of the bit lines BL and each of the bit lines BL, that is, when the driver circuit 2 connected to each of the bit lines BL is the same as the driver circuit 2 in the test structure 3, the bit line selector 4 being connected to the driver circuit 2 and each of the bit lines BL, and when the driver circuit 2 connected to each of the bit lines BL is different from the driver circuit 2 in the test structure 3 (the driver circuit 2 connected to each of the bit lines BL is the first driver circuit, and the driver circuit 2 in the test structure 3 is the second driver circuit as described above), the bit line selector 4 being connected to the first driver circuit and each of the bit lines BL; an address buffer 5; a word line decoder 6, the word line decoder 6 being connected to the address buffer 5 and each of the word lines WL; a bit line decoder 7, the bit line decoder 7 being connected with the address buffer 5 and the bit line selector 4. The specific structure and function of the bit line selector 4, the address buffer 5, the word line decoder 6 and the bit line decoder 7 are known to those skilled in the art, and will not be described in detail herein.
As an example, each of the bit lines BL, each of the word lines WL, the phase change memory array, the bit line selector 4, the address buffer 5, the word line decoder 6, the bit line decoder 7, and the driving circuit 2 connected to the bit line selector 4 may be disposed on a same chip, for example, the chip may be a 64Mb phase change memory chip manufactured based on 45nm process node in the middle core world, and 8129 first phase change memory cells 12 on the same bit line WL share the same driving circuit 2. The test structure 3 may be disposed on the chip, and may be disposed outside the phase change memory array, or may be disposed outside the chip. The number of the test structures 3 may be one as shown in fig. 1 and 2, or may be two or more, and the number of the test structures 3 is not limited.
As an example, continuing to refer to fig. 3, the test structure 3 may further include an oscilloscope 34, where the oscilloscope 34 is connected in parallel with the second phase change memory unit 33. Specifically, the oscilloscope 34 is connected to the upper electrode and the phase of the second phase change memory unit 33, so as to be connected in parallel to the second phase change memory unit 33.
For example, referring to fig. 4 in combination with fig. 1 and 2, the first phase change memory cell 12 farthest from the driving circuit 2 is referred to as a first phase change memory cell a as shown in fig. 1 and 2, the first phase change memory cell 12 closest to the driving circuit 2 is referred to as a first phase change memory cell B as shown in fig. 1 and 2, and a simplified circuit diagram of the first phase change memory cell a is illustrated in fig. 4, as can be seen from fig. 4, the circuit diagram includes a parasitic resistance R1 of a MOS transistor connected to the first phase change memory cell a, a parasitic capacitance C1 of a MOS transistor connected to the first phase change memory cell a, a parasitic resistance R2 of the first phase change memory cell a, a parasitic capacitance C2 of the first phase change memory cell a, a parasitic resistance R3 of a bit line BL3 connected to the first phase change memory cell a, and a parasitic capacitance C3 of a bit line BL3 connected to the first phase change memory cell a; the parasitic resistance R1 of the MOS transistor connected with the first phase change memory cell A, the parasitic capacitance C1 of the MOS transistor connected with the first phase change memory cell A, the parasitic resistance R2 of the first phase change memory cell A and the parasitic capacitance C2 of the first phase change memory cell A are independent of the position of the first phase change memory cell A in the phase change memory array, so that the main reason that the resistance value difference is obvious after operation due to the position difference is the parasitic parameter loss of the bit line (the parasitic resistance of the bit line and the parasitic capacitance of the bit line).
Referring to fig. 5, fig. 5 shows the distribution of resistance values measured after the first phase change memory cell a and the first phase change memory cell B are subjected to a plurality of write operations and erase operations, as can be seen from fig. 5, due to the loss on the bit line, the first phase change memory cell a farthest from the drive circuit 2 is hardly subjected to a write operation (RESET) to a high resistance value, that is, the resistance value of the first phase change memory cell a after the write operation in fig. 5 is generally lower than the resistance value of the first phase change memory cell B after the write operation, this fully illustrates that the first phase change memory cell a, which is furthest from the driver circuit 2, cannot be fully operated, being a failed cell, and the longer the length of the bit line, the greater the loss on the bit line, the more first phase change memory cells 12 that cannot be fully operated.
The working principle of the measuring system for the bit line parasitic parameters in the phase change memory array is as follows: first, the same stimulus signal is sent to the first phase change memory cell 12 and the second phase change memory cell 33 by using the driving circuit 2; secondly, measuring the resistance value of any one of the first phase change memory cells 12 in the phase change memory array, preferably the resistance value of the first phase change memory cell 12 farthest from the driving circuit 2 in the phase change memory arrays on both sides; then, the resistance value of the variable resistor 31 and the capacitance value of the variable capacitor 32 are adjusted until the difference between the resistance value of the second phase change memory cell 33 and the resistance value of the first phase change memory cell 12 is within an error allowable range; finally, the resulting resistance value of the variable resistor 31 determines the parasitic resistance on the bit line in the phase change memory array, and the resulting capacitance value of the variable capacitor 32 determines the parasitic capacitance on the bit line in the phase change memory array. It should be noted that, since the first phase change memory cell 12 and the second phase change memory cell 33 include two operations of a write operation (RESET) and an erase operation (SET), the resistance value of the first phase change memory cell 12 and the second phase change memory cell 33 after the write operation and the resistance value after the erase operation need to be tested in the measurement process; if the difference between the two resistance values of the variable resistor is within a predetermined range, the average value of the two resistance values of the variable resistor is used as the parasitic resistance on the bit line in the phase change memory array; if the obtained difference value of the two resistance values of the variable resistor exceeds a preset range, taking the resistance value of the variable resistor obtained when the difference value of the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range as a parasitic resistance on a bit line in the phase change memory array; if the obtained difference value of the two capacitance values of the variable capacitor is within a preset range, taking the average value of the two capacitance values of the variable capacitor as the parasitic capacitance on the bit line in the phase change memory array; and if the obtained difference value of the two capacitance values of the variable capacitor exceeds a preset range, taking the capacitance value of the variable capacitor obtained when the difference value of the resistance value of the second phase change memory unit after the write operation and the resistance value of the first phase change memory unit after the write operation is within an error allowable range as the parasitic capacitance on the bit line in the phase change memory array.
According to the invention, by combining the test structure 3 with the phase change memory array, parasitic parameters of the bit line WL in the phase change memory array can be simply and conveniently obtained, a basis is provided for each first phase change memory unit 12 in the phase change memory array to be fully operated to make up for energy loss, and a basis is provided for obtaining relatively consistent resistance distribution and improving the working reliability of a phase change memory chip; meanwhile, the system for measuring the bit line parasitic parameters in the phase change memory array has the advantages of simple structure and higher reliability.
Example two
Referring to fig. 6 in conjunction with fig. 1 to 5, the present invention further provides a method for measuring parasitic parameters of bit lines in a phase change memory array, comprising the following steps:
1) providing a system for measuring parasitic parameters of bit lines in a phase change memory array as described in embodiment one;
2) issuing the same stimulus signal to the first phase change memory cell 12 and the second phase change memory cell 33;
3) measuring the resistance of any one of the first phase change memory cells 12 in the phase change memory array;
4) adjusting the resistance value of the variable resistor 31 and the capacitance value of the variable capacitor 32 until the difference between the resistance value of the second phase change memory cell 33 and the resistance value of the first phase change memory cell 12 is within an error tolerance;
5) determining the parasitic resistance on the bit line in the phase change memory array according to the resistance value of the variable resistor 31 obtained in step 4), and determining the parasitic capacitance on the bit line in the phase change memory array according to the capacitance value of the variable capacitor 32 obtained in step 4).
For example, please refer to the first embodiment for a specific structure of the system for measuring the parasitic parameter of the bit line in the phase change memory array, which will not be described herein again.
As an example, in step 2), the same stimulus signal is sent to the first phase change memory cell 12 and the second phase change memory cell 33 using the driving circuit 2; the excitation signal may be, but is not limited to, a current square wave pulse signal of 1mA/100 ns.
As an example, since the first phase change memory cell 12 and the second phase change memory cell 33 include two operations of a write operation (RESET) and an erase operation (SET), the resistance values of the first phase change memory cell 12 and the second phase change memory cell 33 tested in step 3) include the resistance values of the first phase change memory cell 12 and the second phase change memory cell 33 after the write operation and the resistance values after the erase operation.
As an example, in order to ensure the accuracy of the measurement, the resistance value of the first phase change memory cell 12 farthest from the driving circuit 2 in the phase change memory array is measured in step 3).
As an example, in step 4), the resistance value of the variable resistor 31 and the capacitance value of the variable capacitor 32 are adjusted until the difference between the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 is within the error tolerance range, and the resistance value of the variable resistor 31 and the capacitance value of the variable capacitor 32 at this time are recorded; the resistance value of the variable resistor 31 and the capacitance value of the variable capacitor 32 are continuously adjusted until the difference between the resistance value of the second phase change memory cell 33 after the erase operation and the resistance value of the first phase change memory cell 12 after the erase operation is within the error tolerance, and the resistance value of the variable resistor 31 and the capacitance value of the variable capacitor 32 are recorded at this time.
As an example, since the erase operation is too much related to the states of the first phase change memory cell 12 and the phase change memory cell 33, the process defects, and the dominant factors of the phase change, in step 5), if the difference between the two resistance values of the variable resistor 31 obtained in step 4) (i.e., the resistance value of the variable resistor 31 recorded when the difference between the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 is within the allowable error range and the resistance value of the variable resistor 31 recorded when the difference between the resistance value after the erase operation of the second phase change memory cell 33 and the resistance value after the erase operation of the first phase change memory cell 12 is within the allowable error range) is within the predetermined range, the average value of the two resistance values of the variable resistor 31 is taken as the parasitic resistance on the bit line in the phase change memory array; if the difference between the two resistance values of the variable resistor 31 obtained in step 4) is out of the preset range, taking the resistance value of the variable resistor 31 obtained when the difference between the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 is within the error tolerance range as the parasitic resistance on the bit line in the phase change memory array; if the difference between the two capacitance values of the variable capacitor obtained in step 4) (i.e., the capacitance value of the variable capacitor 32 recorded when the difference between the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 is within the error tolerance range, and the capacitance value of the variable capacitor 32 recorded when the difference between the resistance value after the erase operation of the second phase change memory cell 33 and the resistance value after the erase operation of the first phase change memory cell 12 is within the error tolerance range) is within the predetermined range, taking the average value of the two capacitance values of the variable capacitor 32 as the parasitic capacitance on the bit line in the phase change memory array; if the difference between the two capacitance values of the variable capacitor 32 obtained in step 4) is out of the preset range, the capacitance value of the variable capacitor 32 obtained when the difference between the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 is within the error tolerance range is used as the parasitic capacitance on the bit line in the phase change memory array.
It should be noted that the above-mentioned "the difference between the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 is within the error tolerance range" means that the resistance value after the write operation of the second phase change memory cell 33 and the resistance value after the write operation of the first phase change memory cell 12 are substantially the same or the difference between the two is within a preset numerical range, and the above-mentioned "the difference between the resistance value after the erase operation of the second phase change memory cell 33 and the resistance value after the erase operation of the first phase change memory cell 12 is within the error tolerance range" means that the resistance value after the erase operation of the second phase change memory cell 33 and the resistance value after the erase operation of the first phase change memory cell 12 are substantially the same or the difference between the two is within a preset numerical range.
As an example, the following steps are also included after step 5): obtaining the real excitation signal waveform applied to the first phase change memory unit 12 according to the parasitic resistance and the parasitic capacitance obtained in the step 5).
Specifically, in an example, a real current value flowing through the first phase change memory cell 12 is obtained according to the parasitic resistance, delay of a rising edge and a falling edge of the excitation signal applied to the first phase change memory cell 12 is obtained according to the parasitic capacitance, and a real excitation signal waveform applied to the first phase change memory cell 12 is obtained according to the real current value and the delay of the rising edge and the falling edge of the excitation signal. In another example, the oscilloscope 34 connected in parallel with the second phase change memory unit 33 is used to obtain the real stimulus signal waveform applied to the second phase change memory unit 33, and the obtained real stimulus signal waveform is the real stimulus signal waveform applied to the first phase change memory unit 12.
In summary, the present invention provides a system and a method for measuring parasitic parameters of bit lines in a phase change memory array, where the system for measuring parasitic parameters of bit lines in a phase change memory array at least includes: a plurality of word lines arranged in parallel at intervals; the bit lines are arranged in parallel at intervals, and the extending direction of the bit lines and the extending direction of the word lines have a preset angle; the phase change memory array comprises a plurality of phase change memories which are arranged in rows and columns at intervals; along the extending direction of the bit lines, the phase change memories and the word lines are alternately arranged in sequence at intervals; along the extending direction of the word line, the phase change memories and the bit lines are arranged in sequence at intervals; each phase change memory comprises an MOS tube and a first phase change memory unit, in each phase change memory, the grid electrode of the MOS tube is connected with the word line adjacent to the MOS tube, the drain electrode of the MOS tube is connected with the bit line adjacent to the MOS tube through the first phase change memory unit, and the source electrode of the MOS tube is grounded; a driving circuit connected to each of the bit lines; at least one test structure including the driving circuit, a variable resistor, a variable capacitor, and a second phase change memory cell; wherein a series circuit in which the variable resistor and the variable capacitor are connected in series has one end connected to the drive circuit and the other end connected to the second phase change memory cell; the structure of the second phase change memory cell is the same as the structure of the first phase change memory cell. The invention provides a measuring system and a measuring method capable of measuring parasitic parameters on bit lines in a phase change memory, wherein the parasitic parameters of the bit lines in the phase change memory array can be simply and conveniently obtained by combining a testing structure with the phase change memory array, a basis is provided for each phase change memory unit in the phase change memory array to be fully operated to make up for energy loss, and a basis is provided for obtaining relatively consistent resistance distribution and improving the working reliability of a phase change memory chip; the measuring system of the invention has simple structure and higher reliability.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A system for measuring parasitic parameters of bit lines in a phase change memory array, comprising:
a plurality of word lines arranged in parallel at intervals;
the bit lines are arranged in parallel at intervals, and the extending direction of the bit lines and the extending direction of the word lines have a preset angle;
the phase change memory array comprises a plurality of phase change memories which are arranged in rows and columns at intervals; along the extending direction of the bit lines, the phase change memories and the word lines are alternately arranged in sequence at intervals; along the extending direction of the word line, the phase change memories and the bit lines are arranged in sequence at intervals; each phase change memory comprises an MOS tube and a first phase change memory unit, in each phase change memory, the grid electrode of the MOS tube is connected with the word line adjacent to the MOS tube, the drain electrode of the MOS tube is connected with the bit line adjacent to the MOS tube through the first phase change memory unit, and the source electrode of the MOS tube is grounded;
a driving circuit connected to each of the bit lines;
at least one test structure including the driving circuit, a variable resistor, a variable capacitor, and a second phase change memory cell; wherein a series circuit in which the variable resistor and the variable capacitor are connected in series has one end connected to the drive circuit and the other end connected to the second phase change memory cell; the structure of the second phase change memory cell is the same as the structure of the first phase change memory cell.
2. The system of claim 1, wherein the system comprises: the MOS tube comprises an NMOS tube.
3. The system of claim 1, wherein the system comprises: the number of the word lines is n, the number of the bit lines is m, and the phase change memories are arranged in n rows and m columns at intervals; the grid electrode of the MOS tube in the ith row of the phase change memory is connected with the ith word line, and the drain electrode of the MOS tube in the jth column of the phase change memory is connected with the jth bit line; wherein i is an integer greater than 0 and less than or equal to n, j is an integer greater than 0 and less than or equal to m, and m and n are both integers greater than 0.
4. The system of claim 1, wherein the system comprises: the drive circuit includes:
a first driving circuit connected to each of the bit lines for providing a first driving signal to the first phase change memory cell;
a second drive circuit connected to a series circuit of the variable resistor and the variable capacitor in series for supplying a second pumping signal identical to the first pumping signal to the second phase change memory cell; the second driver circuit and the variable resistor, the variable capacitor and the second phase change memory cell together constitute the test structure.
5. The system of claim 4, wherein the system comprises: the system for measuring the parasitic parameters of the bit lines in the phase change memory array further comprises:
a bit line selector connected to the first driving circuit and each of the bit lines;
an address buffer;
a word line decoder connected to the address buffer and each of the word lines;
and the bit line decoder is connected with the address buffer and the bit line selector.
6. The system of claim 1, wherein the system comprises: the system for measuring the parasitic parameters of the bit lines in the phase change memory array further comprises:
a bit line selector connected to the driving circuit and each of the bit lines;
an address buffer;
a word line decoder connected to the address buffer and each of the word lines;
and the bit line decoder is connected with the address buffer and the bit line selector.
7. The system of claim 1, wherein the system comprises: the measuring system of the bit line parasitic parameters in the phase change memory array comprises a plurality of test structures.
8. The system according to any one of claims 1 to 7, wherein: the test structure further comprises an oscilloscope, and the oscilloscope is connected with the second phase change memory unit in parallel.
9. A method for measuring bit line parasitic parameters in a phase change memory array, comprising the steps of:
1) providing a measurement system of a bit line parasitic parameter in a phase change memory array of any one of claims 1 to 8;
2) sending out the same excitation signal to the first phase change memory unit and the second phase change memory unit;
3) measuring the resistance value of any one first phase change memory unit in the phase change memory array;
4) adjusting the resistance value of the variable resistor and the capacitance value of the variable capacitor until the difference between the resistance value of the second phase change memory cell and the resistance value of the first phase change memory cell is within an error tolerance range;
5) determining the parasitic resistance on the bit line in the phase change memory array according to the resistance value of the variable resistor obtained in the step 4), and determining the parasitic capacitance on the bit line in the phase change memory array according to the capacitance value of the variable capacitor obtained in the step 4).
10. The method of claim 9, wherein the method further comprises: in step 3), measuring a resistance value of a first phase change memory unit farthest from the driving circuit in the phase change memory array.
11. The method of claim 9, wherein the method further comprises:
measuring the resistance value of the first phase change memory unit after writing operation and the resistance value of the first phase change memory unit after erasing operation in the step 3);
in step 4), adjusting the resistance value of the variable resistor and the capacitance value of the variable capacitor until the difference between the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range, and recording the resistance value of the variable resistor and the capacitance value of the variable capacitor at the moment; continuously adjusting the resistance value of the variable resistor and the capacitance value of the variable capacitor until the difference between the resistance value of the second phase change memory unit after the erasing operation and the resistance value of the first phase change memory unit after the erasing operation is within an error allowable range, and recording the resistance value of the variable resistor and the capacitance value of the variable capacitor at the moment;
in step 5), if the difference value between the two resistance values of the variable resistor obtained in step 4) is within a preset range, taking the average value of the two resistance values of the variable resistor as the parasitic resistance on the bit line in the phase change memory array; if the difference value of the two resistance values of the variable resistor obtained in the step 4) exceeds a preset range, taking the resistance value of the variable resistor obtained when the difference value of the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range as a parasitic resistance on a bit line in the phase change memory array; if the difference value of the two capacitance values of the variable capacitor obtained in the step 4) is within a preset range, taking the average value of the two capacitance values of the variable capacitor as the parasitic capacitance on the bit line in the phase change memory array; if the difference value of the two capacitance values of the variable capacitor obtained in the step 4) exceeds a preset range, taking the capacitance value of the variable capacitor obtained when the difference value of the resistance value after the write operation of the second phase change memory unit and the resistance value after the write operation of the first phase change memory unit is within an error allowable range as a parasitic capacitance on a bit line in the phase change memory array.
12. The method of measuring the parasitic parameter of the bit line in the phase change memory array according to any one of claims 9 to 11, wherein: the following steps are also included after the step 5): obtaining a real excitation signal waveform applied to the first phase change memory unit according to the parasitic resistance and the parasitic capacitance obtained in the step 5).
13. The method of claim 12, wherein the method further comprises: obtaining a real current value flowing through the first phase change memory unit according to the parasitic resistance, obtaining the delay of the rising edge and the falling edge of the excitation signal applied to the first phase change memory unit according to the parasitic capacitance, and obtaining a real excitation signal waveform applied to the first phase change memory unit according to the real current value and the delay of the rising edge and the falling edge of the excitation signal.
14. The method of claim 12, wherein the method further comprises: and acquiring a real excitation signal waveform applied to the second phase change memory unit through an oscilloscope which is connected with the second phase change memory unit in parallel, wherein the acquired real excitation signal waveform is the real excitation signal waveform applied to the first phase change memory unit.
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| CN101901631A (en) * | 2009-05-28 | 2010-12-01 | 海力士半导体有限公司 | Phase change memory apparatus and test circuit therefor |
| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
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| CN101901631A (en) * | 2009-05-28 | 2010-12-01 | 海力士半导体有限公司 | Phase change memory apparatus and test circuit therefor |
| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
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