CN108519707A - A kind of array substrate and display device - Google Patents
A kind of array substrate and display device Download PDFInfo
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- CN108519707A CN108519707A CN201810273263.8A CN201810273263A CN108519707A CN 108519707 A CN108519707 A CN 108519707A CN 201810273263 A CN201810273263 A CN 201810273263A CN 108519707 A CN108519707 A CN 108519707A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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Abstract
The invention discloses a kind of array substrate and display devices, by will at least partly electrostatic discharge protection circuit be arranged close to second signal line, and second signal line is arranged at least adjacent to the second corner, electrostatic charge on the first signal wire of the second corner is released by electrostatic discharge protection circuit, avoid the electrostatic residual on the first signal wire, and then electrostatic breakdown caused by accumulation of static electricity is effectively prevented, to be conducive to improve the display quality of picture.
Description
Technical field
The present invention relates to display technology field, espespecially a kind of array substrate and display device.
Background technology
With the development of display screen technology, shields comprehensively and come into being, compared with common display screen, display area has
The accounting of bigger, and the frame with ultra-narrow, can greatly improve the visual experience of viewer.In addition, aobvious in order to keep away
Show that the performance of panel is influenced the display quality of picture by the interference of electrostatic, needs to be arranged in the neighboring area of display panel
Electrostatic discharge protection circuit；So, how electrostatic discharge protection circuit in neighboring area is set, to discharge the electrostatic charge in screen comprehensively, is
Those skilled in the art's technical problem urgently to be resolved hurrily.
Invention content
An embodiment of the present invention provides a kind of array substrate and display devices, to the electrostatic being released effectively in screen comprehensively
Lotus improves the quality for showing picture.
An embodiment of the present invention provides a kind of array substrates, including：
Display area, and the neighboring area around the display area；
The neighboring area includes：Binding region；The orientation of the binding region and the display area is first
Direction；
The display area includes：Separate binding region side setting and the first corner that shape is on-right angle, with
And close to the second corner of binding region side setting；
The array substrate further includes：A plurality of first signal wire arranged in a second direction；The second direction with it is described
First direction is mutually perpendicular to；
The neighboring area further includes：Multiple electrostatic discharge protection circuits, and at least adjacent to the of second corner setting
Binary signal line；At least partly described electrostatic discharge protection circuit is arranged close to the second signal line；And each electrostatic discharge protection circuit
One end electrical connection corresponding with each first signal wire, close to the electrostatic discharge protection circuit of second signal line setting
The other end is electrically connected with the second signal line.
It is thus possible to which the electrostatic charge on the first signal wire of the second corner is enable to pass through electrostatic discharge protection circuit quilt
It discharges, avoids the electrostatic residual on the first signal wire, and then effectively prevent electrostatic breakdown caused by accumulation of static electricity, to
Be conducive to improve the display quality of picture.
On the other hand, the embodiment of the present invention additionally provides a kind of display device, including：Liquid crystal display panel；
The liquid crystal display panel includes：Such as above-mentioned array substrate provided in an embodiment of the present invention, with the array base
The opposite substrate that plate is opposite and sets, and the liquid crystal between the array substrate and the opposite substrate.
The present invention has the beneficial effect that：
A kind of array substrate and display device provided in an embodiment of the present invention, by will at least partly lean on electrostatic discharge protection circuit
Nearly second signal line setting, and second signal line is arranged at least adjacent to the second corner so that the first signal close to the second corner
Electrostatic charge on line can be released by electrostatic discharge protection circuit, avoid the electrostatic residual on the first signal wire, Jin Eryou
Effect avoids electrostatic breakdown caused by accumulation of static electricity, to be conducive to improve the display quality of picture.
Description of the drawings
Fig. 1 is the structural schematic diagram of display panel in the prior art；
Fig. 2 is the structural schematic diagram of the array substrate provided in the embodiment of the present invention；
Fig. 3 to Fig. 5 is respectively the partial structural diagram of the array substrate provided in the embodiment of the present invention；
Fig. 6 to Fig. 8 is respectively the sectional view in array substrate surface direction；
Fig. 9 is the partial structural diagram of the array substrate provided in the embodiment of the present invention；
Figure 10 is the structural schematic diagram of the electrostatic discharge protection circuit provided in the embodiment of the present invention；
Figure 11 is the structural schematic diagram of the display device provided in the embodiment of the present invention；
Figure 12 is the structural schematic diagram of the liquid crystal display panel provided in the embodiment of the present invention.
Specific implementation mode
Below in conjunction with attached drawing, to the specific embodiment party of a kind of array substrate provided in an embodiment of the present invention and display device
Formula is described in detail.It should be noted that described embodiments are only a part of the embodiments of the present invention, rather than it is complete
The embodiment in portion.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Inventor has found under study for action, for traditional display panel, such as rectangular display panel, on the periphery of display panel
It is usually provided with binding region in region, and driving chip can be set in binding region, for being the driving in neighboring area
Circuit provides corresponding drive signal, to realize display function；Also, in order to eliminate the electrostatic charge in display panel, usually exist
The neighboring area of display panel is provided with electrostatic discharge protection circuit, and each electrostatic discharge protection circuit and each data line one in display area
One is correspondingly connected with, and for discharging the electrostatic charge in data line, avoids the transmission for influencing data-signal in data line.
In addition, when display panel is low temperature polycrystalline silicon (Low Temperature Ploy-Silicon, LTPS) product,
That is when the active layer of the transistor in display panel is all made of low-temperature polysilicon silicon materials, due to this kind of transistor
Area occupied is smaller, so the area occupied for the electrostatic discharge protection circuit being made of this kind of transistor is also smaller, so as to will be quiet
Electric protection circuit is arranged in the neighboring area of binding region side；And when display panel is non-crystalline silicon product, that is to say, that
When the active layer of transistor in display panel is all made of amorphous silicon material, due to this kind of transistor area occupied compared with
Greatly so that the electrostatic discharge protection circuit being made of this kind of transistor, and the area occupied of other driving circuits are also larger, to
Electrostatic discharge protection circuit can be arranged in neighboring area of the display area far from binding region side, be conducive to display panel
Layout.
However, for display panel shown in FIG. 1, wherein including：Display area and neighboring area 1, and display area is wrapped
It includes：First display area A1, the second display area A2 and third display area A3；First display area A1 and the second display area
It is intermediate region B1 between A2, intermediate region B1 belongs to neighboring area 1；First display area A1, intermediate region B1 and second
Display area A2 is respectively positioned on the same side of third display area A3.
For conventional display panels, in order to obtain aesthetic effect, it will usually set four angles of rectangular display area
It is set to arc-shaped corner.However, compared with the conventional display panels of rectangular display area, shield display panel shown in Fig. 1 comprehensively
First display area A1 and the second display area A2 actually is equivalent to the part of its periphery region of conventional display panels.When making figure
Shield shown in 1 comprehensively after, due to having increased display area newly, in the neighboring area 1 of arc-shaped corner (as illustrated with the dotted box) nearby
It is provided with driving circuit (not shown), which can be used for driving the display that screen increases newly compared with convention display comprehensively
The pixel circuit in region.Therefore, the neighboring area area of comprehensive screen display panel shown in FIG. 1 is reduced, specifically, aobvious with first
Show that region A1 and the area of the second adjacent peripheral region of display area A2 are greatly reduced, so that in the neighboring area 1
Electrostatic discharge protection circuit 2 is arranged in not enough spaces, and the data line 3 close to arc-shaped edge is caused to fail that electrostatic protection is arranged
Circuit 2, the problem of can not dischargeing by the electrostatic charge accumulated in the data line 3 at this, be susceptible to screen flicker.
Based on this, an embodiment of the present invention provides a kind of array substrate and display devices, for solving close to arc-shaped side
The problem of electrostatic remains in data line at angle, to improve the display quality of picture.
Specifically, a kind of array substrate provided in an embodiment of the present invention, as shown in Fig. 2, may include：
Display area, and the neighboring area B around display area；Specifically, as shown in Fig. 2, display area is by
What one display area A1, the second display area A2 and third display area A3 were constituted；
Neighboring area B may include：Binding region B0；The orientation of binding region B0 and display area is first party
To the first direction is Y-direction in fig. 2；
Display area may include：The separate sides binding region B0 setting and the first corner a1 that shape is on-right angle, with
And the second corner a2 close to the setting of the sides binding region B0；
Array substrate can also include：The a plurality of first signal wire S1 arranged in a second direction；The second direction is in fig. 2
For X-direction, so second direction is mutually perpendicular to first direction, that is to say, that X-direction is mutually perpendicular to Y-direction；
Neighboring area B can also include：Multiple electrostatic discharge protection circuits 10 (rectangular region of filled black in such as figure), with
And the second signal line S2 at least adjacent to the second corner a2 settings；At least partly electrostatic discharge protection circuit 10 is close to second signal line S2
Setting；And one end electrical connection corresponding with each first signal wire S1 of each electrostatic discharge protection circuit 10, close to the S2 settings of second signal line
The other end of electrostatic discharge protection circuit 10 be electrically connected with second signal line S2.
In above-mentioned array substrate provided in an embodiment of the present invention, while realizing screen comprehensively, by will at least partly
Electrostatic discharge protection circuit is arranged close to second signal line, and second signal line is arranged at least adjacent to the second corner so that close to second
Electrostatic charge on first signal wire of corner can be released by electrostatic discharge protection circuit, be avoided quiet on the first signal wire
Electricity residual, and then electrostatic breakdown caused by accumulation of static electricity is effectively prevented, to be conducive to improve the display quality of picture.
In the specific implementation, the shape of display area can there are many, and in embodiments of the present invention mainly with Fig. 2 institutes
It is shown as what example illustrated, but it is not limited to this；Specifically, as shown in Fig. 2, display area may include：First display area
A1, the second display area A2 and third display area A3；Wherein, between the first display area A1 and the second display area A2
For intermediate region Bm, and the first display area A1, intermediate region Bm and the second display area A2 are respectively positioned on third display area A3
The same side；It should be pointed out that intermediate region Bm may belong to neighboring area B, intermediate region Bm is generally used for being arranged at this time
The devices such as camera, receiver or inductor, can be with setting unit circuit；So set, effectively increasing accounting for for display area
With area, screen accounting is improved, is advantageously implemented the design shielded comprehensively；Certainly, it is simple to can be also used for display by intermediate region Bm
Image, at this time intermediate region Bm then belong to display area, in this way, can then further increase screen accounting, be more conducive to reality
The design now shielded comprehensively；And neighboring area B is belonged to intermediate region Bm to illustrate in embodiments of the present invention.
Therefore, according to the structure of the display area of above-mentioned introduction, the first corner a1 can be that the first display area A1 is separate
The on-right angle corner of the intermediate region sides Bm；Second corner a2 can be third display area A3 close to the sides binding region B0
Corner.
Optionally, in embodiments of the present invention, as shown in Fig. 2, display area can also include：Close to binding region B0 mono-
Side is arranged and belongs to the third corner a3 of third display area A3, and far from binding region B0 and intermediate region Bm settings and belongs to
In the 4th corner a4 of the second display area A2；Wherein, the second corner a2 and third corner a3 can be right angle corner, and the
Four corner a4 are on-right angle corner, do not provide diagram；It is, of course, also possible to as shown in Fig. 2, the second corner a2, third corner a3 and
4th corner a4 can be on-right angle corner, to increase the aesthetic feeling of display panel.
Optionally, in embodiments of the present invention, second signal line S2 can be only located at close to the peripheral region of the second corner a2
In the B of domain, diagram is not provided, in this way, can pass through the electrostatic discharge protection circuit 10 close to second signal line S2 setting so that close to the
Electrostatic charge on first signal wire S1 of two corner a2 settings is released, and effectively avoids the first signal wire S1 at this because of electrostatic
Lotus assembles and leads to electrostatic breakdown.
Further, in embodiments of the present invention, second signal line S2 can also be disposed in proximity to the week of third corner a3
In border region B, as shown in Fig. 2, in this way, when the first corner a1 and the 4th corner a4 are on-right angle corner, by second
Corner a2 and third corner a3 is respectively provided with second signal line S2, and electrostatic discharge protection circuit is arranged around second signal line S2
10, the electrostatic charge that can be released effectively on the first signal wire S1 that the second corner a2 and third corner a3 is arranged, to have
Conducive to the reliability of the entire display panel of raising.
Specifically, in order to clearly demonstrate the structure of the array substrate provided in the present invention, the first side will be located at herein
Neighboring area B between angle a1 and the second corner a2 is referred to as the first neighboring area B1, will be located at third corner a3 and the 4th side
Neighboring area B between the a4 of angle is referred to as the second neighboring area B2, by the week between the first corner a1 and the 4th corner a4
Border region B is referred to as third neighboring area B3, and third neighboring area B3 and binding region B0 is located at opposite the two of display area
Side, as shown in Figure 2.
Also, inventor has found under study for action, and the above-mentioned array substrate that embodiment provides in the present invention is liquid crystal display
When array substrate in panel, in the first neighboring area B1 and it is both provided with common signal line 20 in the second neighboring area B2,
For transmitting common signal (i.e. COM signals) for the public electrode (not shown) in display area, to realize liquid crystal display
The display function of panel.And in embodiments of the present invention, the current potential of second signal line S2 can be the current potential or the of common signal
Binary signal line S2 can be ground signal line, so as to utilize common signal line 20 or ground signal line in array substrate,
The electrostatic charge being released effectively on the first signal wire S1, avoids static focus phenomenon；Therefore, it is public affairs in the current potential of second signal line S2
Altogether when the current potential of signal, the second signal line S2 being arranged close to the second corner a2 and third corner a3, can respectively with positioned at the
Common signal line 20 in one neighboring area B1 and in the second neighboring area B2 is electrically connected, as shown in Fig. 2, for disperseing electrostatic
Lotus；Wherein, if common signal line 20 and second signal line S2 is located at same layer, the two can be directly electrically connected, such as Fig. 3 to Fig. 5
It is shown, wherein Fig. 3 to Fig. 5 is the partial schematic diagram of array substrate；If common signal line 20 is located at different from second signal line S2
When layer, then the two can be electrically connected by via k, as shown in figure 9, for details, reference can be made to following the description.
Certainly, it when second signal line S2 is ground signal line, then needs (not provide figure with the insulation of common signal line 20
Show), in case ground signalling has an impact common signal.Below just using the current potential of second signal line S2 as the current potential of common signal
For illustrate.
Based on this, in embodiments of the present invention, second signal line S2 can along the second corner a2 in display area and
The outer edge of third corner a3 is arranged, as shown in Fig. 2, to be conducive to the design of the other structures in neighboring area；Also, second
The shape of signal wire S2 can be arc-shaped or step-like, as shown in Figures 2 to 5, to be further reduced the occupancy of neighboring area
Area；Wherein, when the second corner a2 and third corner a3 is right angle corner, diagram is not provided, optionally, second signal line S2
Shape could be provided as it is step-like, be conducive to along the outer edge of the second corner a2 and third corner a3 be arranged, reduce week
The area occupied of border region；It is, of course, also possible to be arc-shaped (not providing diagram), do not limit herein；In the second corner a2 and
When third corner a3 is on-right angle corner, as shown in Figures 2 to 5, wherein the second corner a2 is illustrated only in Fig. 3 to Fig. 5, the
The shape of binary signal line S2 can be arc-shaped (as shown in Figures 2 to 4) or step-like (as shown in Figure 5), so that second signal
Line S2 can outer edge that is parallel or being approximately parallel to the second corner a2 and third corner a3, to reduce the occupancy face of neighboring area
Product, is conducive to the design of narrow frame.
It should be noted that one end of second signal line S2 is connected on the driving chip in binding region B0, such as Fig. 2
It is shown, but driving chip is not provided in figure, in order to provide common signal for second signal line S2 by driving chip or connect
Earth signal, to realize the dispersion of electrostatic charge.
It should also be noted that, in Fig. 3 to Fig. 5, the width of second signal line S2 is than the width of the first signal wire S1
Greatly, this is because：Second signal line S2 is structure as a whole with common signal line 20, and common signal line 20 is generally positioned at first
Neighboring area B1 and the second neighboring area B2, for providing common signal for the public electrode in display area, to realize display；
And in order to ensure the homogeneity of display, it needs to ensure that the pressure difference of the common signal of different location in display area is less than default threshold
Value, to avoid pressure difference it is larger caused by show difference, therefore, the width of common signal line 20 is made larger, reduces electricity
Resistance, and then pressure drop is reduced, ensure the homogeneity of signal, to ensure display effect.
In addition, in the configuration shown in fig. 9, second signal line S2 with common signal line 20 be electrically connected by via k, and
And the width of second signal line S2 is bigger than the width of common signal line 20, this is because：Second signal line S2 is along the second side
The outer edge of angle a2 and third corner a3 are arranged, no matter and be arranged to arc-shaped or step-like, pass through increase second signal line
The width of S2 can effectively reduce manufacture difficulty；Also, the driving chip electricity of one end of second signal line S2 and binding region B0
Connection, the other end are electrically connected with common signal line 20, by increasing the width of second signal line S2, can reduce second signal line
The resistance of S2, and then pressure drop is effectively reduced, the homogeneity of signal is improved, is conducive to improve display effect.
Optionally, in embodiments of the present invention, the electrostatic discharge protection circuit 10 close to the S2 settings of second signal line is specifically set
Seated position can have following several embodiments：The first embodiment, close to the electrostatic protection electricity of second signal line S2 settings
Road 10 is respectively arranged at second signal line S2 close to the side of the second corner a2 and second signal line S2 close to third corner a3's
Side, as shown in Figures 2 and 3 so that it is compact-sized, advantageously reduce the area occupied of neighboring area.
Second of embodiment is respectively arranged at the second letter close to the electrostatic discharge protection circuit 10 of second signal line S2 settings
Number side and second signal line S2 sides far from third corner a3 of the line S2 far from the second corner a2, as shown in Figure 4 and Figure 5,
To avoid regional area wiring it is more crowded caused by interfere with each other or short circuit.
The third embodiment is respectively arranged at the second letter close to the electrostatic discharge protection circuit 10 of second signal line S2 settings
Number side and second signal line S2 of the line S2 far from the second corner a2 and third corner a3 are close to the second corner a2 and third side
The side of angle a3 does not provide diagram, so set, both can to avoid regional area connect up it is more crowded caused by interfere with each other or
Short circuit can reduce neighboring area with the layout of optimization array substrate while the reliability for effectively improving display panel
Area occupied.
Specifically, when second signal line S2 is arranged, no matter which kind of above-mentioned embodiment is used, in the embodiment of the present invention
In, when display area can also include the first transistor T1, second signal line S2 can be with the source/drain in the first transistor T1
Pole same material and same layer setting, as shown in Figure 6, wherein Fig. 6 is the sectional view in array substrate surface direction；At this point,
If the first signal wire S1 is data line, then needing to ensure second signal line S2 and data line mutually insulated, to avoid the second letter
Number interfering with each other between line S2 and data line；Alternatively, second signal line S2 can be with the same material of grid in the first transistor T1
Matter and same layer setting, do not provide diagram, since second signal line S2 is located at grid layer, so no matter the first signal wire S1 is data
Line or touching signals line are not in situation short-circuit between the first signal wire S1 and second signal line S2；Again alternatively,
Display area can also include：When outermost public electrode 30 far from array substrate side is set in the first signal wire S1,
Second signal line S2 can be arranged with 30 same material of public electrode and same layer, as shown in Figure 8, wherein Fig. 8 is perpendicular to array base
Another sectional view on plate surface direction, if at this point, when the first signal wire S1 is touching signals line, since touching signals lines may
With 30 same layer of public electrode, so needing to ensure second signal line S2 and touching signals line mutually insulated, to avoid second signal
It is interfered with each other between line S2 and touching signals line；Therefore, second signal line S2 either with the source/drain in the first transistor T1
Same material and same layer are arranged, or are arranged with the grid same material in the first transistor T1 and same layer, or are and common electrical
30 same material of pole and same layer setting, may be implemented to simplify manufacture craft, reduce the purpose of manufacture difficulty.
It should be pointed out that the source/drain same material and same layer in common signal line 20 and the first transistor T1 are arranged,
And first signal wire S1 be data line when, then common signal line 20 and the first signal wire S1 are located at same layer, if second signal line S2
Equally it is arranged with the source/drain same material in the first transistor T1 and same layer, that is to say, that common signal line 20, the first signal
Line S1 and second signal line S2 are respectively positioned on same layer, in order to avoid mutually dry between second signal line S2 and the first signal wire S1
It disturbs, needs to ensure second signal line S2 and the first signal wire S1 mutually insulateds, may so increase manufacture craft, increase and make
Difficulty；Therefore, second signal line S2 can be set to being arranged with the grid same material in the first transistor T1 and same layer, or set
It is set to and 30 same material of public electrode and same layer setting；In this way, common signal line 20 and second signal line S2 is located at different layers, need
To pass through via (via k) electrical connections as shown in Figure 9, to be advantageously implemented the dispersion and release of electrostatic charge.
Similarly, in common signal line 20 and 30 same material of public electrode and same layer setting, and the first signal wire S1 is touch-control
When signal wire, common signal line 20 and the first signal wire S1 are still located at same layer, at this time in order to simplify manufacture craft, reduce and make hardly possible
Degree can set second signal line S2 to the source/drain same material in the first transistor T1 and same layer to be arranged, or with first
Grid same material and same layer in transistor T1 are arranged；Therefore, common signal line 20 and second signal line S2 is located at different layers, needs
To pass through via (via k) electrical connections as shown in Figure 9, to be advantageously implemented the dispersion and release of electrostatic charge.
Again similarly, the source/drain same material in common signal line 20 and the first transistor T1 and same layer setting, and first
When signal wire S1 is touching signals line, common signal line 20 and the first signal wire S1 are located at different layers, if second signal line at this time
When S2 is equally arranged with the source/drain same material in the first transistor T1 and same layer, second signal line S2 and the first signal wire S1
It not will produce then and interfere with each other positioned at different layers, and common signal line 20 and second signal line S2 is located at same layer, therefore can be straight
Electrical connection is connect, or makes and is structure as a whole, as shown in Figures 3 to 5, to simplify manufacture craft.
Again similarly, in common signal line 20 and 30 same material of public electrode and same layer setting, and the first signal wire S1 is number
When according to line, common signal line 20 and the first signal wire S1 are located at different layers, if second signal line S2 is equally and public electrode at this time
30 same materials and same layer are arranged, and second signal line S2 and the first signal wire S1, which is located at different layers and not will produce then, to be interfered with each other, and
Common signal line 20 and second signal line S2 is located at same layer, therefore can directly be electrically connected, or makes and be structure as a whole, such as Fig. 3
Shown in Fig. 5, to simplify manufacture craft.
Further, the source/drain same material in second signal line S2 and the first transistor T1 and same layer setting, and the
When one signal wire S1 is data line, in order to make data line be electrically connected with the driving chip for being set to binding region B0, so as to
Data-signal is provided for data line in driving chip, realizes display function, so data line also has for connecting in neighboring area B
The extended line S1d of the driving chip in binding region B0 is met, (driving chip is not shown) as shown in Figures 2 to 5, also, electrostatic
One end of protection circuit 10 is electrically connected with extended line S1d, in order to disperse the electrostatic on data line by electrostatic discharge protection circuit 10
Lotus.
In addition, regardless of whether extended line S1d and second signal line S2 is same layer setting, extended line S1d can be across second
Signal wire S2 extends to binding region B0, is set as and second signal as shown in Fig. 2, Fig. 4 and Fig. 5, also, by extended line S1d
Line S2 mutually insulateds are easy to cause short circuit between each signal wire to avoid the wiring congestion near second signal line S2 and influence
Display effect.Alternatively, when the extended line S1d of data line is arranged, extended line S1d can also be along second signal line S2 close to the
The side of two corner a2 and/or third corner a3 extend to binding region B0, as shown in figure 3, to avoid because of extended line S1d and
The overlapping transmission for generating parasitic capacitance and influencing signal occurs for binary signal line S2.
Specifically, in the other end of the electrostatic discharge protection circuit 10 close to the S2 settings of second signal line and second signal line S2 electricity
When connection, the other end close to the electrostatic discharge protection circuit 10 of second signal line S2 settings can be believed by connecting line 40 and second
Number line S2 electrical connections, as shown in Fig. 3 to Fig. 5 and Fig. 9, at this point, connecting line 40 can be conducting wire or static short ring.It needs
, it is noted that when connecting line is arranged, the extending direction of the extending direction and common signal line 20 of connecting line 40 can mutually hang down
Directly (as shown in Figure 3 and Figure 9), can also be mutually parallel (as shown in Figure 5), can also at an angle (as shown in Figure 4), herein
It does not limit, as long as can ensure that electrostatic discharge protection circuit 10 is electrically connected by connecting line 40 with second signal line S2.
Further, connecting line 40 can be arranged with the grid same material in the first transistor T1 and same layer, such as Fig. 6 institutes
Show；Alternatively, connecting line 40 can also be arranged with the source/drain same material in the first transistor T1 and same layer, as shown in fig. 7, its
In, Fig. 7 is the another sectional view in array substrate surface direction, at this point, when the first signal wire S1 is data line, is
It avoids short circuit occurring and interferes with each other between the connecting line 40 and data line of same layer, connecting line 40 needs and data line phase
Mutually insulation；Again alternatively, connecting line 40 can also be arranged with 30 same material of public electrode and same layer, as shown in figure 8, at this point, the
When one signal wire S1 is touching signals line, in order to avoid the generation short circuit between the connecting line 40 and touching signals line of same layer
It interferes with each other, connecting line 40 needs and touching signals line mutually insulated.
Further, the source/drain same material in second signal line S2 and the first transistor T1 and same layer setting, and
When source/drain same material and same layer in connecting line 40 and the first transistor T1 are arranged, second signal line S2 and connecting line 40
In same layer, therefore second signal line S2 can be directly electrically connected with connecting line 40, as shown in Figure 7；If second signal line S2 with
Source/drain same material and same layer in the first transistor T1 are arranged, and the same material of grid in connecting line 40 and the first transistor T1
When matter and same layer setting, second signal line S2 is located at different layers with connecting line 40, therefore second signal line S2 is needed with connecting line 40
It to be electrically connected by via (as shown in virtual coil in Fig. 6).It should be noted that no matter second signal line S2 and connecting line
Which layer 40 be located at, as long as second signal line S2 is located at different layers, second signal line S2 and connecting line 40 with connecting line 40
It just needs to be electrically connected by via, if second signal line S2 is located at same layer, second signal line S2 and connecting line with connecting line 40
40 can directly be electrically connected.
It is data line or touching signals in the first signal wire S1 it should be noted that in the actual structure of display panel
When line, the first signal wire S1 for being located at display area is sparse unlike shown in Fig. 2, but very intensive, Fig. 2
Be in order to illustrate between the first signal wire S1, electrostatic discharge protection circuit 10, second signal line S2 connection relation and installation position, and
Actual setting quantity is not represented.
Also, in array substrate other than being provided with the first signal wire S1, array substrate can also include：Along second
The extended grid line 50 in direction, the orientation of grid line 50 and the orientation of the first signal wire S1 are perpendicular, and are showing
In the actual structure of panel, the setting of grid line 50 is also comparatively dense；Also, when for the ease of making data line and grid line 50,
Occur bending to avoid data line and grid line 50 and leads to static charge buildup, the partial schematic diagram of array substrate as shown in Figure 9,
When electrostatic discharge protection circuit 10 is arranged, it is small that at least four adjacent electrostatic discharge protection circuits 10 can form an electrostatic discharge protection circuit
Group (as shown in dotted line frame e), and region of the grid line 50 between two neighboring electrostatic discharge protection circuit group e, can so protect
Card avoids data line and grid line from being bent when making, to effectively avoid static charge buildup and influence to show.
Certainly, when electrostatic discharge protection circuit group e is arranged, however it is not limited to which four electrostatic discharge protection circuits 10 form an electrostatic
Protection circuit group e can also be made of the electrostatic discharge protection circuit 10 of the other quantities such as 6,7 or 8, not limit herein
It is fixed.
In addition, when the grid same material and same layer in second signal line S2 and the first transistor T1 are arranged, due to second
Signal wire S2 is located at same layer with grid line 50, in order to avoid generating interference to the grid line scanning signal on grid line 50, needs grid line
50 be set as with second signal line S2 mutually insulateds, to ensure the normal display of display panel.
Optionally, the structure of the connecting line 40 between electrostatic discharge protection circuit group e and second signal line S2 can be
Branching shape structure, as shown in Figure 9, that is to say, that can only pass through one between electrostatic discharge protection circuit group e and second signal line S2
Connecting line 40 is electrically connected, then this connecting line 40 respectively with each electrostatic discharge protection circuit 10 in electrostatic discharge protection circuit group e
Electrical connection, structure when being electrically connected with each electrostatic discharge protection circuit 10 due to the connecting line 40 is similar to branching shape, so connecting line
40 structure can be branching shape structure；So set, wiring can be effectively reduced, wiring congestion is avoided, advantageously reduces week
The area occupied of border region.
Certainly, in embodiments of the present invention, the structure of connecting line 40 is not limited to shown in Fig. 9, can also be that other can be with
Realize the structure being electrically connected between each electrostatic discharge protection circuit 10 and second signal line S2 in electrostatic discharge protection circuit group e, herein
It is not construed as limiting.
Optionally, in embodiments of the present invention, electrostatic discharge protection circuit 10 can be all arranged close to second signal line S2,
Diagram is not provided；It is, of course, also possible to partial electrostatic protection circuit 10 is arranged close to second signal line S2, at this point, neighboring area B
Can also include：The third signal wire S3 being arranged far from the sides binding region B0 close to display area, that is to say, that in third week
Third signal wire S3 is additionally provided in border region B3, third signal wire S3 can be electrically connected with rest part electrostatic discharge protection circuit 10
It connects, for balancing the electrostatic charge on remaining first signal wire S1, therefore, rest part electrostatic discharge protection circuit 10 can be close to third
Signal wire S3 settings；And the other end of rest part electrostatic discharge protection circuit 10 can be electrically connected with third signal wire S3, such as Fig. 2
It is shown.Wherein, third signal wire S3 equally with it is public in the first neighboring area B1 and in the second neighboring area B2
Signal wire 20 is electrically connected, and to balance the electrostatic charge of entire array substrate, improves the reliability of display panel.
Specifically, third signal wire S3 can be arranged along outer edge of the display area far from binding region side, such as Fig. 2
It is shown, that is to say, that third signal wire S3 is tied up along the first display area A1, intermediate region Bm and the second display area A2 are separate
Determine the outer edge setting of the region sides B0, rest part electrostatic discharge protection circuit 10 is arranged close to third signal wire S3, to reduce the
The area occupied of three neighboring area B3, is conducive to the design of narrow frame.
Certainly, when partial electrostatic protection circuit 10 is arranged close to second signal line S2, in addition to this partial electrostatic protects electricity
Except road 10, the week close to the sides binding region B0 in third display area A3 can also be arranged in rest part electrostatic discharge protection circuit
(diagram is not provided), in border region B at this time, it may be necessary to third signal wire S3 be arranged in the B of the neighboring area, with balanced remainder data
Electrostatic charge on line.
Optionally, in embodiments of the present invention, the concrete structure of electrostatic discharge protection circuit 10 may include as shown in Figure 10：
Second transistor T2 and third transistor T3；
The grid G 2 and source S 2 of second transistor T2 is electrically connected with the first signal wire S1, the drain electrode of second transistor T2
D2 is electrically connected with second signal line S2；
The grid G 3 and source S 3 of third transistor T3 is electrically connected with second signal line S2, the drain electrode of third transistor T3
D3 is electrically connected with the first signal wire S1.
To which by electrostatic discharge protection circuit 10 shown in Fig. 10, the electrostatic charge that accumulated on the first signal wire S1 can be released
It is put on second signal line S2, or the electrostatic charge accumulated on second signal line S2 is discharged on the first signal wire S1, to avoid
Occur the problem of the accumulation of partial electrostatic lotus excessively causes electrostatic breakdown, and display panel is caused not show normally；Also, this
The electrostatic discharge protection circuit 10 of kind structure not only can be used for large-sized display panel, but also can be used for the display panel of small size,
It is not limited thereto.
Specifically, second transistor T2 and third transistor T3 can be P-type transistor or be N-type transistor.
It is N with second transistor T2 and third transistor T3 in conjunction with the structure of electrostatic discharge protection circuit 10 shown in Fig. 10
For transistor npn npn, the course of work of electrostatic discharge protection circuit 10 is：It is electric caused by the electrostatic charge accumulated on the first signal wire S1
When pressure is more than the first predetermined threshold value so that second transistor T2 is opened, and electrostatic charge is transmitted on second signal line S2, so that
The electrostatic charge accumulated on first signal wire S1 is rapidly released；And caused by the electrostatic charge accumulated on second signal line S2
When voltage is more than the second predetermined threshold value, third transistor T3 is opened, so that the electrostatic charge accumulated on second signal line S2 is rapidly
It is released；Therefore, by electrostatic discharge protection circuit 10, can effectively disperse to be accumulated in the first signal wire S1 or second signal line S2
On electrostatic charge, to avoid partial electrostatic lotus it is excessive caused by electrostatic breakdown, thereby may be ensured that display area is normally shown
Image.
Similarly, when second transistor T2 and third transistor T3 are P-type transistor, product on the first signal wire S1 is needed
Voltage caused by tired electrostatic charge is less than voltage caused by the electrostatic charge accumulated on third predetermined threshold value or second signal line S2
It, in order to discharge electrostatic charge, is kept away less than the 4th predetermined threshold value so that second transistor T2 or third transistor T3 open
Exempting from the accumulation of partial electrostatic lotus excessively leads to electrostatic breakdown, ensures that display area normally shows image.
Certainly, the first predetermined threshold value and third predetermined threshold value can be the cut-in voltages of second transistor T2, and second is default
Threshold value and the 4th predetermined threshold value can be the cut-in voltages of third transistor T3；Also, the first predetermined threshold value and the second default threshold
Value can be identical, can not also be identical, needs according to actual demand, the unlatching to second transistor T2 and third transistor T3
Voltage is correspondingly arranged, and is not limited thereto.
Can also include being located at periphery it should be pointed out that being not limited to the above-mentioned transistor referred in array substrate
The transistor in driving circuit in region, and referred in the present invention transistor (such as the first transistor, second transistor and
Third transistor etc.) in active layer be made of amorphous silicon material, so by array substrate structure provided in an embodiment of the present invention
At display panel be non-crystalline silicon product.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, as shown in figure 11, can wrap
It includes：Liquid crystal display panel m；Wherein, the structure of liquid crystal display panel m may include as shown in figure 12：Such as the embodiment of the present invention
The above-mentioned array substrate 100 provided, and the opposite substrate 200 set opposite with array substrate 100, and it is located at array substrate
Liquid crystal 300 between 100 and opposite substrate 200.
Specifically, which can be mobile phone (as shown in figure 11), tablet computer, television set, display, notebook
Any product or component with display function such as computer, Digital Frame, navigator.Other for the display device must can not
Few component part is it will be apparent to an ordinarily skilled person in the art that having, and this will not be repeated here, also be should not be used as pair
The limitation of the present invention.
In conclusion an embodiment of the present invention provides a kind of array substrate and display device, by will at least partly electrostatic
Protection circuit is arranged close to second signal line, and second signal line is arranged at least adjacent to the second corner so that close to the second corner
The first signal wire on electrostatic charge can be released by electrostatic discharge protection circuit, the electrostatic avoided on the first signal wire is residual
It stays, and then effectively prevents electrostatic breakdown caused by accumulation of static electricity, to be conducive to improve the display quality of picture.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (18)
1. a kind of array substrate, including：
Display area, and the neighboring area around the display area；
The neighboring area includes：Binding region；The orientation of the binding region and the display area is first direction；
The display area includes：It is arranged far from the binding region side and shape is the first corner of on-right angle, and leans on
Second corner of the nearly binding region side setting；
The array substrate further includes：A plurality of first signal wire arranged in a second direction；The second direction and described first
Direction is mutually perpendicular to；
The neighboring area further includes：Multiple electrostatic discharge protection circuits, and the second letter at least adjacent to second corner setting
Number line；At least partly described electrostatic discharge protection circuit is arranged close to the second signal line；And the one of each electrostatic discharge protection circuit
Hold the another of the electrostatic discharge protection circuit for being electrically connected, being arranged close to the second signal line corresponding with each first signal wire
End is electrically connected with the second signal line.
2. array substrate as described in claim 1, which is characterized in that the display area includes：First display area, second
Display area and third display area；
It is intermediate region between first display area and second display area；The intermediate region belongs to the periphery
Region；
First display area, the intermediate region and second display area are respectively positioned on the same of the third display area
Side.
3. array substrate as claimed in claim 2, which is characterized in that first corner is that first display area is separate
The on-right angle corner of the intermediate region side；
Second corner is corner of the third display area close to the binding region side.
4. array substrate as claimed in claim 3, which is characterized in that the display area further includes：Close to the binding area
Domain side is arranged and belongs to the third corner of the third display area, and far from the binding region and the intermediate region
It is arranged and belongs to the 4th corner of second display area；
Second corner, the third corner and the 4th corner are on-right angle corner.
5. array substrate as claimed in claim 4, which is characterized in that the second signal line is also provided at close to the third
In the neighboring area of corner.
6. array substrate as claimed in claim 5, which is characterized in that the second signal line is along institute in the display area
State the outer edge setting of the second corner and the third corner；
The shape of the second signal line is arc-shaped or step-like.
7. array substrate as claimed in claim 5, which is characterized in that the part electrostatic discharge protection circuit is close to second letter
The setting of number line；
The neighboring area further includes：The third signal wire being arranged far from the binding region side close to the display area；
Electrostatic discharge protection circuit described in rest part is arranged close to the third signal wire；And electrostatic discharge protection circuit described in rest part
The other end be electrically connected with the third signal wire.
8. array substrate as claimed in claim 5, which is characterized in that the electrostatic close to second signal line setting is anti-
Protection circuit is respectively arranged at the second signal line close to the side of second corner and the second signal line close to described
The side of third corner；Or,
Close to the electrostatic discharge protection circuit of second signal line setting, the second signal line is respectively arranged at far from described
The side of the side of second corner and the second signal line far from the third corner；Or,
Close to the electrostatic discharge protection circuit of second signal line setting, the second signal line is respectively arranged at far from described
The side and the second signal line of second corner and the third corner are close to second corner and the third corner
Side.
9. array substrate as claimed in claim 8, which is characterized in that the display area further includes：The first transistor；It is described
Second signal line and the source/drain same material in the first transistor and same layer setting；First signal wire is data line；
The second signal line and the data line mutually insulated；Or,
The second signal line and the grid same material in the first transistor and same layer setting；Or,
The display area further includes：It is arranged in first signal wire far from the outermost public of the array substrate side
Electrode；The second signal line and the public electrode same material and same layer setting；First signal wire is touching signals line；
The second signal line and the touching signals line mutually insulated.
10. array substrate as claimed in claim 9, which is characterized in that in the second signal line and the first transistor
Source/drain same material and same layer be arranged；First signal wire is data line；
The data line has the extended line for connecting the driving chip in the binding region in the neighboring area；It is described
One end of electrostatic discharge protection circuit is electrically connected with the extended line；
The extended line is extended to along the second signal line close to the side of second corner and/or the third corner
The binding region；Or, the extended line extends to the binding region across the second signal line, and the extended line with
The second signal line mutually insulated.
11. array substrate as claimed in claim 9, which is characterized in that close to the electrostatic of second signal line setting
The other end of protection circuit is electrically connected by connecting line with the second signal line；
The connecting line is conducting wire or static short ring.
12. array substrate as claimed in claim 11, which is characterized in that the connecting line and the grid in the first transistor
Pole same material and same layer setting；Or,
The connecting line and the source/drain same material in the first transistor and same layer setting；First signal wire is number
According to line；The connecting line and the data line mutually insulated；Or,
The connecting line and the public electrode same material and same layer setting；First signal wire is touching signals line；It is described
Connecting line and the touching signals line mutually insulated.
13. array substrate as claimed in claim 11, which is characterized in that the array substrate further includes：Along the second party
To extended grid line；
At least four adjacent electrostatic discharge protection circuits form an electrostatic discharge protection circuit group；
The grid line runs through the region between the two neighboring electrostatic discharge protection circuit group；
The second signal line and the grid same material in the first transistor and same layer setting；The grid line and described second
Signal wire mutually insulated.
14. array substrate as claimed in claim 13, which is characterized in that be located at the electrostatic discharge protection circuit group and described the
The structure of connecting line between binary signal line is branching shape structure.
15. array substrate as described in claim 1, which is characterized in that the electrostatic discharge protection circuit includes：Second transistor and
Third transistor；
The grid and source electrode of the second transistor are electrically connected with first signal wire, the drain electrode of the second transistor with
The second signal line electrical connection；
The grid and source electrode of the third transistor are electrically connected with the second signal line, the drain electrode of the third transistor with
The first signal wire electrical connection.
16. array substrate as claimed in claim 15, which is characterized in that the second transistor and the third transistor are equal
For P-type transistor or it is N-type transistor.
17. such as claim 1-16 any one of them array substrates, which is characterized in that the current potential of the second signal line is public affairs
The current potential of signal altogether；Or the second signal line is ground signal line.
18. a kind of display device, which is characterized in that including：Liquid crystal display panel；
The liquid crystal display panel includes：Such as claim 1-17 any one of them array substrates, with the array substrate phase
Pair and the opposite substrate set, and the liquid crystal between the array substrate and the opposite substrate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810273263.8A CN108519707B (en) | 2018-03-29 | 2018-03-29 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810273263.8A CN108519707B (en) | 2018-03-29 | 2018-03-29 | Array substrate and display device |
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| CN108519707B CN108519707B (en) | 2022-06-21 |
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| CN109377933A (en) * | 2018-12-26 | 2019-02-22 | 厦门天马微电子有限公司 | A kind of driving method of display panel, display panel and display device |
| CN109377874A (en) * | 2018-12-21 | 2019-02-22 | 上海中航光电子有限公司 | Display panel and display device |
| CN109445210A (en) * | 2018-12-27 | 2019-03-08 | 上海天马微电子有限公司 | A kind of display panel and display device |
| CN109545089A (en) * | 2018-12-29 | 2019-03-29 | 厦门天马微电子有限公司 | A kind of display panel and display device |
| CN109765737A (en) * | 2019-03-20 | 2019-05-17 | 厦门天马微电子有限公司 | A kind of array substrate and display device |
| WO2021238801A1 (en) * | 2020-05-29 | 2021-12-02 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| CN114863806A (en) * | 2022-04-11 | 2022-08-05 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2022266884A1 (en) * | 2021-06-23 | 2022-12-29 | 京东方科技集团股份有限公司 | Display substrate, display device and compensation method therefor |
| WO2023115406A1 (en) * | 2021-12-22 | 2023-06-29 | Boe Technology Group Co., Ltd. | Array substrate and display apparatus |
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