CN108509382A

CN108509382A - A method of overlength sequence fast convolution operation is realized based on FPGA

Info

Publication number: CN108509382A
Application number: CN201810276062.3A
Authority: CN
Inventors: 孙桂玲; 王鹏霄; 郑祥雨; 陈雨歌; 辛港涛; 陈江韬
Original assignee: Nankai University
Current assignee: Nankai University
Priority date: 2018-03-27
Filing date: 2018-03-27
Publication date: 2018-09-07
Anticipated expiration: 2038-03-27
Also published as: CN108509382B

Abstract

The invention discloses a kind of methods for realizing overlength sequence fast convolution operation based on FPGA.Two paths of signals is acquired by AD sampling modules first, then collected two paths of data is stored in the two panels random access memory (SRAM) outside FPGA respectively in order, data are taken out from two panels SRAM in the opposite order in burst-length later carries out fast convolution operation, in the DDR2 outside mass data deposit FPGA that operation is obtained simultaneously, the fast convolution operation to two paths of signals based on FPGA is finally realized.

Description

A method of overlength sequence fast convolution operation is realized based on FPGA

【Technical field】

The invention belongs to space orientation problem high speed Real-time digital signal processing field, to two paths of signals carry out high speed, Big depth-sampling and convolution algorithm is to differentiate the small phase difference of two paths of signals.AD sampling modules are adopted using binary channels 12bit AD Collect the Cyclone IV series of modules A N926, FPGA using altera corp, model Cyclone IV EP4CE115F29C7N.The two panels SRAM of storage data is read by way of burst, burst-length adds up, greatly improves successively Arithmetic speed finally realizes the fast convolution operation of two paths of signals within a short period of time.

【Background technology】

In space orientation problem, the phase difference of two paths of signals is an important parameter, can be with by this phase difference Realize that space accurately positions, and convolution algorithm is the important method for finding this phase difference.

When the phase difference of two paths of signals and its it is small when, the resolution of such as optical signal, phase difference must pass through high sampling Convolution is carried out after the sampling of rate and big depth, just can be achieved.Currently, being mainly to two-way discrete digital signal progress convolution algorithm It is realized by software, and the speed that software executes overlength sequence convolution is relatively low, cannot be satisfied to igh-speed wire-rod production line real-time Requirement, and the characteristics of realized using FPGA, its rich hardware resource and concurrent operation can be made full use of, greatly improve Arithmetic speed, to realize sterically defined real-time.

【Invention content】

This method realizes that the fast convolution operation of two paths of signals, technical solution include the following aspects using FPGA：

1.AD modules acquiring datas

Two-way analog signal is sampled using binary channels 12bit AD acquisition modules AN926, sample frequency is 50Mhz, sampling time 5.243ms, i.e. sampling obtain the data of two groups of 262144 12bit after terminating.

2. the outer SRAM of FPGA pieces is written in data

External Static RAM uses the SRAM of two panels model IS61LV25616AL, is connected to by GPIO mouthfuls On FPGA, the storage resource of the SRAM is 256Kx 16bit, meets memory requirement.

Since the data line of the SRAM is 16bit, and the data that the AD acquisitions of storage are actually needed are only 12, therefore In external hardware design, D12, D13, D14, D15 of the SRAM are directly grounded.

Data write-in external SRAM be by FPGA inside control logic control tristate bus line realize.First when need When SRAM is written in the data of AD acquisitions, FPGA controls A/D module and obtains the bus right to use, and FPGA is controlled again at the end of write-in A/D module processed discharges bus, gives bus control right to fast convolution module.3. reading data from SRAM

In order to coordinate fast convolution methods, the method that data are read from SRAM is the key component of this method.Using prominent The mode of hair reads external SRAM, and burst-length reads burst each time since 256, reads length and is increased by 256.It adopts Two panels SRAM is read out with the sequence being completely reversed, i.e. the reading order of SRAM_A is 0,1,2,3 when the first secondary burst ... 255；The reading order of SRAM_B be 255,254,253 ... 2,1,0.The reading order of SRAM_A is 0,1,2 when the second secondary burst, 3…511；The reading order of SRAM_B be 511,510,509 ... 2,1,0.

4. fast convolution operation

The data read from SRAM are sent into fast convolution module, when the first secondary burst, set burst-length as 256, Data parallel is inputted in 256 multipliers successively in order, is used in combination latch to latch multiplication result, Mei Gesuo Storage separate counts successively, the output simultaneously at the end of all latch count full 256 namely the first secondary bursts as a result, Obtain 256 convolution algorithm results that the first secondary burst is calculated.Immediately after enter the second secondary burst, burst-length 512, The data of reading are still sent into fast convolution module, when all latch count full 512, while exporting result.With this side Formula, whole convolution results can be obtained by passing through 1024 secondary bursts altogether.

5. operation result is stored in DDR2 outside FPGA

DRR2 SDRAM have the characteristics that large capacity, high read and write rate.The read-write mode of DDR2 is burst mode.Whenever fast After fast convolution module carries out burst read operation of completion and exports result, DDR2, which just enters, writes burst, length 256, according to The sequence of latch writes the result into DDR2 successively.Before the reading of next secondary burst starts, DDR2, which will write, to be finished and discharges bus.

【The advantages and positive effects of the present invention】

That present invention utilizes FPGA hardwares is resourceful, can parallel computation the characteristics of, realize overlength sequence with hardware circuit The fast convolution operation of row, ensure that the real-time of igh-speed wire-rod production line under the premise of meeting measurement accuracy.If using passing The software convolution method of system reads data from memory and is multiplied accumulating by turn, when convolution completes two sequences of 262144 length Row need to consume 1+2+3+4+ ... 262143+262144=3.436*10 altogether¹⁰A clock cycle, when clock is 100Mhz, It is about 5min43s to need the time consumed；And 256+512+768+ ...+261888+262144=need to only be consumed using this method 1.3435*10⁸A clock cycle, when clock is 100Mhz, it is about 1.34s to need the time consumed, and arithmetic speed improves 255 times, greatly improve arithmetic speed.

【Description of the drawings】

Fig. 1 is system principle diagram；

Fig. 2 is fast convolution module principle block diagram；

Fig. 3 is first via sinusoidal signal；

Fig. 4 is the second tunnel sinusoidal signal；

Fig. 5 is the small phase difference of two paths of signals；

Fig. 6 is fast convolution operation result；

Fig. 7 is fast convolution methods flow chart.

【Specific implementation mode】

In order to become apparent to illustrate embodiment of the present invention, with reference to attached drawing hereinafter, the present invention is done further Explanation.

As shown in Figure 3-Figure 5, there is the sinusoidal signal of small phase difference to carry out convolution algorithm two-way, two paths of signals passes through Length after A/D module acquisition is 262144, it is stored in order in the SRAM outside FPGA.Next it carries out successively 1024 secondary burst read operations read length and successively increase 256 since 256, the obtained data of reverse read two panels SRAM are sent Enter fast convolution module, as shown in Figure 2.256 convolution results are obtained simultaneously at the end of burst, are stored in outside FPGA in order In DDR2.Fast convolution operation terminates after 1024 secondary bursts, and convolution results are as shown in Figure 6, it can be seen that, although two paths of signals Phase difference is extremely small, but can still distinguish peak value and appear in left-of-center position.

Claims

1. a kind of method for realizing overlength sequence fast convolution operation based on FPGA, the two paths of data that this method acquires A/D module It is stored in outside FPGA in the independent SRAM of two panels by tristate bus line, then two panels SRAM is carried out respectively in burst-length Inverted sequence is read, and the data of reading is sent into fast convolution module, while operation result being stored in the DDR2 outside FPGA.

2. this method takes the mode of burst to be written and read operation to data, burst read operation terminates that 256 can be obtained each time For a convolution algorithm as a result, burst-length is successively increased since 256, each burst-length increases by 256, carries out 1024 secondary bursts altogether Read operation, so that it may complete the sequence convolution of two row, 262144 length, speed improves 255 times than traditional software approach.