CN108509013B

CN108509013B - Method and device for processing instruction

Info

Publication number: CN108509013B
Application number: CN201710114931.8A
Authority: CN
Inventors: 黄罡; 梁文亮
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-02-28
Filing date: 2017-02-28
Publication date: 2020-06-26
Anticipated expiration: 2037-02-28
Also published as: CN108509013A

Abstract

The embodiment of the invention provides a method and a device for processing instructions, relates to the technical field of computers, and can save the time of a processor for executing tasks and reduce the power consumption of the processor. The method comprises the following steps: the method comprises the steps that a processor acquires a first instruction, wherein the first instruction comprises a first sequence and is used for instructing the processor to read at least one micro-operation corresponding to the first sequence; the processor reads at least one micro-operation corresponding to the first sequence according to the first instruction, wherein the at least one micro-operation is a saved result obtained after decoding at least one second instruction; the processor executes the at least one micro-operation.

Description

Method and device for processing instruction

Technical Field

The embodiment of the invention relates to the technical field of computers, in particular to a method and a device for processing instructions.

Background

The processor is an operation core and a control core of the device, and when the processor executes a task, the processor can generally perform the tasks of fetching an instruction, translating the instruction (i.e., decoding the instruction), and executing a micro-operation (the micro-operation is a result obtained after decoding the instruction).

In the case of a current processor executing a large number of repeated tasks (a task is usually composed of at least one instruction), the processor repeatedly fetches and decodes the same instruction, and the repeated fetching and decoding of the same instruction by the processor results in a longer time for the processor to execute the task, which increases the power consumption of the processor.

Disclosure of Invention

The application provides a method and a device for processing instructions, which can save the time of a processor for executing tasks and reduce the power consumption of the processor.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, a method of processing instructions is provided, the method comprising: the processor acquires a first instruction (the first instruction comprises a first sequence) for instructing the processor to read at least one micro-operation corresponding to the first sequence, reads the at least one micro-operation corresponding to the first sequence according to the first instruction, and executes the at least one micro-operation. Wherein the at least one micro-operation is a result of the stored decoded at least one second instruction.

In this application, when a processor executes a task (a task is usually composed of at least one second instruction), after the processor acquires a first instruction (the first instruction includes a first sequence) for instructing the processor to read at least one micro-operation corresponding to the first sequence, the processor may read at least one micro-operation corresponding to the first sequence according to the first instruction; and because the at least one micro-operation is a stored micro-operation obtained after decoding the at least one second instruction, when the processor repeatedly executes a task consisting of the at least one second instruction, the processor does not need to repeatedly acquire the at least one second instruction and repeatedly decode the at least one second instruction, that is, the processor can directly execute the stored micro-operation obtained after decoding the at least one second instruction (that is, the processor can directly complete the execution of the at least one second instruction), thereby saving the time for the processor to execute the task and reducing the power consumption of the processor.

In a first possible implementation manner of the first aspect, the number of the at least one micro-operation is specifically at least two, the at least two micro-operations may include at least one first micro-operation and at least one second micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the one first micro-operation when the processor executes the one first micro-operation for the first time. The method for the processor to execute the at least one micro-operation may include: the processor corrects the first operation address in each first micro-operation, and the processor executes each first micro-operation and at least one second micro-operation after correcting the first operation address.

In a second possible implementation manner of the first aspect, the at least one micro-operation is at least one first micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the one first micro-operation when the processor executes the one first micro-operation for the first time. The method for the processor to execute the at least one micro-operation may include: the processor corrects the first operation address in each first micro-operation, and the processor executes each first micro-operation after correcting the first operation address.

In the present application, the micro-operations may be divided into two types, one type being a first micro-operation for acquiring data or storing data, and the other type being a second micro-operation for operating on data. Since the first micro-operation is used to obtain data or store data, and the data is usually stored in a certain storage address in the storage medium, the storage address of the data is included in the first micro-operation, and the storage address of the data in the first micro-operation may be referred to as an operation address of the first micro-operation. However, since the second micro-operation is used for operating on data, and the operation is usually implemented by a register without involving a storage address, the second micro-operation may not include the storage address of the data, that is, the second micro-operation may have no operation address.

Generally, since different data have different storage addresses, when a processor first executes a first micro-operation to obtain or store one datum, the storage address of the datum may be different from the storage address of the datum when the processor executes the first micro-operation again to obtain or store another datum, that is, generally, the operation address of the first micro-operation (for example, the first operation address included in the first micro-operation) when the processor first executes the first micro-operation may be different from the operation address of the first micro-operation when the processor executes the first micro-operation again. In this application, each saved first micro-operation includes the first operation address, so that in order to ensure that one first micro-operation can be correctly executed each time, except for the first execution of the one first micro-operation, the first operation address in the one first micro-operation may be corrected before the rest of the first micro-operations are executed each time.

In a third possible implementation manner of the first aspect, the first instruction may further include an address offset, and for the one first micro-operation, the address offset is an offset of the second operation address (the second operation address is an operation address of the one first micro-operation when the processor currently executes the one first micro-operation) with respect to the first operation address in the one first micro-operation. Since the address offset is the same for each first micro-operation, the method for the processor to correct the address of the first operation in each first micro-operation may include: for each first micro-operation, the processor may perform process (1) described below to modify the first operation address in the each first micro-operation. Wherein, the process (1) can be: the processor corrects a first operation address in a first micro-operation to a second operation address according to the address offset.

In this application, since the operation address of the first micro-operation when the processor executes the first micro-operation for the first time is different from the operation address of the first micro-operation when the processor executes the first micro-operation again, and the first operation address in the first micro-operation is the operation address of the first micro-operation when the processor executes the first micro-operation for the first time, before the processor executes the first micro-operation again, the first operation address in the first micro-operation may be corrected to the operation address (i.e., the second operation address) of the first micro-operation when the processor executes the first micro-operation for the current time according to the address offset in the instruction obtained by the processor, so as to ensure that the first micro-operation can be executed correctly when the processor executes the first micro-operation again.

In a fourth possible implementation manner of the first aspect, in a case that the processor executes the at least one second instruction for the first time, the method for processing an instruction provided by the present application may further include: the processor obtains a third instruction (the third instruction includes the first sequence) for instructing the processor to save the corresponding relationship between the first sequence and the at least one micro-operation, and the processor saves the corresponding relationship between the first sequence and the at least one micro-operation (namely, a result obtained after decoding the at least one second instruction) according to the third instruction.

In a second aspect, a processor is provided that includes a control unit and a processing unit. The control unit is configured to obtain a first instruction (the instruction includes a first sequence) for instructing the control unit to read at least one micro-operation corresponding to the first sequence, and read the at least one micro-operation corresponding to the first sequence according to the first instruction. The processing unit is used for executing the at least one micro-operation read by the control unit. Wherein the at least one micro-operation is a result of the stored decoded at least one second instruction.

In a first possible implementation manner of the second aspect, the number of the at least one micro-operation is specifically at least two, the at least two micro-operations may include at least one first micro-operation and at least one second micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the one first micro-operation when the control unit executes the one first micro-operation for the first time. The processing unit is specifically configured to correct a first operation address in each first micro-operation, and execute each first micro-operation and the at least one second micro-operation after the first operation address is corrected.

In a second possible implementation manner of the second aspect, the at least one micro-operation is at least one first micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the one first micro-operation when the processing unit executes the one first micro-operation for the first time. The processing unit is specifically configured to correct a first operation address in each first micro-operation, and execute each first micro-operation after the first operation address is corrected.

In a third possible implementation manner of the second aspect, the first instruction may further include an address offset, and for one first micro-operation, the address offset is an offset of the second operation address (the second operation address is an operation address of the one first micro-operation when the control unit currently executes the one first micro-operation) with respect to the first operation address in the one first micro-operation. Since the address offset is the same for each first micro-operation, the processing unit is specifically configured to perform, for each first micro-operation, the following procedure (2) to correct the first operation address in each first micro-operation. Wherein the process (2) is as follows: the processing unit corrects a first operation address in a first micro-operation into a second operation address according to the address offset.

In a fourth possible implementation manner of the second aspect, the control unit is further configured to, when the processing unit executes at least one second instruction for the first time, obtain a third instruction (where the third instruction includes the first sequence) for instructing the control unit to store a correspondence between the first sequence and at least one micro-operation, and store, according to the third instruction, a correspondence between the first sequence and the at least one micro-operation.

In a fifth possible implementation manner of the second aspect, the number of the processing units is at least two. For each of the at least two processing units, the control unit performs the following process (3) to read at least one micro-operation corresponding to the first sequence according to the first instruction:

the control unit is further configured to control one processing unit of the at least two processing units to obtain instruction information for instructing the one processing unit to execute at least one third micro-operation, where the at least one third micro-operation is a micro-operation in the at least one micro-operation; the control unit is specifically configured to control the processing unit to read the at least one third micro-operation corresponding to the first sequence and indicated by the indication information according to the indication information and a first instruction; the processing unit is specifically configured to execute the at least one third micro-operation that the control unit controls the processing unit to read.

For a description of the technical effect of the second aspect or any one of its possible implementations, reference may be specifically made to the above-mentioned description of the technical effect of the first aspect or any one of its possible implementations, and details are not described here again.

In a third aspect, there is provided an apparatus for processing instructions, the apparatus comprising the processor of the second aspect or any one of its possible implementations.

In a fourth aspect, a computer-readable storage medium is provided, which includes computer instructions that, when executed on a processor, cause the processor to perform the method for processing instructions of the first aspect or any one of its possible implementations.

In a fifth aspect, there is provided a computer program product comprising computer instructions, which when run on a processor, causes the processor to perform the method of processing instructions of the first aspect or any one of its possible implementations.

For the description of the technical effects of the third aspect, the fourth aspect and the fifth aspect, reference may be specifically made to the above-mentioned description of the technical effects of the first aspect or any one of the possible implementation manners thereof, and details are not repeated here.

Drawings

Fig. 1 is a schematic diagram of a hardware structure of a server according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a hardware structure of a processor according to an embodiment of the present invention;

FIG. 3 is a first diagram illustrating a method for processing instructions according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a second method for processing instructions according to an embodiment of the present invention;

FIG. 5 is a block diagram of a method for processing instructions according to an embodiment of the present invention;

FIG. 6 is a block diagram illustrating a fourth method for processing instructions according to an embodiment of the present invention;

FIG. 7 is a block diagram illustrating a fifth exemplary method for processing instructions according to the present invention;

FIG. 8 is a flowchart illustrating a data flow based micro-operation performed by a processor according to an embodiment of the present invention;

FIG. 9 is a first block diagram illustrating a processor according to an embodiment of the present invention;

fig. 10 is a second schematic structural diagram of a processor according to an embodiment of the present invention;

fig. 11 is a third schematic structural diagram of a processor according to an embodiment of the present invention.

Detailed Description

In the embodiments of the present invention, words such as "exemplary" or "for example" are used to mean serving as examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "e.g.," an embodiment of the present invention is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

The terms "first", "second", and "third", etc. in the embodiments of the present invention are used for distinguishing different objects, not for describing a particular order of the objects. For example, the first, second, and third instructions, etc. are for distinguishing between different instructions, rather than for describing a particular order of the instructions.

In the description of the present invention, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of processing units refers to two or more processing units.

Generally, in the case of a processor executing a large number of repeated tasks, the processor repeatedly fetches and decodes the same instruction, and repeatedly fetches and decodes the same instruction, which results in a longer time for the processor to execute the tasks (one task usually consists of at least one instruction), and increases the power consumption of the processor.

In order to solve the above problem, embodiments of the present invention provide a method and an apparatus for processing an instruction, which can save the time for a processor to execute a task and reduce the power consumption of the processor. Specifically, the method and apparatus for processing instructions according to the embodiments of the present invention will be described in detail in the following embodiments.

The method for processing the instruction provided by the embodiment of the invention can be applied to an apparatus for processing the instruction, and the apparatus for processing the instruction can be a device comprising a processor. The device may be a terminal device or a network device, such as a computer, a smart phone, a server or a base station. The device may also be other types of terminal devices or network devices, and embodiments of the present invention are not limited in particular.

The method for processing the instruction provided by the embodiment of the invention can be applied to a scenario that a processor executes a large number of repeated tasks (each task is composed of at least one instruction, for example, at least one second instruction in the embodiment of the invention). For example, in a communication system adopting a fifth generation mobile communication technology (hereinafter, referred to as a 5G communication system), each device/network element (e.g., a server, etc.) may need to perform a large number of repeated tasks during communication. Therefore, in the 5G communication system, when these devices/network elements perform these repeated tasks, each instruction in the task may be processed by using the method for processing instructions provided by the embodiment of the present invention.

The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

By way of example, taking a device for processing instructions provided by an embodiment of the present invention as a server as an example, the following specifically describes each constituent component of the server with reference to fig. 1. As shown in fig. 1, the server includes a processor 01 and a memory 02. It will be appreciated that the architecture of the server shown in fig. 1 does not constitute a limitation on the server, and may include more or fewer components than those shown in fig. 1, or may combine some of the components shown in fig. 1 (e.g., the processor 01 and memory 02 may be integrated together), or may be arranged differently than those shown in fig. 1.

The processor 01 may be a Central Processing Unit (CPU), or may be other general-purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like. The general purpose processor may be a microprocessor or any conventional processor, among others.

The memory 02 may store one or more instructions. When the apparatus for processing an instruction processes an instruction, the instruction may be fetched from the memory 02 by the processor 01 and processed. The memory may be a volatile memory, such as a random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.

Illustratively, the various constituent components of the processor will be described in greater detail below in conjunction with FIG. 2. As shown in fig. 2, the processor may include: a controller 11, an operator 12 and a register 13. It will be understood that the configuration of the processor shown in fig. 2 does not constitute a limitation on the processor, and may include more or less components than those shown in fig. 2, or may combine some of the components shown in fig. 2, or may be arranged differently than those shown in fig. 2.

The controller 11 may be configured to fetch an instruction and decode the fetched instruction to obtain a micro-operation. Alternatively, the controller 11 is further configured to send a control signal to the arithmetic unit 12 for controlling the arithmetic unit 12 to execute a micro-operation obtained after the controller 11 decodes the instruction.

For example, in this embodiment of the present invention, the micro-operations obtained after the controller decodes the instruction may include: a micro operation for acquiring data (which may be referred to as a read operation, for example), a micro operation for storing data (which may be referred to as a write operation, for example), a micro operation for operating on data (which may be referred to as an arithmetic operation, for example), and the like. The specific details may be determined according to practical situations, and the embodiments of the present invention are not limited.

The operator 12 may be used to execute micro-operations resulting from the decoding of instructions by the controller 11.

The registers 13 may include general purpose registers, special purpose registers, or control registers, among others. General registers may be divided into fixed point number registers and floating point number registers, which are used to hold register operands and operation results in instructions. General purpose registers are important components of the processor, and most instructions access the general purpose registers. A special register is a register that is needed to perform some special operation. Control registers are typically used to indicate the state of the processor processing instructions. The control registers may include privilege status registers, condition code registers, handling exception crash registers, error detection registers, and the like.

The execution main body of the method for processing the instruction provided by the embodiment of the invention can be a processor, and can also be a functional module in the processor. The following takes an execution subject of the method for processing instructions as an example of a processor, and an exemplary description is given of the method for processing instructions provided by the embodiment of the present invention.

As shown in fig. 3, an embodiment of the present invention provides a method for processing an instruction, which includes the following steps S101-S108.

S101, the processor acquires a third instruction, wherein the third instruction comprises a first sequence.

The third instruction may be configured to instruct the processor to store a correspondence between the first sequence and at least one micro-operation, where the at least one micro-operation is a result obtained after decoding the at least one second instruction. The at least one second instruction constitutes a task to be performed by the processor.

Typically, the tasks performed by the processor are composed of instructions stored in a memory accessible to the processor, which may be a memory integrated in the processor or a memory in the device in which the processor resides (e.g., a hard disk in the device). For example, when a device on which the processor is located performs a task, the task may be performed by the processor. In particular, the processor may retrieve instructions that make up the task from the memory of the device and process the instructions to perform the task.

For example, it is assumed that when the processor performs a task of calculating the sum of data a and data b, the task may be performed by the processor. In particular, instructions indicating the sum of the calculation data a and the calculation data b may be retrieved from the memory of the device by the processor, which may then process the instructions to perform the task.

In this embodiment of the present invention, the task executed by the processor may be composed of at least one second instruction, and the processor may obtain, when the task composed of the at least one second instruction is executed for the first time (that is, the processor executes the at least one second instruction for the first time), a third instruction for instructing the processor to store a correspondence between the first sequence and at least one micro-operation obtained after decoding the at least one second instruction, that is, the processor executes the above S101. In this way, in the case where the processor executes the task composed of the at least one second instruction for the first time, the processor may save the correspondence between the first sequence and the at least one micro-operation obtained after decoding the at least one second instruction. The specific process of the processor executing the at least one second instruction for the first time will be described in detail in S102-S104 below.

Optionally, in this embodiment of the present invention, the processor may store, through a predefined interface, a correspondence between the first sequence and at least one micro-operation obtained after decoding the at least one second instruction. For example, the predefined interface may be a predefined interface function, which may be expressed as:

Store uop(Serial No，Function name){}；

wherein, Store uop represents save micro-operation (specifically, Store represents save, uop represents micro-operation). Serial No represents a sequence number (e.g., the first sequence that may be provided for embodiments of the present invention). Function name represents the name of the Function module; the function module name may be a function name of a function/functions in an instruction (e.g., a second instruction that may be provided for embodiments of the present invention); the function name represents, in the interface function, all the micro-operations obtained after the function indicated by the function name is decoded. The code sections of the micro-operations needing to be saved are defined in the specification.

In combination with the above description of the interface function provided by the embodiment of the present invention, the interface function specifically indicates: and saving the corresponding relation between the Serial No and all the micro-operations obtained after decoding the Function indicated by the Function name. It is understood that, in the embodiment of the present invention, if the first sequence and the at least one micro-operation obtained after decoding the at least one second instruction are saved, then the Serial No in the interface Function may be the first sequence, the Function name may include Function names of all functions in the at least one second instruction, and the code segment of the at least one micro-operation obtained after decoding the at least one second instruction is in { }.

Optionally, the third instruction may be input into the processor (or a device where the processor is located) by a user, or may be sent to the processor (or a device where the processor is located) by another device.

In an embodiment of the present invention, the first sequence may be a predefined string of binary numbers, for example, the first sequence may be represented as 0001.

S102, the processor acquires at least one second instruction.

In this embodiment of the present invention, the at least one second instruction may be at least one instruction that constitutes a task to be executed by the processor and is acquired by the processor after the processor acquires the third instruction.

For example, assuming that the at least one second instruction is two instructions (instruction 1 and instruction 2, and instruction 1 and instruction 2 constitute one task 1), instruction 1 may be the first instruction fetched by the processor after the processor fetches the third instruction, and instruction 2 may be the 2 nd instruction fetched by the processor after the processor fetches the third instruction.

S103, the processor decodes the at least one second instruction to obtain at least one micro-operation.

In the embodiment of the invention, the processor can obtain one micro-operation or at least two micro-operations after decoding one second instruction. The specific method can be determined according to actual use requirements, and the embodiment of the invention is not limited.

S104, the processor executes the at least one micro-operation.

In this embodiment of the present invention, for convenience of understanding the implementation manner of the embodiment of the present invention, the processor executes the above-mentioned S102 to S104 from the perspective of executing at least one second instruction from the processor, and in practical applications, the processor processes one second instruction every time the processor acquires one second instruction (i.e. the processor may decode the second instruction to obtain at least one micro-operation, and execute the at least one micro-operation). Illustratively, the above S102-S104 may be implemented by the processor executing at least one of the following S102a-S104 a.

S102, 102a, the processor obtains a second instruction.

In this embodiment of the present invention, the processor may obtain a second instruction from a memory of the device in which the processor is located.

S103a, the processor decodes the second instruction to obtain at least one micro-operation.

Typically, the second instruction may be decoded by a controller in a processor (e.g., controller 11 in the processor shown in FIG. 2 above) to obtain at least one micro-operation.

In this embodiment of the present invention, the processor may obtain at least one basic operation after decoding a second instruction, and each basic operation in the at least one basic operation may be referred to as a micro-operation, that is, the processor may obtain at least one micro-operation after decoding a second instruction.

S104, 104a, the processor executes the at least one micro-operation.

For example, assume that the processor has decoded the second instruction and then has obtained a micro-operation (e.g., micro-operation 1). The processor may perform micro-operation 1. If the micro-operation 1 is to obtain the data a at the address 1, the processor executes the micro-operation 1, that is, the processor obtains the data a at the address 1.

For example, assuming that the processor decodes the second instruction to obtain at least two micro-operations (for example, the number of the at least two micro-operations is three, and the three micro-operations are micro-operation 1, micro-operation 2, and micro-operation 3), the processor may execute micro-operation 1, micro-operation 2, and micro-operation 3. If micro-operation 1 is fetching data a at address 1, micro-operation 2 is fetching data b at address 2, and micro-operation 3 is adding a and b. The processor performs micro-operation 1, micro-operation 2 and micro-operation 3, i.e. the processor fetches data a at address 1 and the processor fetches data b at address 2, and the processor adds the fetched data a and data b.

Optionally, in this embodiment of the present invention, it is assumed that the number of the at least one micro-operation is at least two, and when the processor executes the at least two micro-operations, the processor may sequentially execute the at least two micro-operations according to a certain order. For example, assuming that at least two micro-operations are micro-operation 1, micro-operation 2, and micro-operation 3, respectively, as described above, the processor may execute micro-operation 1, micro-operation 2, and micro-operation 3 in sequence according to the order of micro-operation 1, micro-operation 2, and micro-operation 3 after decoding the second instruction. For example, if the processor decodes the second instruction and then obtains micro-operation 1, micro-operation 3, and micro-operation 2 in that order, the processor may execute micro-operation 1, micro-operation 3, and micro-operation 2 in that order.

In an embodiment of the invention, the process of the processor executing the steps S102a-S104a at least once is a process of the processor executing at least one second instruction for the first time. And after the processor executes the processes of the steps S102a-S104a at least once, at least one micro-operation obtained by decoding the at least one second instruction can be obtained.

S105, the processor saves the corresponding relation between the first sequence and the at least one micro-operation according to the third instruction.

In an embodiment of the present invention, the storing, by the processor, the corresponding relationship between the first sequence and the at least one micro-operation according to the third instruction may be understood as: the processor stores the corresponding relation between the first sequence and the at least one micro-operation by executing a third instruction.

For example, the processor may Store the correspondence between the first sequence and the at least one micro-operation through the interface function Store uop (Serial No, functional name) { }. For the description of the interface function, reference may be made to the description of the interface function in S101 above, and details are not described here again.

For example, the correspondence between the first sequence and the at least one micro-operation obtained after decoding the at least one second instruction may be stored in a cache of the processor or a memory of a device in which the processor is located.

For example, assuming that the first sequence is 0001 and at least one micro-operation obtained after decoding the at least one second instruction is micro-operation 1 and micro-operation 2, respectively, the correspondence between the first sequence and the at least one micro-operation may be stored in the manner shown in table 1.

TABLE 1

Sequence of	Micro-operations
		0001 (first sequence)	Micro-operation 1 and micro-operation 2

Optionally, in this embodiment of the present invention, when the number of the at least one micro-operation obtained after the processor decodes the at least one second instruction is at least two, the processor may further store an execution sequence of the at least two micro-operations. For example, the processor may maintain an order of execution in which the processor first executes the at least two micro-operations.

Further, the cache of the processor or the memory of the device in which the processor is located may also store the correspondence between the sets of sequences and the micro-operations. As shown in table 2, table 2 exemplifies correspondence (first correspondence, second correspondence, and third correspondence, respectively) between three sets of sequences and the micro-operation stored in a cache of the processor or a memory of the device in which the processor is located. Wherein, the first corresponding relationship is the corresponding relationship between the first sequence (assuming that the first sequence is 0001) and the micro-operation 1 and the micro-operation 2; the second correspondence is the correspondence between the second sequence (assuming that the second sequence is 0010) and the micro-operation 3; the third correspondence is the correspondence of the third sequence (let it be 0011) with the micro-operation 4, the micro-operation 5 and the micro-operation 6.

TABLE 2

Sequence of	Micro-operations
		0001 (first sequence)	Micro-operation 1 and micro-operation 2
0010 (second sequence)	Micro-operation 3
		0011 (third sequence)	Micro-operation 4, micro-operation 5, and micro-operation 6

Because data stored in a cache of the processor or a memory of the device in which the processor is located is lost when the processor or the device in which the processor is located is powered off, in the embodiment of the present invention, the first execution of the at least one second instruction by the processor means that the processor executes the at least one second instruction for the first time after the processor or the device in which the processor is located is powered on (started and operated) again each time. In the case where the processor executes the at least one second instruction for the first time, the processor may store a correspondence between the first sequence and at least one micro-operation obtained after decoding the at least one second instruction.

S106, the processor acquires a first instruction, wherein the first instruction comprises a first sequence.

The first instruction is used for instructing the processor to read at least one micro-operation corresponding to the first sequence. The at least one micro-operation is a result of the stored decode of the at least one second instruction.

In this embodiment of the present invention, for the description of the first sequence, reference may be specifically made to the description of the first sequence in S101, and details are not described here again.

Optionally, the first instruction may be input into the processor (or a device where the processor is located) by a user, or may be sent to the processor (or a device where the processor is located) by another device.

In this embodiment of the present invention, after the processor acquires the first instruction and recognizes that the first instruction includes the first sequence, the processor may execute the following step S107.

S107, the processor reads at least one micro-operation corresponding to the first sequence according to the first instruction.

In an embodiment of the present invention, the reading, by the processor according to the first instruction, at least one micro operation corresponding to the first sequence may be understood as: the processor reads at least one micro-operation corresponding to the first sequence by executing the first instruction.

In the embodiment of the present invention, since the processor already stores the correspondence between the first sequence and the at least one micro-operation before the processor acquires the first instruction for instructing the processor to read the at least one micro-operation corresponding to the first sequence, after the processor may acquire the first instruction for instructing the processor to read the at least one micro-operation corresponding to the first sequence, the processor may read the at least one micro-operation corresponding to the first sequence by executing the first instruction.

Optionally, in this embodiment of the present invention, the processor may store a correspondence between the first sequence and the at least one micro-operation in a cache of the processor or a memory of the device in which the processor is located, so that after the processor acquires the first instruction, the processor may read the at least one micro-operation corresponding to the first sequence in the first instruction from the cache of the processor or the memory of the device in which the processor is located. For example, the processor may read micro-operation 1 and micro-operation 2 from Table 1 above, corresponding to the first sequence (i.e., 0001).

S108, the processor executes the at least one micro-operation.

In the embodiment of the present invention, for the description of S108, reference may be specifically made to the description of S104a in the foregoing embodiment, and details are not described here again.

The method flow for processing instructions provided by the embodiment of the present invention is further described below by taking fig. 4 as an example. Fig. 4 is a schematic diagram of a method for processing an instruction (the direction of the arrow in fig. 4 indicates the execution sequence of the steps), and fig. 4 shows a process of the processor obtaining a first instruction, reading at least one micro-operation corresponding to a first sequence in the first instruction according to the first instruction, and executing the at least one micro-operation in the first instruction. The process may specifically include: firstly, a processor acquires a first instruction (the first instruction comprises a first sequence); the second processor identifies the first sequence (i.e., the processor identifies that the first instruction includes the first sequence); and thirdly, the processor reads at least one micro-operation corresponding to the first sequence in the memory of the processor or the cache of the device where the processor is located, and finally the processor executes the at least one micro-operation.

In the implementation of the present invention, when a processor executes tasks (a task is usually composed of at least one second instruction), after the processor acquires a first instruction (the first instruction includes a first sequence) for instructing the processor to read at least one micro-operation corresponding to the first sequence, the processor may read at least one micro-operation corresponding to the first sequence according to the first instruction; and because the at least one micro-operation is a stored micro-operation obtained after decoding the at least one second instruction, when the processor repeatedly executes a task consisting of the at least one second instruction, the processor does not need to repeatedly acquire the at least one second instruction and repeatedly decode the at least one second instruction, that is, the processor can directly execute the stored micro-operation obtained after decoding the at least one second instruction (that is, the processor can directly complete the execution of the at least one second instruction), thereby saving the time for the processor to execute the task and reducing the power consumption of the processor.

Optionally, in a possible implementation manner, the number of the at least one micro-operation read by the processor in S107 and corresponding to the first sequence may be at least two, the at least two micro-operations may include at least one first micro-operation and at least one second micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and a first operation address in one first micro-operation is an operation address of the first micro-operation when the processor executes the first micro-operation for the first time.

It should be noted that, in the embodiment of the present invention, the micro-operations may be divided into two types, one type is a first micro-operation for acquiring data or storing data, and the other type is a second micro-operation for operating on data. Since the first micro-operation is used to obtain data or store data, and the data is usually stored in a certain storage address in the storage medium, the storage address of the data is included in the first micro-operation, and the storage address of the data in the first micro-operation may be referred to as an operation address of the first micro-operation. However, since the second micro-operation is used for operating on data, and the operation is usually implemented by a register without involving a storage address, the second micro-operation may not include the storage address of the data, that is, the second micro-operation may have no operation address.

For example, assume that there are 3 micro-operations, micro-operation 1, micro-operation 2, and micro-operation 3, and micro-operation 1 fetches data a at address 1; the micro-operation 2 is to obtain data b at address 2; micro-operation 3 is to add a and b. Then micro-operation 1 and micro-operation 2 are both first micro-operations and micro-operation 3 is a second micro-operation. Wherein, the address 1 is a storage address of the data a, that is, an operation address of the micro-operation 1; address 2 is the storage address of data b, i.e., the operation address of micro-operation 2.

Generally, since different data have different storage addresses, when a processor first executes a first micro-operation to acquire or store one data, the storage address of the data may be different from the storage address of the data when the processor executes the first micro-operation again to acquire or store another data, that is, generally, an operation address of the first micro-operation (for example, a first operation address included in the first micro-operation) when the processor first executes the first micro-operation may be different from the operation address of the first micro-operation when the processor executes the first micro-operation again.

In the embodiment of the present invention, each saved first micro-operation includes the first operation address, so that in order to ensure that one first micro-operation can be correctly executed each time, except for the first execution of the one first micro-operation, before the rest of the first micro-operations are executed each time, the first operation address in the one first micro-operation may be modified.

Referring to fig. 3, as shown in fig. 5, S107 shown in fig. 3 may be replaced with S107a described below.

S107a, the processor reads at least one first micro-operation and at least one second micro-operation corresponding to the first sequence.

Optionally, in this embodiment of the present invention, the processor may read at least one first micro-operation and at least one second micro-operation corresponding to the first sequence from a cache of the processor or a memory of a device in which the processor is located.

Further, as shown in fig. 5, S108 shown in fig. 3 may be replaced with S108a and S108b described below.

S108a, the processor revises the first operation address in each first micro-operation in the at least one first micro-operation.

S108b, the processor executes each first micro-operation and at least one second micro-operation after the first operation address is corrected.

Optionally, in another possible implementation manner, the at least one micro-operation read by the processor in S107 and corresponding to the first sequence may be at least one first micro-operation, where each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the first micro-operation when the processor executes the first micro-operation for the first time.

For the description of the first micro-operation, reference may be made to the description of the first micro-operation in the foregoing one possible implementation manner, and details are not described herein again.

Referring to fig. 3, as shown in fig. 6, S107 shown in fig. 3 may be replaced with S107b described below.

S107b, the processor reads at least one first micro-operation corresponding to the first sequence.

Optionally, in this embodiment of the present invention, the processor may read the at least one first micro-operation from a cache of the processor or a memory of a device in which the processor is located.

Further, as shown in fig. 6, S108 shown in fig. 3 may be replaced with S108c and S108d described below.

S108c, the processor revises the first operation address in each first micro-operation in the at least one first micro-operation.

S108d, the processor executes each first micro-operation after the first operation address is corrected.

Optionally, in this embodiment of the present invention, the first instruction may further include an address offset. For a first micro-operation, the address offset is the offset of the second operation address relative to the first operation address in the first micro-operation. The second operation address is an operation address of the first micro-operation when the processor executes the first micro-operation currently.

For example, in the embodiment of the present invention, the above-mentioned S108a in fig. 5 or S108c in fig. 6 may be implemented by the processor executing the following method (1) on each first micro-operation.

(1) The processor corrects a first operation address in a first micro-operation to a second operation address according to the address offset.

The method shown in (1) above is described by taking one first micro-operation in each first micro-operation as an example, and for each first micro-operation, the processor may modify the first operation address according to the method shown in (1) above.

In the embodiment of the invention, since the operation address of the first micro-operation when the processor executes the first micro-operation for the first time is different from the operation address of the first micro-operation when the processor executes the first micro-operation again, and the first operation address in the first micro-operation is the first time the processor executes a first micro-operation, the operation address of the one first micro-operation, and therefore before the processor executes the one first micro-operation again, the address of the first operation in the one first micro-operation may be modified to the current address of the one first micro-operation based on the address offset in the first instruction it fetches, the operation address (i.e., the second operation address) of the one first micro-operation is used to ensure that the one first micro-operation can be executed correctly when the processor executes the one first micro-operation again.

In the embodiment of the present invention, the processor corrects the first operation address in the first micro operation to the second operation address according to the address offset, which may be specifically implemented by the processor increasing the address offset for the first operation address in the first micro operation. I.e. the second operation address is the sum of the first operation address and the address offset.

It should be noted that, in the embodiment of the present invention, since the address offset is the same for each first micro-operation, the processor may correct the first operation address in each first micro-operation by adding the address offset to the first operation address in each first micro-operation.

In an embodiment of the present invention, in a case where the number of the at least one micro-operation corresponding to the first sequence read by the processor is at least two, and the at least two micro-operations include at least one first micro-operation and at least one second micro-operation, or in a case where the at least one micro-operation corresponding to the first sequence read by the processor is at least one first micro-operation, the processor may add an address offset to the first micro-operation included in the at least one micro-operation before executing the at least one micro-operation. Illustratively, in conjunction with fig. 4, as shown in fig. 7 (the direction of the arrows in fig. 7 indicates the execution sequence of the steps), there is provided a schematic diagram of a method for processing instructions according to an embodiment of the present invention. Fig. 7 shows a specific process of the processor in the above embodiment to obtain the first instruction, read at least one micro-operation corresponding to the first sequence according to the first instruction, and execute the at least one micro-operation. The process may specifically include: first, a processor acquires a first instruction (comprising a first sequence); the second processor identifies the first sequence (i.e., the processor identifies that the first instruction includes the first sequence); thirdly, the processor reads at least one micro-operation corresponding to the first sequence from the memory of the processor or the cache of the device where the processor is located, and then increases the address offset for the first micro-operation included in the at least one micro-operation; the processor finally executes the at least one micro-operation (specifically, the processor executes each first micro-operation and at least one second micro-operation after the first operation address is corrected, or the processor executes each first micro-operation after the first operation address is corrected).

Optionally, the processor in the embodiment of the present invention may be a processor (e.g., a CPU) based on a control flow, and may also be a processor based on a data flow.

A control-flow-based processor may include a control unit (or called a control node) for fetching and decoding instructions and a processing unit for performing micro-operations, and the control unit and the processing unit are integrated in one chip. In the case that the processor in the embodiment of the present invention is a control flow-based processor, the process of the processor processing the instruction may be: the control unit in the processor obtains the instruction, decodes the instruction to obtain the micro-operation, then loads the micro-operation into the register file in the processor to form a micro-operation queue, and finally, the processing unit in the processor sequentially executes each micro-operation in the micro-operation queue.

The data stream based processor may include a control unit (or called a control node) for fetching and decoding an instruction, and at least two processing units for performing a micro-operation, the control unit being integrated in one chip, and the at least two processing units being integrated in another chip. In the case that the processor in the embodiment of the present invention is a data stream-based processor, the process of the processor processing the instruction may be: the control unit in the processor acquires the instruction, decodes the instruction to obtain the micro-operation, then distributes the micro-operation to at least two processing units in the processor, and finally each processing unit in the at least two processing units executes the micro-operation distributed by the control unit.

In an embodiment of the present invention, in a case that the processor is a data stream based processor (that is, the processor includes one control unit and at least two processing units), each of the at least two processing units in the processor may be controlled by the control unit through control information (for instructing each of the at least two processing units to execute at least one third micro-operation, where the at least one third micro-operation is a micro-operation in the at least one micro-operation) to execute one/some of the at least two micro-operations. For example, a method of a control unit in a processor controlling each of at least two processing units in the processor to execute one/some of the at least one micro-operation may include: for each of the processing units, the control unit performs the following steps (a) and (b) to control each of the processing units to perform one/some of the at least two micro-operations.

(a) And controlling one processing unit of the at least two processing units to acquire indication information by a control unit in the processor, wherein the indication information is used for indicating the one processing unit to execute at least one third micro-operation, and the at least one third micro-operation is a micro-operation in the at least one micro-operation.

(b) And controlling the processing unit to read the at least one third micro-operation corresponding to the first sequence in the first instruction and indicated by the indication information according to the indication information and the first instruction by the control unit.

Further, the processing unit is specifically configured to execute the at least one third micro-operation that the control unit controls the processing unit to read.

Wherein the indication information may be used to instruct the one processing unit to execute the micro-operation/micro-operations of the at least one micro-operation. Specifically, the indication information indicates which micro-operation/micro-operations of the at least one micro-operation the one processing unit can execute, and after the one processing unit executes the corresponding micro-operation, the one processing unit can send a result of executing the corresponding micro-operation to which processing unit/processing units. That is to say, when the processor provided in the embodiment of the present invention includes at least two processing units, for each processing unit, the control unit may perform the step (a) and the step (b), so as to control each processing unit to know which micro-operation/micro-operations it/they execute according to the indication information; and after each processing unit knows which micro-operation/micro-operations it executes, it can read the corresponding micro-operation, then execute the corresponding micro-operation, and send the result of executing the corresponding micro-operation to which processing unit/processing units.

Exemplarily, as shown in fig. 8, a flowchart for performing a micro-operation for a possible data-stream-based processor according to an embodiment of the present invention is shown (fig. 8 illustrates an example of including 8 processing units in the data-stream-based processor). When the processor executes at least one second instruction for the first time, the control unit in the processor decodes the at least one second instruction to obtain at least one micro-operation (the execution of 8 micro-operations is illustrated in fig. 8), and then the control unit may allocate one micro-operation that can be executed to each processing unit in the 8 processing units (as shown by a dotted arrow in fig. 8), so that the 8 processing units may execute the micro-operation allocated by the control unit, respectively. And the control unit may store, in the memory of the processor or the cache of the device in which the processor is located, a correspondence between the first sequence in the third instruction obtained by the control unit and the at least one micro-operation and indication information (where the indication information is used to indicate which micro-operation of the 8 micro-operations is executed by each processing unit of the 8 processing units, and is used to indicate to which processing unit, after the execution of the corresponding micro-operation, the result of the execution of the corresponding micro-operation is sent by each processing unit of the 8 processing units). Thus, when the processor needs to execute the at least one second instruction or the 8 micro-operations again, each processing unit in the processor may directly obtain the indication information corresponding to the processing unit from the memory of the processor or the cache of the device where the processor is located (as shown by the solid arrow in fig. 8), read at least one third micro-operation (the at least one third micro-operation is a micro-operation in the at least one micro-operation) corresponding to the first sequence and indicated by the indication information, and finally, each processing unit executes the at least one third micro-operation again.

In the embodiment of the present invention, the processor may store the indication information in a cache of the processor or a memory of a device in which the processor is located, so that when the processor repeatedly processes the same instruction, the control unit in the processor does not need to repeatedly allocate the micro-operation, which can be executed by each processing unit, to each processing unit of the at least two processing units. Therefore, the resources of the processor can be saved, and the efficiency of the processor for executing the instructions is improved.

The scheme provided by the embodiment of the invention is mainly from the perspective of the processor. It will be appreciated that the processor, in order to implement the above-described functions, comprises corresponding hardware structures and/or software elements for performing the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

The embodiment of the present invention may divide the work energy unit of the processor according to the method embodiment, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware or a form of a software functional module. It should be noted that the division of the unit in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

An exemplary structure of a processor provided in an embodiment of the present invention is shown in fig. 9, and in fig. 9, the processor may include a control unit 21 and a processing unit 22.

Among them, the control unit 21 may be configured to support the processor to execute S101, S102 (or S102a), S103 (or S103a), S105, S106, and S107 (which may include S107a or S107b) in the method embodiments.

The processing unit 22 is configured to support the processor to execute S104 (or S104a) or S108 (which may include S108a and S108b, or may include S108c and S108d) in the above method embodiment.

Optionally, the processor in the embodiment of the present invention may include at least two processing units. As shown in fig. 10, it is exemplified that the processor includes 3 processing units (in fig. 10, in order to distinguish the 3 processing units, the 3 processing units are respectively denoted as a processing unit 221, a processing unit 222, and a processing unit 223), and at least one micro operation is 3 micro operations. The control unit 21 may be specifically configured to control the processing unit 221, the processing unit 222, and the processing unit 223 to respectively execute one of the 3 micro-operations to execute the 3 micro-operations, so as to support the processor to execute the above S104 (or S104a) or S108 (which may include S108a and S108b, or may include S108c and S108 d).

Optionally, as shown in the processor shown in fig. 10, for the processing unit 221, the control unit 21 is further configured to control the processing unit 221 to obtain indication information 1 indicating that the processing unit 221 executes one micro operation (for example, micro operation 1) of 3 micro operations (for example, micro operation 1, micro operation 2, and micro operation 3, respectively), and control the processing unit 221 to read the micro operation 1 corresponding to the first sequence and indicated by the indication information 1 according to the indication information 1 and the first instruction, so that the processing unit 221 executes the micro operation 1. For the processing unit 222, the control unit 21 is further configured to control the processing unit 222 to obtain instruction information 2 instructing the processing unit 222 to execute one micro-operation (for example, micro-operation 2) of the 3 micro-operations, and control the processing unit 222 to read the micro-operation 2 corresponding to the first sequence and indicated by the instruction information 2 according to the instruction information 2 and the first instruction, so that the processing unit 222 executes the micro-operation 2. For the processing unit 223, the control unit 21 is further configured to control the processing unit 223 to obtain indication information 3 indicating that the processing unit 223 executes one micro operation (for example, micro operation 3) of the 3 micro operations, and control the processing unit 223 to read the micro operation 3 corresponding to the first sequence and indicated by the indication information 3 according to the indication information 3 and the first instruction, so that the processing unit 223 executes the micro operation 3.

It should be noted that the connection relationship among the 3 processing units (processing unit 221, processing unit 222, and processing unit 223) in fig. 10 is a possible connection manner. Yet another possible connection of 3 processing units (processing unit 221, processing unit 222 and processing unit 223) is shown in the processor shown in fig. 11. Of course, the 3 processing units may also be connected in other manners, which is not listed in the embodiment of the present invention. In practical applications, the specific connection manner between the processing units in the specific processor may be set according to actual requirements, and the embodiment of the present invention is not limited.

For example, assume that there are 3 micro-operations (micro-operation 1, micro-operation 2, and micro-operation 3, respectively), and the processing unit 221 executes micro-operation 1; the processing unit 222 executes micro-operation 2; the processing unit 223 executes the micro-operation 3. In the case where the processing unit 222 performs the micro-operation 2 according to the result of the micro-operation 1 performed by the processing unit 221, and the processing unit 223 performs the micro-operation 3 according to the result of the micro-operation 2 performed by the processing unit 222, the processing unit 221, the processing unit 222, and the processing unit 223 may be connected to each other by a connection as shown in fig. 10. In the case where the processing unit 223 executes the micro-operation 3 according to the result obtained by the processing unit 221 executing the micro-operation 1 and the result obtained by the processing unit 222 executing the micro-operation 2, the processing unit 221, the processing unit 222, and the processing unit 223 may be connected by a connection as shown in fig. 11.

The control unit 21 and the processing unit 22 (which may include the processing unit 221, the processing unit 222, and the processing unit 223) described above may also be used to perform other processes for the techniques described herein.

Illustratively, the functions of the control unit 21 may be specifically realized by the controller 11 in the processor shown in fig. 2, and the functions of the processing unit 22 (which may include the processing unit 221, the processing unit 222, and the processing unit 223) may be specifically realized by the arithmetic unit 12 in the processor shown in fig. 2.

In the embodiment of the present invention, the processor shown in fig. 9 may be the above-mentioned control-flow-based processor, and the processor shown in fig. 10 or 11 may be the above-mentioned data-flow-based processor.

The embodiment of the invention provides a device for processing an instruction, which can be a computer, a smart phone, a server or a base station and the like. The apparatus may comprise a processor as shown in any of figures 9 to 11. Optionally, the apparatus may further comprise a memory coupled to the processor, or the like.

Illustratively, the processor in the apparatus for processing instructions may be processor 01 in a server as shown in fig. 1. The memory in the apparatus for processing instructions may be the memory 02 in the server as shown in fig. 1.

Optionally, the apparatus for processing instructions may further include a bus, where the bus may include a data bus, a power bus, a control bus, a signal status bus, and the like. The processor and the memory in the device for processing instructions can be connected with each other through the bus and can complete communication with each other.

When a task (a task generally consists of a plurality of instructions) is executed, after a processor in the apparatus acquires a first instruction (the first instruction includes a first sequence) for instructing the processor to read at least one micro-operation corresponding to the first sequence, the processor may read at least one micro-operation corresponding to the first sequence according to the first instruction; and because the at least one micro-operation is a stored micro-operation obtained after decoding the at least one second instruction, when the processor repeatedly executes a task consisting of the at least one second instruction, the processor does not need to repeatedly acquire the at least one second instruction and repeatedly decode the at least one second instruction, that is, the processor can directly execute the stored micro-operation obtained after decoding the at least one second instruction (that is, the processor can directly complete the execution of the at least one second instruction), thereby saving the time for the processor to execute the task and reducing the power consumption of the processor.

The technical solutions provided in the embodiments of the present invention are essentially or partially contributed to by the prior art, or all or part of the technical solutions may be implemented by software programs, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the flow or functions according to embodiments of the invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy disk, magnetic tape), an optical medium (e.g., Digital Video Disk (DVD)), or a semiconductor medium (e.g., Solid State Drive (SSD)), among others.

Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, only the division of the functional modules is illustrated, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of processing instructions, comprising:

a processor acquires a first instruction, wherein the first instruction comprises a first sequence, and the first instruction is used for instructing the processor to read at least one micro-operation corresponding to the first sequence, and the at least one micro-operation is a saved result obtained after decoding at least one second instruction;

the processor reads the at least one micro-operation corresponding to the first sequence according to the first instruction;

the processor executing the at least one micro-operation;

the number of the at least one micro-operation is specifically at least two, the at least two micro-operations include at least one first micro-operation and at least one second micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the one first micro-operation when the processor executes the one first micro-operation for the first time;

the processor executes the at least one micro-operation, including:

the processor amends the first operation address in each first micro-operation;

the processor executes the each first micro-operation and the at least one second micro-operation after correcting the first operation address.

2. The method of claim 1, wherein the at least one micro-operation is at least one first micro-operation, each of the at least one first micro-operation includes a first operation address, and the first operation address of one first micro-operation is an operation address of the one first micro-operation when the processor first executes the one first micro-operation;

the processor executes the at least one micro-operation, including:

the processor amends the first operation address in each first micro-operation;

the processor executes the first micro-operations after the first operation address is corrected.

3. The method of claim 1 or 2, further comprising an address offset, wherein for the one first micro-operation, the address offset is an offset of a second operation address relative to a first operation address in the one first micro-operation, and wherein the second operation address is an operation address of the one first micro-operation when the processor is currently executing the one first micro-operation;

the processor modifying the first operation address in each first micro-operation, comprising:

for each of the first micro-operations, the processor performs the following steps to modify the first operation address in the each of the first micro-operations:

and the processor corrects the first operation address in the first micro-operation into the second operation address according to the address offset.

4. The method according to any of claims 1-2, wherein in case the processor executes the at least one second instruction for the first time, the method further comprises:

the processor acquires a third instruction, wherein the third instruction comprises the first sequence and is used for indicating the processor to save the corresponding relation between the first sequence and the at least one micro-operation;

and the processor saves the corresponding relation between the first sequence and the at least one micro-operation according to the third instruction.

5. The method of claim 3, wherein in a case where the processor executes the at least one second instruction for the first time, the method further comprises:

6. A processor, characterized in that the processor comprises a control unit and a processing unit;

the control unit is used for acquiring a first instruction, wherein the first instruction comprises a first sequence, and reading at least one micro-operation corresponding to the first sequence according to the first instruction; the first instruction is used for instructing the control unit to read the at least one micro-operation corresponding to the first sequence, wherein the at least one micro-operation is a saved result obtained after at least one second instruction is decoded;

the processing unit is used for executing the at least one micro-operation read by the control unit;

the number of the at least one micro-operation is specifically at least two, the at least two micro-operations include at least one first micro-operation and at least one second micro-operation, each first micro-operation in the at least one first micro-operation includes a first operation address, and the first operation address in one first micro-operation is an operation address of the one first micro-operation when the processing unit executes the one first micro-operation for the first time;

the processing unit is specifically configured to correct a first operation address in each first micro-operation, and execute each first micro-operation and the at least one second micro-operation after the first operation address is corrected.

7. The processor of claim 6, wherein the at least one micro-operation is at least one first micro-operation, each of the at least one first micro-operation includes a first operation address, and the first operation address of one first micro-operation is an operation address of the one first micro-operation when the processing unit first executes the one first micro-operation;

the processing unit is specifically configured to correct a first operation address in each first micro-operation, and execute each first micro-operation after the first operation address is corrected.

8. The processor of claim 6 or 7, further comprising an address offset, for the one first micro-operation, where the address offset is an offset of a second operation address relative to a first operation address in the one first micro-operation, and the second operation address is an operation address of the one first micro-operation when the processing unit is currently executing the one first micro-operation;

for each of the first micro-operations, the processing unit performs the following process to correct the first operation address in the each of the first micro-operations:

the processing unit is specifically configured to modify the first operation address in the one first micro-operation to the second operation address according to the address offset.

9. The processor according to any one of claims 6 to 7,

the control unit is further configured to, when the processing unit executes the at least one second instruction for the first time, obtain a third instruction, where the third instruction includes the first sequence, and store a correspondence between the first sequence and the at least one micro-operation according to the third instruction; wherein the third instruction is to instruct the control unit to save a correspondence between the first sequence and the at least one micro-operation.

10. The processor of claim 8,

11. The processor according to any one of claims 6 to 7 or 10, wherein the number of the processing units is at least two;

for each of at least two processing units, the control unit performs the following procedure to read at least one micro-operation corresponding to the first sequence according to the first instruction:

the control unit is further configured to control one processing unit of the at least two processing units to obtain indication information, where the indication information is used to indicate the one processing unit to execute at least one third micro-operation, and the at least one third micro-operation is a micro-operation in the at least one micro-operation;

the control unit is specifically configured to control the processing unit to read the at least one third micro-operation corresponding to the first sequence and indicated by the indication information according to the indication information and the first instruction;

the processing unit is specifically configured to execute the at least one third micro-operation that the control unit controls the processing unit to read.

12. An apparatus for processing instructions, comprising a processor according to any one of claims 6 to 11.

13. A computer readable storage medium comprising computer instructions which, when executed on a processor, cause the processor to perform a method of processing instructions as claimed in any of claims 1 to 5.