CN108509013A - A kind of method and device of process instruction - Google Patents

A kind of method and device of process instruction Download PDF

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Publication number
CN108509013A
CN108509013A CN201710114931.8A CN201710114931A CN108509013A CN 108509013 A CN108509013 A CN 108509013A CN 201710114931 A CN201710114931 A CN 201710114931A CN 108509013 A CN108509013 A CN 108509013A
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China
Prior art keywords
microoperation
processor
instruction
operation address
processing unit
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CN201710114931.8A
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CN108509013B (en
Inventor
黄罡
梁文亮
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/261—Microinstruction address formation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

The embodiment of the present invention provides a kind of method and device of process instruction, is related to field of computer technology, can save the time that processor executes task, reduce the power consumption of processor.This method includes：Processor obtains the first instruction, which includes First ray, which is used to indicate processor and reads at least one microoperation corresponding with the First ray；Processor reads at least one microoperation corresponding with the First ray according to first instruction, which is the result obtained later at least one second Instruction decoding preserved；Processor executes at least one microoperation.

Description

A kind of method and device of process instruction
Technical field
The present embodiments relate to field of computer technology more particularly to a kind of method and devices of process instruction.
Background technology
Processor is the arithmetic core and control core of equipment, when processor executes task, can usually complete fetching Enable, translate instruction (i.e. to Instruction decoding) and execute the work such as microoperation (microoperation is the result to being obtained after Instruction decoding).
Current processor is in the feelings for executing the task (task is usually made of at least one instruction) largely repeated Under condition, the identical instruction of acquisition that processor can repeat, and identical instruction is repeated to decode, and the acquisition phase that processor repeats Same instruction, and repeating decoding to identical instruction can cause the time of processor execution task longer, increase the work(of processor Consumption.
Invention content
The application provides a kind of method and device of process instruction, can save the time that processor executes task, reduces The power consumption of processor.
In order to achieve the above objectives, the application adopts the following technical scheme that：
In a first aspect, providing a kind of method of process instruction, this method includes：Processor acquisition is used to indicate the processor The first instruction (first instruction includes First ray) of at least one microoperation corresponding with First ray is read, and is located Device is managed according to first instruction, at least one microoperation corresponding with the First ray is read and processor executes this extremely A few microoperation.Wherein, which is the knot obtained later at least one second Instruction decoding preserved Fruit.
In the application, when processor executes task (task is usually made of at least one second instruction), due to The first instruction that processor reading at least one microoperation corresponding with First ray is used to indicate in processor acquisition (should First instruction includes First ray) after, which can read corresponding with the First ray according to first instruction At least one microoperation；And due at least one microoperation be preserved at least one second Instruction decoding after Obtained microoperation, therefore when the processor repeats being made of at least one second instruction for task, the processor It may not need repetition and obtain at least one second instruction, and repeat to decode without at least one second instruction, i.e., The processor can directly execute microoperation (the i.e. processor obtained later at least one second Instruction decoding preserved The execution of at least one second instruction can be done directly), so as to save the time that the processor executes task, reducing should The power consumption of processor.
In the first possible realization method of first aspect, the quantity of above-mentioned at least one microoperation is specially at least Two, at least two microoperations may include at least one first microoperation and at least one second microoperation, this is at least one The first microoperation of each of first microoperation includes the first operation address, the first operation address in first microoperation When executing first microoperation for the first time for processor, the operation address of first microoperation.Above-mentioned processor executes The method of at least one microoperation may include：Processor corrects the first operation address in each first microoperation, and locates First microoperation and at least one second microoperation each of after reason device execution the first operation address of amendment.
In second of possible realization method of first aspect, above-mentioned at least one microoperation is at least one first micro- Operation, the first microoperation of each of at least one first microoperation includes the first operation address, first microoperation In the first operation address be processor when executing first microoperation for the first time, first microoperation is operatively Location.The method that above-mentioned processor executes at least one microoperation may include：Processor is corrected in each first microoperation First operation address, and the first microoperation each of after processor execution the first operation address of amendment.
In the application, microoperation can be divided into two classes, and one kind is for obtaining data or storing first micro- behaviour of data Make, it is another kind of for for the second microoperation to data operation.Since the first microoperation is for obtaining data or storage data, And data are generally stored inside in some storage address in storage medium, therefore the first microoperation includes the storage of data Location, the storage address of data is properly termed as the operation address of first microoperation in the first microoperation.And due to the second microoperation For to data operation, and operation is usually realized by register, is not related to storage address, therefore can not in the second microoperation It can be without operation address in storage address namely the second microoperation including data.
It is different generally, due to the storage address of different data, thus processor execute for the first time first microoperation with Obtain or when one data of storage, the storage address of the data with processor execute first microoperation again to obtain or The storage address of the data may be different when storing another data, that is to say, that usual processor is executing one for the first time One first microoperation when one microoperation operation address (such as first microoperation include first operatively Location) operation address of one first microoperation when executing first microoperation again from processor may be different.This Shen Please in, due in the first microoperation of each of preservation include the first operation address, in order to ensure can correctly to hold every time One the first microoperation of row, other than executing first microoperation for the first time, remaining execute every time this it is first micro- Before operation, the first operation address in first microoperation can be first corrected.
Can also include address offset in above-mentioned first instruction in the third possible realization method of first aspect Amount, for the first microoperation of said one, which is that the second operation address (for processor work as by second operation address When one the first microoperation of preceding execution, the operation address of first microoperation) relative in first microoperation The offset of first operation address.Due to for each first microoperation, address above mentioned offset all same, therefore above-mentioned processing The method of the first operation address in each first microoperation of device amendment may include：For each first microoperation, processor Following processes (1) can be executed, to correct the first operation address in each first microoperation.Wherein, process (1) can be with For：Processor is modified to the second operation address according to the address offset amount, by the first operation address in first microoperation.
In the application, due to processor for the first time execute first microoperation when one first microoperation operatively The operation address of first microoperation is different when location executes first microoperation from processor again, and said one When the first operation address in one microoperation is that the processor executes first microoperation for the first time, first microoperation Operation address, therefore before processor executes first microoperation again, it can be according to the ground in the instruction of its acquisition The first operation address in one first microoperation is modified to when currently executing first microoperation by location offset, The operation address (i.e. the second operation address) of one first microoperation, with ensure processor execute again this it is first micro- When operation, first microoperation can be correctly executed.
In the 4th kind of possible realization method of first aspect, above-mentioned at least one second is executed for the first time in processor and is referred to In the case of order, the method for process instruction provided by the present application can also include：Processor acquisition is used to indicate processor preservation The third instruction (third instruction includes First ray) of correspondence between First ray and at least one microoperation, and And processor is instructed according to the third, preserves above-mentioned First ray and above-mentioned at least one microoperation (i.e. to above-mentioned at least one The result obtained after second Instruction decoding) between correspondence.
Second aspect provides a kind of processor, which includes control unit and processing unit.The control unit is used for It obtains and is used to indicate control unit and reads and the first of corresponding with First ray at least one microoperation instruct that (instruction includes First ray), and according to first instruction, read at least one microoperation corresponding with the First ray.Processing unit is used In at least one microoperation for executing control unit reading.Wherein, which is to preserve at least one The result obtained after second Instruction decoding.
In the first possible realization method of second aspect, the quantity of above-mentioned at least one microoperation is specially extremely Two few, at least two microoperations may include at least one first microoperation and at least one second microoperation, this at least one The first microoperation of each of a first microoperation includes the first operation address, and first in first microoperation is operatively When unit executes first microoperation for the first time in order to control for location, the operation address of first microoperation.Above-mentioned processing list Member is specifically used for correcting the first operation address in each first microoperation, and executes every after correcting the first operation address A first microoperation and at least one second microoperation.
In second of possible realization method of second aspect, above-mentioned at least one microoperation is at least one first Microoperation, the first microoperation of each of at least one first microoperation include the first operation address, a first micro- behaviour When the first operation address in work is that processing unit executes first microoperation for the first time, the operation of first microoperation Address.Above-mentioned processing unit is specifically used for correcting the first operation address in each first microoperation, and executes and correct first First microoperation each of after operation address.
Can also include address offset in above-mentioned first instruction in the third possible realization method of second aspect Amount, for first microoperation, which is that (unit is current in order to control for second operation address for the second operation address When executing first microoperation, the operation address of first microoperation) relative to the in first microoperation The offset of one operation address.Due to for each first microoperation, the address offset amount all same, therefore for each first Microoperation, the processing unit are specifically used for executing following processes (2), with correct in each first microoperation first operatively Location.Wherein, process (2) is：Processing unit repaiies the first operation address in first microoperation according to the address offset amount Just it is being the second operation address.
In the 4th kind of possible realization method of second aspect, above-mentioned control unit is additionally operable to hold for the first time in processing unit In the case of at least one second instruction of row, acquisition is used to indicate the control unit and preserves First ray and at least one microoperation Between correspondence third instruction (third instruction include First ray), and according to third instruction, preserve this Correspondence between one sequence and at least one microoperation.
In the 5th kind of possible realization method of second aspect, the quantity of above-mentioned processing unit is at least two.For Each processing unit at least two processing units, above-mentioned control unit are performed both by following processes (3), to refer to according to first It enables, reads at least one microoperation corresponding with First ray：
The processing unit acquisition that above-mentioned control unit is additionally operable at least two processing units of control is used to indicate this One processing unit executes the instruction information of at least one third microoperation, which is above-mentioned at least one Microoperation in a microoperation；The control unit is specifically used for controlling a processing unit according to the instruction information and the first finger It enables, reads at least one third microoperation of the and instruction information corresponding with First ray instruction；One processing unit At least one third microoperation of processing unit reading is controlled specifically for executing the control unit.
The description of the technique effect of second aspect or its any one possible realization method specifically may refer to The associated description of the technique effect to first aspect or its any one possible realization method is stated, details are not described herein again.
The third aspect, provides a kind of device of process instruction, the device include above-mentioned second aspect or its any one can Processor described in the realization method of energy.
Fourth aspect provides a kind of computer readable storage medium, which includes computer Instruction, when the computer instruction is run on a processor so that the processor executes above-mentioned first aspect or its any one The method of process instruction in possible realization method.
5th aspect, provides a kind of computer program product including computer instruction, when the computer program product exists When being run on processor so that the processor executes the processing in above-mentioned first aspect or its any one possible realization method The method of instruction.
It is above-mentioned right that the description of the technique effect of the above-mentioned third aspect, fourth aspect and the 5th aspect specifically may refer to The associated description of the technique effect of first aspect or its any one possible realization method, details are not described herein again.
Description of the drawings
Fig. 1 is the hardware architecture diagram of server provided in an embodiment of the present invention；
Fig. 2 is the hardware architecture diagram of processor provided in an embodiment of the present invention；
Fig. 3 is a kind of method schematic diagram one of process instruction provided in an embodiment of the present invention；
Fig. 4 is a kind of method schematic diagram two of process instruction provided in an embodiment of the present invention；
Fig. 5 is a kind of method schematic diagram three of process instruction provided in an embodiment of the present invention；
Fig. 6 is a kind of method schematic diagram four of process instruction provided in an embodiment of the present invention；
Fig. 7 is a kind of method schematic diagram five of process instruction provided in an embodiment of the present invention；
Fig. 8 is the flow diagram that a kind of processor based on data flow provided in an embodiment of the present invention executes microoperation；
Fig. 9 is a kind of structural schematic diagram one of processor provided in an embodiment of the present invention；
Figure 10 is a kind of structural schematic diagram two of processor provided in an embodiment of the present invention；
Figure 11 is a kind of structural schematic diagram three of processor provided in an embodiment of the present invention.
Specific implementation mode
In embodiments of the present invention, " illustrative " or " such as " etc. words for indicate make example, illustration or explanation.This Be described as in inventive embodiments " illustrative " or " such as " any embodiment or design scheme be not necessarily to be construed as comparing Other embodiments or design scheme more preferably or more advantage.Specifically, use " illustrative " or " such as " etc. words purport Related notion is being presented in specific ways.
Term " first ", " second " and " third " in the embodiment of the present invention etc. be for distinguishing different objects, without It is the particular order for description object.For example, the first instruction, the second instruction and third instruction etc. are for distinguishing different fingers It enables, rather than the particular order for describing instruction.
In the description of the present invention, unless otherwise indicated, the meaning of " plurality " is refer to two or more.For example, more A processing unit refers to two or more processing units.
In general, in the case that processor executes largely repeating for task, the identical instruction of acquisition that processor can repeat, and It repeats to decode to the identical instruction of acquisition that identical instruction repeats to decode, and repeat, and to identical instruction, can cause to handle The time that device executes task (task is usually made of at least one instruction) is longer, increases the power consumption of processor.
To solve the above-mentioned problems, the embodiment of the present invention provides a kind of method and device of process instruction, can save place The time that device executes task is managed, the power consumption of processor is reduced.Specifically, the method for process instruction provided in an embodiment of the present invention and Device will be described in detail in the following embodiments.
The method of process instruction provided in an embodiment of the present invention can be applied in the device of process instruction, the process instruction Device can be the equipment for including processor.The equipment can be terminal device or the network equipment, such as computer, intelligence Mobile phone, server or base station etc..The equipment can also be other kinds of terminal device or the network equipment, the embodiment of the present invention It is not specifically limited.
The method of process instruction provided in an embodiment of the present invention can be applied to processor and execute a large amount of iterative tasks (often A task by least one of at least one instruction, such as the embodiment of the present invention second instruct form) scene.It is exemplary , in the communication system (hereinafter referred to as 5G communication systems) using the 5th third-generation mobile communication technology, each equipment/network element (such as server etc.) may need to execute largely repeating for task in communication process.Therefore in 5G communication systems, these Equipment/network element can use at the method for process instruction provided in an embodiment of the present invention when executing the task that these are repeated Manage each instruction in the task.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is done retouches in detail It states.
Illustratively, illustrate so that the device of process instruction provided in an embodiment of the present invention is server as an example, it below will knot Close each component parts that Fig. 1 specifically introduces server.As shown in Figure 1, the server includes processor 01 and memory 02.It can With understanding, the structure of server shown in Fig. 1 does not constitute the restriction to server, may include such as Fig. 1 institutes The more or fewer components of component shown, or the certain components that can be combined in component as shown in Figure 1 (such as can will be located Reason device 01 and memory 02 are integrated together), or can be different from component as shown in Figure 1 arrangement.
Wherein, above-mentioned processor 01 can be central processing unit (central processing unit, CPU), can be with For other general processors, digital signal processor (digital signal processing, DSP), application-specific integrated circuit (application specific integrated circuit, ASIC), field programmable gate array (field- Programmable gate array, FPGA) either other programmable logic device, discrete gate or transistor logic, Discrete hardware components etc..Wherein, general processor can be microprocessor or any conventional processor.
Above-mentioned memory 02 can store one or more instructions.When the device of the process instruction handles an instruction, The instruction can be obtained from memory 02 by processor 01, and handle the instruction.The memory can be volatile memory, Such as random access memory；The memory can also include nonvolatile memory, such as read-only memory, flash Device, hard disk or solid state disk etc.；The memory can also include the combination of the memory of mentioned kind.
Illustratively, each component parts of processor is specifically introduced below in conjunction with Fig. 2.As shown in Fig. 2, processor can To include：Controller 11, arithmetic unit 12 and register 13.It is understood that the structure of processor shown in Figure 2 not structure The restriction of pairs of processor, may include the more or fewer components of component such as shown in Fig. 2, or can combine such as figure Certain components in component shown in 2, or can be different from component as shown in Figure 2 arrangement.
Wherein, controller 11 can be used for acquisition instruction, and to the Instruction decoding of acquisition, to obtain microoperation.Alternatively, control Device 11 processed is additionally operable to send to arithmetic unit 12 micro- to being obtained after Instruction decoding for controlling the execution controller 11 of arithmetic unit 12 The control signal of operation.
Illustratively, in the embodiment of the present invention, controller may include to the microoperation obtained after Instruction decoding：For Obtain microoperation (such as being properly termed as read operation), the microoperation (such as being properly termed as write operation) for storing data of data And the microoperation (such as being properly termed as arithmetic operation) etc. for data to be carried out with operation.It specifically can be according to actual conditions It determines, the embodiment of the present invention is not construed as limiting.
Arithmetic unit 12 can be used for executing microoperation of the controller 11 to being obtained after Instruction decoding.
Register 13 may include general register, special register or control register etc..General register again may be used It is divided to fixed-point number register and floating number register two classes, they are used for preserving the register operand and operating result in instruction. Wherein, general register is the important component of processor, and general register will be accessed in most of instructions.Special deposit Device is to execute the register needed for some special operations.Control register is commonly used to instruction processor process instruction State.Control register may include that privileged mode register, condition code register, processing abnormal accident register and error detection are posted Storage etc..
The executive agent of the method for process instruction provided in an embodiment of the present invention can be processor, or processor In function module.Below by taking the executive agent of the method for process instruction is processor as an example, to provided in an embodiment of the present invention The method of process instruction is as exemplary.
As shown in figure 3, the embodiment of the present invention provides a kind of method of process instruction, this method includes following S101-S108.
S101, processor obtain third instruction, and third instruction includes First ray.
Wherein, third instruction can serve to indicate that processor preserves pair between First ray and at least one microoperation It should be related to, which is the result to being obtained after at least one second Instruction decoding.This at least one second The pending task of instruction composition processor.
In general, the task that processor executes is made of the instruction being stored in the memory that the processor is able to access that , wherein the memory that the processor is able to access that can be the memory integrated in the processor, or the processor Memory (such as hard disk in the equipment) in a device.It, can be with for example, when equipment executes task where the processor The task is executed by the processor.Specifically, the processor can obtain the finger for forming the task from the memory of the equipment It enables, and handles the instruction, to execute the task.
Illustratively, it is assumed that when equipment executes the task for the sum for calculating data a and data b where processor, Ke Yiyou The processor executes the task.It is used to indicate calculating number specifically, can be obtained from the memory of the equipment by the processor According to the instruction of the sum of a and data b, then the processor can handle the instruction, to execute the task.
In the embodiment of the present invention, the task that processor executes can be made of at least one second instruction, and processor can be with Executing the task being made of at least one second instruction for the first time (i.e. processor executes at least one second instruction for the first time) In the case of, acquisition be used to indicate processor preserve First ray and to obtain after at least one second Instruction decoding to The third instruction of correspondence between a few microoperation, i.e. processor execute above-mentioned S101.In this way, being held for the first time in processor In the case that row is by least one second instruction the forming of the task, processor can preserve the First ray and to this at least one Correspondence between at least one microoperation obtained after a second Instruction decoding.Wherein, processor executes at least for the first time The detailed process of one second instruction will describe in detail in following S102-S104.
Optionally, in the embodiment of the present invention, processor can preserve above-mentioned First ray and right by predefined interface Correspondence between at least one microoperation obtained after above-mentioned at least one second Instruction decoding.Illustratively, this is pre- The interface of definition can be a predefined interface function, which can be expressed as：
Store uop (Serial No, Function name) { }；
Wherein, Store uop indicate to preserve microoperation (specifically, Store indicates to preserve, uop indicates microoperation). Serial No indicate sequence number (such as can be First ray provided in an embodiment of the present invention).Function name indicate work( It can module name；The function module name can be instruction (such as can be it is provided in an embodiment of the present invention second instruct) in some/ The function name of certain functions；The function name is indicated in above-mentioned interface function after the function decoding that preservation indicates the function name Obtained all microoperations.The code segment of the microoperation preserved for needs in { }.
In conjunction with the above-mentioned description to interface function provided in an embodiment of the present invention, which specifically indicates：It preserves The correspondence of Serial No and all microoperations that the function decoding of Function name instructions is obtained later.It can manage It solves, in the embodiment of the present invention, if preserving First ray and to being obtained at least after above-mentioned at least one second Instruction decoding One microoperation, then the Serial No in above-mentioned interface function can be First ray, Function name may include The function name of all functions at least one second instruction, be in { } to obtain after at least one second Instruction decoding to The code segment of a few microoperation.
Optionally, above-mentioned third instruction can be user's input processor (or equipment where processor), or Other equipment is sent to processor (or equipment where processor).
In the embodiment of the present invention, above-mentioned First ray can be predefined a string of binary numbers, such as above-mentioned first sequence Row can be expressed as 0001.
S102, processor obtain at least one second instruction.
In the embodiment of the present invention, it is above-mentioned it is at least one second instruction can be processor get third instruction after, At least one instruction for the composition pending task of processor that processor is got.
Illustratively, it is assumed that above-mentioned at least one second instruction (respectively instructs 1 and instruction 2, and instruct for two instructions 1 and instruction 2 composition one task 1), then instruction 1 can be processor get third instruction after, processor is got First instruction, instruction 2 can be processor after getting third instruction, get the 2nd instruction of processor.
S103, processor obtain at least one microoperation at least one second Instruction decoding.
In the embodiment of the present invention, a microoperation can be obtained after second Instruction decoding of processor pair, it can also Obtain at least two microoperations.It can specifically be determined according to actual use demand, the embodiment of the present invention is not construed as limiting.
S104, processor execute at least one microoperation.
In the embodiment of the present invention, realization method to facilitate understanding of the present embodiment of the invention, processor executes above-mentioned S102- S104 is to execute the angle of at least one second instruction from processor to describe, and in practical applications, processor often obtains one A second instruction, just (i.e. processor can obtain at least one micro- behaviour to one second instruction of processing to second Instruction decoding Make, and execute at least one microoperation).Illustratively, under above-mentioned S102-S104 can be executed at least once by processor State S102a-S104a realizations.
S102a, processor obtain one second instruction.
In the embodiment of the present invention, processor can obtain one second instruction from the memory of equipment where processor.
S103a, processor obtain at least one microoperation to second Instruction decoding.
In general, can be by the second Instruction decoding of controller pair in processor (such as in above-mentioned processor shown in Fig. 2 Controller 11), to obtain at least one microoperation.
In the embodiment of the present invention, at least one basic operation can be obtained after second Instruction decoding of processor pair, Each basic operation at least one basic operation is properly termed as a microoperation, i.e. one second instruction of processor pair At least one microoperation can be obtained after decoding.
S104a, processor execute at least one microoperation.
Illustratively, it is assumed that processor is (for example, micro- to having obtained a microoperation after second Instruction decoding Operation is 1).So processor can execute microoperation 1.Wherein, it if microoperation 1 is to obtain data a in address 1, handles It is that processor obtains data a in address 1 that device, which executes microoperation 1,.
Illustratively, it is assumed that processor after second Instruction decoding to having obtained at least two microoperations (with this For the quantity of at least two microoperations is three, and three microoperations are respectively microoperation 1, microoperation 2 and microoperation 3), that Processor can execute microoperation 1, microoperation 2 and microoperation 3.Wherein, if microoperation 1 is to obtain data a in address 1, Microoperation 2 is to obtain data b in address 2, and microoperation 3 is to be added a with b.So processor executes microoperation 1,2 and of microoperation Microoperation 3, as processor obtain data a in address 1, and processor obtains data b and processor in address 2 and will obtain The data a arrived is added with data b.
Optionally, in the embodiment of the present invention, it is assumed that the quantity of above-mentioned at least one microoperation is at least two, in processor In the case of executing at least two microoperations, processor can execute at least two microoperation successively in a certain order. Illustratively, it is assumed that at least two microoperations are respectively above-mentioned microoperation 1, microoperation 2 and microoperation 3, then processor can To execute microoperation 1, micro- successively according to the sequence for obtaining microoperation 1, microoperation 2 and microoperation 3 after the second Instruction decoding Operation 2 and microoperation 3.For example, microoperation 1, microoperation 3 and micro- have been obtained after the second Instruction decoding of processor pair successively Operation 2, then processor can execute microoperation 1, microoperation 3 and microoperation 2 successively.
In the embodiment of the present invention, the process that above-mentioned processor executes above-mentioned steps S102a-S104a at least once is to locate Reason device executes the process of at least one second instruction for the first time.And above-mentioned steps S102a- is executed at least once in processor At least one microoperation to being obtained after above-mentioned at least one second Instruction decoding can be got after the process of S104a.
S105, processor are instructed according to third, preserve the correspondence of the First ray and at least one microoperation.
In the embodiment of the present invention, above-mentioned processor is instructed according to third, preserves the First ray and at least one micro- behaviour The correspondence of work can be understood as：Processor is at least one micro- with this to preserve the First ray by executing third instruction The correspondence of operation.
Illustratively, processor can pass through interface function Store uop (the Serial No, Function of foregoing description Name) { } preserves the correspondence between First ray and at least one microoperation.It can be with for the description of the interface function Referring to, to the associated description of the interface function, details are not described herein again in above-mentioned S101.
Illustratively, above-mentioned First ray and at least one micro- to obtaining after above-mentioned at least one second Instruction decoding In the memory of equipment where correspondence between operation can be stored in the caching or processor of processor.
Illustratively, it is assumed that above-mentioned First ray is 0001, and to being obtained after above-mentioned at least one second Instruction decoding At least one microoperation be respectively microoperation 1 and microoperation 2, then the First ray and between at least one microoperation Correspondence can preserve in the manner as shown in table 1.
Table 1
Sequence Microoperation
0001 (First ray) Microoperation 1 and microoperation 2
Optionally, in the embodiment of the present invention, when processor to obtained after at least one second Instruction decoding at least one In the case that the quantity of a microoperation is at least two, what processor can also preserve at least two microoperations executes sequence.Example As executed sequence when processor can preserve, and processor is executed at least two microoperation for the first time.
Further, can also be preserved in the memory of equipment where the caching of processor or processor multigroup sequence with it is micro- The correspondence of operation.As shown in table 2, table 2 in the memory of equipment where the caching of processor or processor to preserve three It is said for group sequence and the correspondence of microoperation (being respectively the first correspondence, the second correspondence and third correspondence) Bright.Wherein, to be First ray (assuming that First ray be 0001) corresponding with microoperation 1 and microoperation 2 for the first correspondence Relationship；Second correspondence is the correspondence of the second sequence (assuming that the second sequence is 0010) and microoperation 3；Third, which corresponds to, closes System is correspondence of the third sequence (assuming that third sequence is 0011) with microoperation 4, microoperation 5 and microoperation 6.
Table 2
Sequence Microoperation
0001 (First ray) Microoperation 1 and microoperation 2
0010 (the second sequence) Microoperation 3
0011 (third sequence) Microoperation 4, microoperation 5 and microoperation 6
Due to processor either equipment in the caching of processor or where processor when device powers down where processor The data preserved in memory can lose, therefore in the embodiment of the present invention, and processor executes at least one second instruction for the first time is Refer to after equipment where processor or processor re-powers and (starts and run) every time, processor executes at least one for the first time Second instruction.In the case where processor executes at least one second instruction for the first time, processor can preserve First ray and right Correspondence between at least one microoperation obtained after at least one second Instruction decoding.
S106, processor obtain the first instruction, which includes First ray.
Wherein, which is used to indicate processor and reads at least one microoperation corresponding with First ray.This is extremely A few microoperation is to preserve to the result after above-mentioned at least one second Instruction decoding.
In the embodiment of the present invention, the description for First ray is specifically referred in above-mentioned S101 to First ray Description, details are not described herein again.
Optionally, above-mentioned first instruction can be user's input processor (or equipment where processor), or Other equipment is sent to processor (or equipment where processor).
In the embodiment of the present invention, processor obtain first instruct and identify that the first instruction includes First ray after, Processor can execute following S107.
S107, processor read at least one microoperation corresponding with the First ray according to first instruction.
In the embodiment of the present invention, above-mentioned processor is read corresponding with First ray at least one according to first instruction Microoperation can be understood as：Processor is by executing first instruction, to read at least one micro- behaviour corresponding with First ray Make.
It is corresponding with First ray at least due to being used to indicate processor reading in processor acquisition in the embodiment of the present invention Before first instruction of one microoperation, processor has saved the correspondence between First ray and at least one microoperation Relationship, therefore can be used to indicate processor reading at least one microoperation corresponding with First ray obtaining in processor After first instruction, processor can read that corresponding with the First ray this is at least one micro- by executing first instruction Operation.
Optionally, in the embodiment of the present invention, processor can will be between the First ray and at least one microoperation In the memory of equipment where correspondence is stored in the caching or processor of processor, such processor is getting the first finger After order, processor can be from reading in the memory of equipment where the caching or processor of processor and being somebody's turn to do in the first instruction The corresponding at least one microoperation of First ray.Such as processor can be read and First ray (i.e. 0001) from above-mentioned table 1 Corresponding microoperation 1 and microoperation 2.
S108, processor execute at least one microoperation.
In the embodiment of the present invention, the correlation being specifically referred in above-described embodiment to S104a for the description of S108 is retouched It states, details are not described herein again.
The method flow of the process instruction of embodiment offer is be provided by taking Fig. 4 as an example below.As shown in Figure 4 For a kind of method schematic diagram of process instruction (what the direction of arrow indicated each step in Fig. 4 executes sequence), shown in Fig. 4 Processor obtains the first instruction in above-described embodiment, and according to first instruction, reads and the First ray pair in the first instruction At least one microoperation for answering and the process for executing at least one microoperation.The process can specifically include：It handles first Device obtains the first instruction (the first instruction includes First ray)；Its second processor identifies that (i.e. processor identifies First ray First instruction includes First ray)；Again, it is read in the caching of equipment where memory or processor of the processor in processor At least one microoperation corresponding with the First ray, last processor is taken to execute at least one microoperation.
During the present invention is implemented, when processor executes task (task is usually made of at least one second instruction), Due to obtaining the first finger for being used to indicate the processor and reading at least one microoperation corresponding with First ray in the processor After enabling (first instruction includes First ray), which can read and the First ray according to first instruction Corresponding at least one microoperation；And due at least one microoperation be preserved to this it is at least one second instruction translate The microoperation obtained after code, therefore when the processor repeats being made of at least one second instruction for task, it should Processor may not need repetition and obtain at least one second instruction, and repeat to translate without at least one second instruction Code, the i.e. processor can directly execute the microoperation obtained later at least one second Instruction decoding preserved and (i.e. should Processor can be done directly the execution of at least one second instruction), so as to save the time that the processor executes task, Reduce the power consumption of the processor.
Optionally, in a kind of possible realization method, in above-mentioned S107 processor read it is corresponding with First ray extremely The quantity of a few microoperation can be at least two, and at least two microoperations may include at least one first microoperation and extremely Few second microoperation, the first microoperation of each of at least one first microoperation include the first operation address, and one When the first operation address in a first microoperation is that the processor executes first microoperation for the first time, this first micro- The operation address of operation.
It should be noted that in the embodiment of the present invention, microoperation can be divided into two classes, one kind for for obtain data or The first microoperation of data is stored, it is another kind of for for the second microoperation to data operation.Since the first microoperation is for obtaining Access evidence or storage data, and data are generally stored inside in some storage address in storage medium, therefore the first microoperation Include the storage address of data, the storage address of data is properly termed as first microoperation operatively in the first microoperation Location.And since the second microoperation is used for data operation, and operation is usually realized by register, is not related to storage address, because It can be without operation address in storage address that can not be including data in this second microoperation namely the second microoperation.
As an example it is assumed that there is 3 microoperations, respectively microoperation 1, microoperation 2 and microoperation 3, and microoperation 1 be Address 1 obtains data a；Microoperation 2 is to obtain data b in address 2；Microoperation 3 is to be added a with b.So microoperation 1 and micro- Operation 2 is the first microoperation, and microoperation 3 is the second microoperation.Wherein, address 1 is the storage address of data a namely micro- behaviour Make 1 operation address；Address 2 is the storage address of data b namely the operation address of microoperation 2.
It is different generally, due to the storage address of different data, thus processor execute for the first time first microoperation with Obtain or when one data of storage, the storage address of the data with processor execute first microoperation again to obtain or The storage address of the data may be different when storing another data, that is to say, that usual processor is executing one for the first time One first microoperation when one microoperation operation address (for example, first microoperation include first operatively Location) operation address of first microoperation when executing first microoperation again from processor may be different.
In the embodiment of the present invention, due to including the first operation address in the first microoperation of each of preservation, in order to Guarantee can correctly execute first microoperation every time, every at remaining other than executing first microoperation for the first time Before secondary execution one first microoperation, the first operation address in first microoperation can be first corrected.
In conjunction with Fig. 3, as shown in figure 5, above-mentioned S107 shown in Fig. 3 could alternatively be following S107a.
S107a, processor read corresponding with the First ray at least one first microoperation and at least one second micro- Operation.
Optionally, in the embodiment of the present invention, equipment that processor can be where the caching or processor from processor At least one first microoperation corresponding with First ray and at least one second microoperation are read in memory.
Further, as shown in figure 5, above-mentioned S108 shown in Fig. 3 could alternatively be following S108a and S108b.
S108a, processor correct the first operation address in each first microoperation at least one first microoperation.
First microoperation and at least one second micro- behaviour each of after S108b, processor execution the first operation address of amendment Make.
Optionally, in alternatively possible realization method, processor is read corresponding with First ray in above-mentioned S107 At least one microoperation can be at least one first microoperation, the first microoperation of each of at least one first microoperation Include the first operation address, the first operation address in first microoperation is that the processor executes this one first for the first time When microoperation, the operation address of first microoperation.
The description of first microoperation specifically may refer in a kind of above-mentioned possible realization method to the first microoperation Associated description, details are not described herein again.
In conjunction with Fig. 3, as shown in fig. 6, above-mentioned S107 shown in Fig. 3 could alternatively be following S107b.
S107b, processor read at least one first microoperation corresponding with the First ray.
Optionally, in the embodiment of the present invention, equipment that processor can be where the caching or processor from processor At least one first microoperation is read in memory.
Further, as shown in fig. 6, above-mentioned S108 shown in Fig. 3 could alternatively be following S108c and S108d.
S108c, processor correct the first operation address in each first microoperation at least one first microoperation.
First microoperation each of after S108d, processor execution the first operation address of amendment.
Optionally, can also include address offset amount in above-mentioned first instruction in the embodiment of the present invention.For one first Microoperation, the address offset amount are offset of second operation address relative to the first operation address in first microoperation Amount.Wherein, when which is that processor currently executes first microoperation, the behaviour of first microoperation Make address.
Illustratively, in the embodiment of the present invention, the S108c in S108a or Fig. 6 in above-mentioned Fig. 5 can pass through processor Method shown in following (1) is executed to each first microoperation to realize.
(1) the first operation address in first microoperation is modified to second by processor according to the address offset amount Operation address.
Wherein, method shown in above-mentioned (1) is illustrated by taking first microoperation in each first microoperation as an example, For each first microoperation, processor can correct its first operation address according to method shown in above-mentioned (1).
In the embodiment of the present invention, due to processor one first microoperation when executing first microoperation for the first time Operation address when executing first microoperation again from processor the operation address of first microoperation it is different, and on When to state the first operation address in first microoperation be that the processor executes first microoperation for the first time, this one first The operation address of microoperation, therefore before processor executes first microoperation again, can be according to the of its acquisition The first operation address in one first microoperation is modified to and currently executes this by the address offset amount in one instruction When one microoperation, the operation address (i.e. the second operation address) of first microoperation, to ensure to execute again in processor When one first microoperation, first microoperation can be correctly executed.
In the embodiment of the present invention, processor is according to the address offset amount, operatively by first in first microoperation Location is modified to the second operation address and can specifically be increased for the first operation address in first microoperation by processor The address offset amount is realized.That is the second operation address be the first operation address and the address offset amount and.
It should be noted that in the embodiment of the present invention, since for each first microoperation, the address offset amount is homogeneous Together, therefore, processor can be corrected often by increasing the address offset amount for the first operation address in each first microoperation The first operation address in a first microoperation.
In the embodiment of the present invention, it is in the micro- quantity of at least one microoperation corresponding with First ray that processor is read At least two, and in the case that at least two microoperations include at least one first microoperation and at least one second microoperation, Or in the case where at least one microoperation corresponding with First ray that processor is read is at least one first microoperation, Processor can be before executing at least one microoperation, and the first microoperation for including at least one microoperation increases Address offset amount.Illustratively, in conjunction with Fig. 4, as shown in Figure 7 (each step of direction expression of arrow executes sequence in Fig. 7), For a kind of schematic diagram of the method for process instruction provided in an embodiment of the present invention.Processor in above-described embodiment is shown in Fig. 7 The first instruction is obtained, and according to first instruction, reads at least one microoperation corresponding with First ray and executes this extremely The detailed process of a few microoperation.The process can specifically include：Processor obtains first instruction (including the first sequence first Row)；Its second processor identifies First ray (i.e. processor identifies that the first instruction includes First ray)；Again, processor At least one microoperation corresponding with First ray is read in the caching of equipment where memory or processor in processor, so It is that the first microoperation that at least one microoperation includes increases address offset amount afterwards；It is at least one micro- that last processor executes this Operation (particularly the first microoperation and at least one second micro- behaviour each of after the first operation address of finger processor execution amendment First microoperation each of after work or processor execution the first operation address of amendment).
Optionally, the processor in the embodiment of the present invention can be the processor (such as CPU) based on control stream, can also For the processor based on data flow.
It in processor based on control stream may include one and be used for acquisition instruction, and to the control unit of Instruction decoding (or node in order to control) and processing unit for executing microoperation, the control unit and the processing unit are integrated in In one chip.In the case that processor in embodiments of the present invention is the processor based on control stream, processor processing The process of instruction can be：Control unit acquisition instruction in the processor, and to obtaining microoperation after Instruction decoding, then These microoperations are loaded into formation microoperation queue in the register file in processor again, finally again by the processor Processing unit executes each microoperation in the microoperation queue successively.
It in processor based on data flow may include one and be used for acquisition instruction, and to the control unit of Instruction decoding (or node in order to control) and at least two processing unit for executing microoperation, the control unit are integrated in a chip In, which is integrated in another chip.Processor in embodiments of the present invention is based on data flow Processor in the case of, the process of the processor process instruction can be：Control unit acquisition instruction in the processor, and To obtaining microoperation after Instruction decoding, then these microoperations are distributed to at least two processing lists in the processor again Member finally executes microoperation of the control unit for its distribution by each processing unit at least two processing unit again.
It is that (i.e. the processor includes that a control is single to the processor based on data flow in processor in the embodiment of the present invention Member and at least two processing units) in the case of, can by the control unit in processor by control information (be used to indicate to Each processing unit in few two processing units executes at least one third microoperation, and at least one third microoperation is above-mentioned Microoperation at least one microoperation) each processing unit for controlling at least two processing units in the processor executes One/some microoperations at least two microoperation.Illustratively, the control unit in processor controls in the processor At least two processing units in each processing unit execute the sides of one/some microoperations at least one microoperation Method may include：For each processing unit, control unit is performed both by following step (a) and step (b), to control each place Reason unit executes one/some microoperations at least two microoperation.
(a) processing unit at least two processing units is controlled by the control unit in processor and obtains instruction letter Breath, the instruction information are used to indicate a processing unit and execute at least one third microoperation, at least one micro- behaviour of third As the microoperation in above-mentioned at least one microoperation.
(b) by the control unit control a processing unit according to the instruction information and it is above-mentioned first instruction, read with At least one third microoperation of First ray correspondence and instruction information instruction in first instruction.
Further, a processing unit controls processing unit reading specifically for executing the control unit At least one third microoperation.
Wherein, which can serve to indicate that a processing unit executes one at least one microoperation A/some microoperations.Specifically, at least one microoperation can be executed by indicating a processing unit in the instruction information Which of/after which microoperation and processing unit execute corresponding microoperation, which can will Execute corresponding microoperation result be sent to which/which processing unit.That is, in processing provided in an embodiment of the present invention When device includes at least two processing unit, for each processing unit, the control unit can execute above-mentioned steps (a) and Step (b), with control each processing unit can be known according to the instruction information its execute which/which microoperation；And Each processing unit know its execute which/which microoperation after, corresponding microoperation can be read, then executed again corresponding micro- Operation, and by the result for executing corresponding microoperation be sent to which/which processing unit.
Illustratively, as shown in figure 8, being that a kind of possible processor based on data flow provided in an embodiment of the present invention is held The flow diagram of row microoperation (Fig. 8 is illustrated so that the processor based on data flow includes 8 processing units as an example).Its In, when processor executes at least one second instruction for the first time, the control unit in processor is at least one second instruction At least one microoperation (illustrating for executing 8 microoperations in Fig. 8) is obtained after decoding, then the control unit can Its microoperation (the dotted line arrow in such as Fig. 8 that can execute is distributed respectively with each processing unit into 8 processing units Shown in head) so that 8 processing units can execute the microoperation of control unit distribution respectively.And the control unit can The correspondence and instruction information (its of First ray and at least one microoperation in being instructed with the third obtained In, which is used to indicate each processing unit in 8 processing units and executes the micro- behaviour of which of 8 microoperations Make, and each processing unit being used to indicate in 8 processing units is executed corresponding after performing corresponding microoperation Which processing unit is the result of microoperation be sent to) it is maintained in the memory of processor or the caching of processor place equipment In.It is every in the processor so when processor needs to execute at least one second instruction or 8 microoperations again A processing unit can directly obtain the corresponding processing from the caching of equipment where the memory of the processor or the processor The instruction information (as shown in solid arrow in Fig. 8) of unit, and read and the instruction information corresponding with First ray instruction extremely A few third microoperation (at least one third microoperation is the microoperation in above-mentioned at least one microoperation) is last each Processing unit executes at least one third microoperation again.
In the embodiment of the present invention, processor can by above-mentioned instruction information storage processor caching or processor institute In the memory of equipment, so when processor reprocesses identical instruction, the control unit in processor is without being repeated as Each processing unit at least two processing unit distributes its microoperation that can be executed.So as to save processor Resource improves the efficiency that processor executes instruction.
It is above-mentioned that mainly scheme provided in an embodiment of the present invention is introduced from the angle of processor.It can be understood that place Device is managed in order to realize above-mentioned function, it comprises execute the corresponding hardware configuration of each function and/or software unit.This field skill Art personnel should be readily appreciated that, unit and algorithm steps described in conjunction with the examples disclosed in the embodiments of the present disclosure, The embodiment of the present invention can be realized with the combining form of hardware or hardware and computer software.Some function actually with hardware also It is that computer software drives the mode of hardware to execute, depends on the specific application and design constraint of technical solution.Profession Technical staff can use different methods to achieve the described function each specific application, but this realization is not answered Think the range beyond the embodiment of the present invention.
The embodiment of the present invention can make processor according to above method embodiment the division of functional unit, for example, can be with Corresponding each function divides each functional unit, and two or more functions can also be integrated in a processing unit In.The form that hardware had both may be used in above-mentioned integrated unit is realized, can also be realized in the form of software function module.It needs It is noted that be schematical, only a kind of division of logic function to the division of unit in the embodiment of the present invention, it is practical real It is current that there may be another division manner.
Illustratively, a kind of structure of processor provided in an embodiment of the present invention is as shown in figure 9, in fig.9, the processor May include control unit 21 and processing unit 22.
Wherein, above-mentioned control unit 21 can be used for S101, the S102 for supporting that processor executes in above method embodiment (either S102a), S103 (or S103a), S105, S106 and S107 (may include S107a or S107b).
Above-mentioned processing unit 22 be used for support processor execute above method embodiment in S104 (or S104a) or S108 (may include S108a and S108b, or may include S108c and S108d).
Optionally, processor may include at least two processing units in the embodiment of the present invention.As shown in Figure 10, at this It includes that 3 processing units (in Fig. 10, in order to distinguish 3 processing units, which are indicated respectively to manage device For processing unit 221, processing unit 222 and processing unit 223), and at least one microoperation is to illustrate for 3 microoperations. Above-mentioned control unit 21 specifically can be used for holding respectively by control process unit 221, processing unit 222 and processing unit 223 A microoperation in 3 microoperations of row, to execute 3 microoperations, to support processor execute above-mentioned S104 (or ) or S108 (may include S108a and S108b, or may include S108c and S108d) S104a.
Optionally, in processor as shown in Figure 10, for processing unit 221, above-mentioned control unit 21 is additionally operable to control 3 microoperations of the acquisition instruction execution of processing unit 221 of processing unit 221 (such as be respectively microoperation 1, microoperation 2 and microoperation 3) the instruction information 1 of a microoperation (such as microoperation 1) in, and control process unit 221 is according to the instruction information 1 and One instruction, reads the microoperation 1 of the and instruction information 1 corresponding with First ray instruction, and to the execution of processing unit 221, this is micro- Operation 1.For processing unit 222, above-mentioned control unit 21 is additionally operable to control process unit 222 and obtains instruction processing unit 222 The instruction information 2 of a microoperation (such as microoperation 2) in 3 microoperations is executed, and control process unit 222 refers to according to this Show that information 2 and first instructs, read the microoperation 2 of the and instruction information 2 corresponding with First ray instruction, to processing unit 222 execute the microoperation 2.For processing unit 223, above-mentioned control unit 21 is additionally operable to the acquisition of control process unit 223 Indicate that processing unit 223 executes the instruction information 3 of a microoperation (such as microoperation 3) in 3 microoperations, and control process Unit 223 is instructed according to the instruction information 3 and first, reads the microoperation of the and instruction information 3 corresponding with First ray instruction 3, to which processing unit 223 executes the microoperation 3.
It should be noted that 3 processing units (processing unit 221, processing unit 222 and processing unit 223) in Figure 10 Between connection relation be a kind of possible connection type.(the processing of 3 processing units is also shown in processor shown in Figure 11 Unit 221, processing unit 222 and processing unit 223) alternatively possible connection type.Certainly, 3 processing units it Between can also connect by other means, will not enumerate in the embodiment of the present invention.In practical applications, specific processor In each processing unit between specific connection type can be arranged according to actual demand, the embodiment of the present invention is not construed as limiting.
Illustratively, it is assumed that have 3 microoperations (being respectively microoperation 1, microoperation 2 and microoperation 3), and above-mentioned processing list Member 221 executes microoperation 1；Processing unit 222 executes microoperation 2；Processing unit 223 executes microoperation 3.In processing unit 222 1 obtained result of microoperation is executed according to processing unit 221 and executes microoperation 2, and processing unit 223 is according to processing unit In the case that 222 execute the execution microoperation 3 of 2 obtained result of microoperation, processing unit 221, processing unit 222 and processing are single It can be connected by connection type as shown in Figure 10 between member 223.It is executed according to processing unit 221 in processing unit 223 micro- In the case of operating 1 obtained result and execution 2 obtained result of the microoperation execution microoperation 3 of processing unit 222, processing Unit 221, processing unit 222 and processing unit 223 can be connected by connection type as shown in figure 11.
Above-mentioned control unit 21 and processing unit 22 (may include processing unit 221, processing unit 222 and processing unit 223) it can be also used for executing other processes of techniques described herein.
Illustratively, the function of above-mentioned control unit 21 can specifically pass through the controller 11 in processor shown in Fig. 2 It realizes, the function of above-mentioned processing unit 22 (may include processing unit 221, processing unit 222 and processing unit 223) specifically may be used To be realized by the arithmetic unit 12 in processor shown in Fig. 2.
In the embodiment of the present invention, processor as shown in Figure 9 can be the above-mentioned processor based on control stream, such as Figure 10 or Processor shown in 11 can be the above-mentioned processor based on data flow.
The embodiment of the present invention provides a kind of device of process instruction, the device of the process instruction be specifically as follows computer, Smart mobile phone, server or base station etc..The device may include the processor as shown in Fig. 9 to 11 any one.Optionally, should The memory etc. that device can also include and the processor is of coupled connections.
Illustratively, the processor in the device of the process instruction can be the processor in server as shown in Figure 1 01.Memory in the device of the process instruction can be the memory 02 in server as shown in Figure 1.
Optionally, it in the device of the process instruction can also include bus, which may include that data/address bus, power supply are total Line, controlling bus and signal condition bus etc..It can be by this between processor and memory in the device of the process instruction Bus is connected with each other and completes mutual communication.
(task is usually by multiple instruction group in the task of execution for the device of process instruction provided in an embodiment of the present invention At) when, the processor acquisition in the device is used to indicate the processor and reads at least one microoperation corresponding with First ray The first instruction (this first instruction include First ray) after, which can read and be somebody's turn to do according to first instruction The corresponding at least one microoperation of First ray；And due at least one microoperation be preserved to this at least one The microoperation obtained after two Instruction decodings, therefore repeat in the processor and appointed by what at least one second instruction formed When business, which may not need repetition and obtains at least one second instruction, and without at least one second finger It enables and repeats to decode, i.e., the processor can directly execute the micro- behaviour obtained later at least one second Instruction decoding preserved Make (i.e. the processor can be done directly the execution of at least one second instruction), task is executed so as to save the processor Time, reduce the power consumption of the processor.
Technical solution provided in an embodiment of the present invention substantially the part that contributes to existing technology in other words, or should The all or part of technical solution can be realized by software program, hardware, firmware or its arbitrary combination.When using software When program is realized, can entirely or partly it realize in the form of a computer program product.The computer program product includes one A or multiple computer instructions.When loading and execute on computers the computer instruction, entirely or partly generate according to this Flow in inventive embodiments or function.The computer can be all-purpose computer, special purpose computer, computer network or its His programmable device.The computer instruction can store in a computer-readable storage medium, or computer-readable from one Storage medium is transmitted to another computer readable storage medium, for example, the computer instruction can be from a web-site, meter Calculation machine, server or data center pass through wired (such as coaxial cable, optical fiber, Digital Subscriber Line (digital subscriber Line, DSL)) mode or wireless (such as infrared, wireless, microwave etc.) mode be to another web-site, computer, server Or data center's transmission.The computer readable storage medium can be that any usable medium that computer can access either is wrapped Include the data storage devices such as one or more usable mediums integrated server, data center.The usable medium can be magnetic Medium (for example, floppy disk, disk, tape), optical medium (for example, digital video disk (digital video disc, DVD)), Or semiconductor medium (such as solid state disk (solid state drives, SSD)) etc..
Through the above description of the embodiments, it is apparent to those skilled in the art that, for description It is convenienct and succinct, it, can be as needed and by above-mentioned work(only with the division of above-mentioned each function module for example, in practical application It can distribute and be completed by different function modules, i.e., the internal structure of device is divided into different function modules, more than completion The all or part of function of description.The specific work process of the system, apparatus, and unit of foregoing description can refer to aforementioned side Corresponding process in method embodiment, details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the module or The division of unit, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units Or component can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute Display or the mutual coupling, direct-coupling or communication connection discussed can be by some interfaces, device or unit INDIRECT COUPLING or communication connection can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme 's.
In addition, each functional unit in each embodiment of the application can be integrated in a processing unit, it can also It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.Above-mentioned integrated list The form that hardware had both may be used in member is realized, can also be realized in the form of SFU software functional unit.
The above, the only specific implementation mode of the application, but the protection domain of the application is not limited thereto, it is any Change or replacement in the technical scope that the application discloses, should all cover within the protection domain of the application.Therefore, this Shen Protection domain please should be based on the protection scope of the described claims.

Claims (13)

1. a kind of method of process instruction, which is characterized in that including：
Processor obtains the first instruction, and first instruction includes First ray, and first instruction is used to indicate the place It manages device and reads at least one microoperation corresponding with the First ray, at least one microoperation is to preserve at least one The result obtained after a second Instruction decoding；
The processor is instructed according to described first, reads at least one microoperation corresponding with the First ray；
The processor executes at least one microoperation.
2. according to the method described in claim 1, it is characterized in that, the quantity of at least one microoperation is specially at least two A, at least two microoperations include at least one first microoperation and at least one second microoperation, and described at least one first The first microoperation of each of microoperation includes the first operation address, and the first operation address in first microoperation is institute When stating processor and executing one first microoperation for the first time, the operation address of one first microoperation；
The processor executes at least one microoperation, including：
The processor corrects the first operation address in each first microoperation；
The processor executes each first microoperation after correcting the first operation address and described at least one second micro- Operation.
3. according to the method described in claim 1, it is characterized in that, at least one microoperation is at least one first micro- behaviour Make, the first microoperation of each of described at least one first microoperation includes the first operation address, first microoperation In the first operation address be the processor when executing one first microoperation for the first time, one first microoperation Operation address；
The processor executes at least one microoperation, including：
The processor corrects the first operation address in each first microoperation；
The processor executes each first microoperation after correcting the first operation address.
4. according to the method in claim 2 or 3, which is characterized in that further include address offset amount in first instruction, it is right In one first microoperation, described address offset is the second operation address relative in one first microoperation The offset of first operation address, second operation address are that the processor currently executes one first microoperation When, the operation address of one first microoperation；
The processor corrects the first operation address in each first microoperation, including：
For each first microoperation, the processor is performed both by following step, to correct each first microoperation In the first operation address：
The processor is modified to institute according to described address offset, by the first operation address in one first microoperation State the second operation address.
5. according to the method described in any of claim 1 to 4, which is characterized in that described in being executed for the first time in the processor extremely In the case of few one second instruction, the method further includes：
The processor obtains third instruction, and the third instruction includes the First ray, and the third instruction is for referring to Show that the processor preserves the correspondence between the First ray and at least one microoperation；
The processor is instructed according to the third, preserves the correspondence between the First ray and at least one microoperation Relationship.
6. a kind of processor, which is characterized in that the processor includes control unit and processing unit；
Described control unit, for obtaining the first instruction, first instruction includes First ray, and is referred to according to described first It enables, reads at least one microoperation corresponding with the First ray；Wherein, it is single to be used to indicate the control for first instruction Member reads at least one microoperation corresponding with the First ray, and at least one microoperation is to preserve at least The result obtained after one the second Instruction decoding；
The processing unit, at least one microoperation for executing described control unit reading.
7. processor according to claim 6, which is characterized in that the quantity of at least one microoperation is specially at least Two, at least two microoperations include at least one first microoperation and at least one second microoperation, and described at least one The first microoperation of each of one microoperation includes the first operation address, and the first operation address in first microoperation is When the processing unit executes one first microoperation for the first time, the operation address of one first microoperation；
The processing unit is specifically used for correcting the first operation address in each first microoperation, and executes amendment Each first microoperation after first operation address and at least one second microoperation.
8. processor according to claim 6, which is characterized in that at least one microoperation is at least one first micro- Operation, the first microoperation of each of described at least one first microoperation includes the first operation address, a first micro- behaviour When the first operation address in work is that the processing unit executes one first microoperation for the first time, one first micro- behaviour The operation address of work；
The processing unit is specifically used for correcting the first operation address in each first microoperation, and executes amendment Each first microoperation after first operation address.
9. processor according to claim 7 or 8, which is characterized in that further include address offset amount in first instruction, For one first microoperation, described address offset is the second operation address relative in one first microoperation The first operation address offset, second operation address be the processing unit currently execute one first micro- behaviour When making, the operation address of one first microoperation；
For each first microoperation, the processing unit is performed both by following processes, to correct each first micro- behaviour The first operation address in work：
The processing unit is specifically used for according to described address offset, by the first operation in one first microoperation Address correction is second operation address.
10. according to the processor described in claim 6-9 any one, which is characterized in that
Described control unit is additionally operable to, in the case where the processing unit executes at least one second instruction for the first time, obtain Third is taken to instruct, the third instruction includes the First ray, and is instructed according to the third, and the First ray is preserved Correspondence between at least one microoperation；Wherein, the third instruction is used to indicate described control unit preservation Correspondence between the First ray and at least one microoperation.
11. according to the processor described in claim 6-10 any one, which is characterized in that the quantity of the processing unit is extremely It is two few；
For each processing unit at least two processing units, described control unit is performed both by following processes, with according to institute The first instruction is stated, at least one microoperation corresponding with the First ray is read：
Described control unit, a processing unit being additionally operable at least two processing units of control obtains instruction information, described Instruction information is used to indicate one processing unit and executes at least one third microoperation, at least one third microoperation For the microoperation at least one microoperation；
Described control unit is specifically used for the one processing unit of control and is instructed according to the instruction information and described first, Read at least one third microoperation of corresponding with the First ray and described instruction information instruction；
One processing unit, specifically for execute that described control unit controls that one processing unit reads it is described extremely A few third microoperation.
12. a kind of device of process instruction, which is characterized in that include the processor as described in claim 6 to 11 any one.
13. a kind of computer readable storage medium, which is characterized in that including computer instruction, when the computer instruction is being located When being run on reason device so that the method that the processor executes the process instruction as described in claim 1 to 5 any one.
CN201710114931.8A 2017-02-28 2017-02-28 Method and device for processing instruction Expired - Fee Related CN108509013B (en)

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