CN108493259A - A kind of junction barrier schottky diode and manufacturing method - Google Patents
A kind of junction barrier schottky diode and manufacturing method Download PDFInfo
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- CN108493259A CN108493259A CN201810556262.4A CN201810556262A CN108493259A CN 108493259 A CN108493259 A CN 108493259A CN 201810556262 A CN201810556262 A CN 201810556262A CN 108493259 A CN108493259 A CN 108493259A
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- 238000000034 method Methods 0.000 claims abstract description 23
- 238000005520 cutting process Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000001259 photo etching Methods 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000003466 welding Methods 0.000 claims description 8
- 239000002253 acid Substances 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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Abstract
A kind of junction barrier schottky diode and manufacturing method, belong to technical field of semiconductors.Junction barrier schottky chip includes substrate（5）And epitaxial layer（6）, in epitaxial layer（6）Surface be provided with knot in active area（3）And pressure ring（1）, in epitaxial layer（6）Surface formed anode metal layer（4）, in substrate（5）Bottom surface formed cathode metal layer（7）, it is characterised in that：Chip cutting position（10）In the pressure ring（1）Middle part, from chip cutting position（10）Cutting forms cut surface（8）, in cut surface（8）And there is passivation layer in lower edges area（14）Covering.In this junction barrier schottky diode and manufacturing method, one kind is provided to be cut in the middle part of pressure ring, eliminate pressure ring crooked radian position in the prior art, improve the pressure-resistant performance of chip, the manufacture for realizing chip only with one of photoetching simultaneously, makes complex process degree and production cost substantially reduce.
Description
Technical field
A kind of junction barrier schottky diode and manufacturing method, belong to technical field of semiconductors.
Background technology
In recent years due to Schottky-barrier diode（Schottky Barrier Diode, abbreviation SBD）Low conducting pressure
Drop and extremely short reverse recovery time cause people to the raising of circuit system efficiency and pay much attention to and be widely used.SBD has three
A feature is more prominent：（1）Because schottky barrier height is less than PN junction barrier height, the cut-in voltage and conduction voltage drop of SBD
It is smaller than PIN diode, power attenuation in circuit can be reduced to reduced levels；（2）The junction capacity of SBD is relatively low, its work
Working frequency is up to 100GHz；（3）SBD is the injection there is no minority carrier, therefore switching speed is faster, itself Reverse recovery
Time is the charge and discharge time of Schottky barrier capacitance.
Traditional Schottky diode equally exists following defect：（1）When due to reverse blocking capability close to 200V, Xiao Te
The forward voltage drop VF of base rectifier is by close to the forward voltage drop of PIN rectifiers, therefore traditional Schottky-barrier diode is anti-
It is generally below 200V to blocking voltage, the efficiency being allowed in the application is lower.（2）Its reversed leakage current of traditional Schottky diode
Larger and temperature sensitive, traditional Schottky diode junction temperature is between 125 DEG C to 175 DEG C.
Based on drawbacks described above, junction barrier schottky diode（Junction Barrier Schottky, abbreviation JBS）Make
Become the hot spot of research for a kind of enhanced Schottky diode, the typical feature of junction barrier schottky diode structure is to pass
Multiple PN junctions are integrated on the epitaxial layer of the Schottky diode of system, and pectination is presented.Junction barrier schottky diode is in zero bias and positively biased
When Schottky contacts it is partially ON, PN junction part is not turned on；Junction barrier schottky diode PN junction depletion region when reverse-biased broadens
So that pinch-off current channel, effectively inhibits Schottky barrier to reduce effect and effectively control reversed leakage current.So junction barrier Xiao Te
The outstanding advantages of based diode are the on-state and high-speed switch characteristic for possessing Schottky-barrier diode, also PIN diode
OFF state and low current leakage characteristic.
In the prior art, the structure of junction barrier schottky diode is as shown in figure 9, include substrate 5, in the top of substrate 5
For epitaxial layer 6, it is arranged at intervals with knot 3 in several active areas on the surface of epitaxial layer 6, the outside of knot 3 is pressure resistance in active area
Ring 1.It is additionally provided with insulating layer 15 in 6 top surface edge of epitaxial layer, anode metal layer 4 is covered in 6 surface of epitaxial layer and positioned at exhausted
The inside of edge layer 15.There are following defects on product and technique for the junction barrier schottky diode of the prior art：（1）
The bottom of pressure ring 1 is formed with arcwall face, and the bigger potential lines of crooked radian are closeer, and electric field strength is bigger, this affects chip
Pressure-resistant performance.（2）Third photo etching technique is at least needed in prior art：First time is on the surface of epitaxial layer 6 to oxide layer
Photoetching is carried out, then the techniques such as ion implanted form knot 3 and pressure ring 1 in multiple active areas；Second of photoetching process is pair
15 photoetching of insulating layer is allowed to form contact hole, to be further formed schottky interface 2；Third time photoetching is to anode metal layer
4 carry out photoetching, are allowed to positioned at the inside of insulating layer 15, therefore production technology is complex in the prior art, and need wider
One or more pressure rings improve chip pressure resistance performance.
Invention content
The technical problem to be solved by the present invention is to：One kind is overcome the deficiencies of the prior art and provide to carry out in the middle part of pressure ring
Cutting, eliminates pressure ring crooked radian position in the prior art, improves the pressure-resistant performance of chip, while only with one of light
Carve the manufacture for realizing chip, the junction barrier schottky diode for making complex process degree and production cost substantially reduce and manufacture
Method.
The technical solution adopted by the present invention to solve the technical problems is：The junction barrier schottky diode, including knot gesture
The cathode and anode built Schottky chip and drawn respectively by lead from chip, junction barrier schottky chip includes substrate
And the epitaxial layer above substrate, it is provided on the surface of epitaxial layer and ties and be located in active area knot outer ring in several active areas
Pressure ring, the semiconductor type and epitaxial layer of knot and pressure ring on the surface of epitaxial layer on the contrary, be formed with and lead in active area
The anode metal layer of connection forms the cathode metal layer being connect with lead in the bottom surface of substrate, it is characterised in that：Chip cutting position
It sets at the middle part of the pressure ring, cuts to form cut surface from chip cutting position, have in cut surface and lower edges area blunt
Change layer covering.
Preferably, become P+ type semiconductor in the active area.
Preferably, the pressure ring is P+ type semiconductor.
Preferably, draw respectively by the way that soldering-tin layer welding is described on the surface of the anode metal layer and cathode metal layer
Line.
Preferably, the soldering-tin layer is located at the inside of passivation layer.
A kind of manufacturing method of junction barrier schottky diode, which is characterized in that include the following steps：
Step a, the surface of epitaxial layer carry out oxidation processes, form oxide layer, then in active area knot and pressure ring position
It sets and photoetching is carried out to oxide layer, expose the surface of epitaxial layer；
The upper surface injection boron ion of step b, the epitaxial layer after photoetching are simultaneously diffused, and are formed simultaneously in active area knot and resistance to
Pressure ring；
Step c removes the oxide layer of epitaxial layer upper surface；
Step d forms schottky interface in epitaxial layer upper surface；
Step e is respectively formed anode metal layer and cathode metal layer in the bottom surface on the surface of epitaxial layer and substrate, obtains knot gesture
Schottky wafer is built, then junction barrier schottky wafer is cut by chip cutting position, junction barrier Xiao detached
Special base chip；
Step f draws anode, in cathode metal layer in the anode metal layer surface of junction barrier schottky chip by welding lead
Surface cathode is drawn by welding lead；
Step g carries out acid wash passivation process to junction barrier schottky chip, and passivation layer is formed in cut surface and lower edges.
Compared with prior art, advantageous effect possessed by the present invention is：
In this junction barrier schottky diode and manufacturing method, one kind is provided and is cut in the middle part of pressure ring, eliminated existing
There is pressure ring crooked radian position in technology, improves the pressure-resistant performance of chip, while chip is realized only with one of photoetching
Manufacture, makes complex process degree and production cost substantially reduce.
In this junction barrier schottky wafer, chip cutting position is at the middle part of the pressure ring, in each pressure resistance
Cut surface is cut longitudinally to form in the middle part of ring, cutting forms the junction barrier schottky chip of several separation after completing, each
In a junction barrier schottky chip, including knot and the half positioned at outside pressure ring in several active areas at middle part, i.e., it is same
A pressure ring is located at after dicing in two adjacent junction barrier schottky chips.
Since chip cutting position is located at the middle part of pressure ring, eliminate what pressure ring bottom bend in the prior art was formed
Arcwall face reduces its electric field strength, improves the pressure-resistant performance of chip.The spacing tied in the active area of chip is pressed into according to resistance to
Row adjustment, the pinch off of PN junction depletion region broadening realization current channel, effectively inhibits Schottky barrier to reduce effect when reverse-biased.
The processes such as the welded, acid wash passivation of junction barrier schottky chip after cutting separation, in cut surface and upper following
Edge area forms a floor passivation layer, and soldering-tin layer is located at the inside of passivation layer, forms passivation layer by the outlet in chip so that electricity
Stream can not circulate from the side of chip, instead of the effect of insulating layer in the prior art, therefore eliminate progress in the prior art
Second and third road lithography step only utilize one of photoetching due in the production technology of this junction barrier schottky chip
Technique substantially reduces compared at least needing three photoetching processes in the prior art on complex process degree and production cost.
Description of the drawings
Fig. 1 is junction barrier schottky chip structure schematic diagram.
Fig. 2 ~ Fig. 6 is junction barrier schottky chip manufacturing flow chart.
Fig. 7 is junction barrier schottky diode structural schematic diagram.
Fig. 8 is enlarged drawing at A in Fig. 7.
Fig. 9 is prior art junction barrier schottky chip structure schematic diagram.
Wherein：1, pressure ring 2, schottky interface 3, knot 4 in active area, anode metal layer 5, substrate 6, outer
Prolong layer 7, cathode metal layer 8, cut surface 9, oxide layer 10, chip cutting position 11, lead 12, soldering-tin layer
13, chip 14, passivation layer 15, insulating layer.
Specific implementation mode
Fig. 1 ~ 8 are highly preferred embodiment of the present invention, and 1 ~ 8 the present invention will be further described below in conjunction with the accompanying drawings.
As shown in Figure 1, a kind of junction barrier schottky chip, including substrate 5, it is epitaxial layer 6 in the top of substrate 5, outside
The surface for prolonging layer 6 is provided with several pressure rings 1, and knot 3 in several active areas is additionally provided between two neighboring pressure ring 1.
The surface of epitaxial layer 6 does not open up the position of knot 3 and pressure ring 1 in active area and forms schottky interface 2.It is additionally provided with anode gold
Belong to layer 4 and cathode metal layer 7, wherein anode metal layer 4 are covered in knot 3 in active area, pressure ring 1 and schottky interface 2
Surface, the anode for drawing this junction barrier schottky chip, cathode metal layer 7 are covered in the bottom surface of substrate 5, for drawing this
The cathode of junction barrier schottky chip.Substrate 5 and epitaxial layer 6 are N-type semiconductor, and knot 3 and pressure ring 1 are P+ in active area
Type semiconductor.
In this junction barrier schottky wafer（See Fig. 6）In, chip cutting position 10 at the middle part of the pressure ring 1,
The middle part of each pressure ring 1 is cut longitudinally to form cut surface 8, and cutting forms the junction barrier schottky of several separation after completing
Chip, in each junction barrier schottky chip, including in several active areas at middle part knot 3 and be located at outside pressure ring 1
Half, i.e. same pressure ring 1 is located at after dicing in two adjacent junction barrier schottky chips.
Since cut surface 8 is located at the middle part of pressure ring 1, the arc that 1 bottom bend of pressure ring is formed in the prior art is eliminated
Shape face reduces its electric field strength, improves the pressure-resistant performance of junction barrier schottky chip.Junction barrier schottky chip it is active
The spacing of knot 3 is adjusted according to pressure resistance in area, and the pinch off of PN junction depletion region broadening realization current channel, effectively presses down when reverse-biased
Having made Schottky barrier reduces effect.
As shown in Fig. 2 ~ 6, junction barrier schottky chip as shown in Figure 1 is made, includes the following steps：
Step 1, epitaxial layer 6 is formed in the top of substrate 5, then oxidation processes is carried out on the surface of epitaxial layer 6, in epitaxial layer 6
Surface form oxide layer 9, then the position of knot 3 and pressure ring 1 carries out photoetching to oxide layer 9 in active area, exposes outer
Prolong the surface of layer 6, as shown in Figure 2.
Step 2, the upper surface of the epitaxial layer 6 after photoetching is injected boron ion and is diffused, and is formed simultaneously in active area
Knot 3 and pressure ring 1, as shown in Figure 3.
Step 3, the oxide layer 9 of 6 upper surface of epitaxial layer is removed, as shown in Figure 4.
Step 4, schottky interface metal is sputtered in 6 upper surface of epitaxial layer（Such as titanium, platinum, molybdenum, vanadium, tungsten, aluminium etc.）, annealing
Etc. techniques formed schottky interface 2, as shown in Figure 5.
Step 5, the underrun prior art on the surface of epitaxial layer 6 and substrate 5 is respectively formed 4 He of anode metal layer
Cathode metal layer 7 obtains junction barrier schottky wafer as shown in FIG. 6.
Step 6, junction barrier schottky wafer is cut by chip cutting position 10 shown in Fig. 6, by junction barrier
Schottky wafer divides to obtain the junction barrier schottky chip of separation as shown in Figure 1.
As shown in Fig. 7 ~ 8, junction barrier schottky chip as shown in Figure 1 is being obtained（Hereinafter referred to as chip 13）Afterwards, in core
The anode metal layer 4 of piece 13 and 7 surface of cathode metal layer are dressed up respectively by 12 welding lead 11 of soldering-tin layer by welding procedure
Axial diode, since chip cutting trailing flank Schottky junction structure is destroyed, electric current circulates from 13 side of chip, loses Xiao Te
The function of based diode, it is therefore desirable to which acid wash passivation process is carried out to chip 13（Mixed acid）Edge is washed off, in 13 side of chip
And lower edges area forms a floor passivation layer 14, ultimately forms the finished product of junction barrier schottky diode.
Wherein soldering-tin layer 12 is located at the inside of passivation layer 14, and passivation layer 14 is formed by the outlet in chip 13 so that
Electric current can not circulate from the side of chip 13, and instead of the effect of insulating layer 15 in the prior art, therefore it is existing to eliminate progress
Second in technology and third road lithography step, due in the production technology of this junction barrier schottky chip, only utilizing one
Road photoetching process is big in complex process degree and production cost compared at least needing three photoetching processes in the prior art
It is big to reduce.
The above described is only a preferred embodiment of the present invention, being not that the invention has other forms of limitations, appoint
What those skilled in the art changed or be modified as possibly also with the technology contents of the disclosure above equivalent variations etc.
Imitate embodiment.But it is every without departing from technical solution of the present invention content, according to the technical essence of the invention to above example institute
Any simple modification, equivalent variations and the remodeling made, still fall within the protection domain of technical solution of the present invention.
Claims (6)
1. a kind of junction barrier schottky diode, including junction barrier schottky chip and pass through lead from chip（11）Respectively
The cathode and anode of extraction, junction barrier schottky chip include substrate（5）And substrate（5）The epitaxial layer of top（6）, in extension
Layer（6）Surface be provided with knot in several active areas（3）It is tied with being located in active area（3）The pressure ring of outer ring（1）, in active area
Knot（3）And pressure ring（1）Semiconductor type and epitaxial layer（6）On the contrary, in epitaxial layer（6）Surface be formed with and lead（11）
The anode metal layer of connection（4）, in substrate（5）Bottom surface formed and lead（11）The cathode metal layer of connection（7）, feature exists
In：Chip cutting position（10）In the pressure ring（1）Middle part, from chip cutting position（10）Cutting forms cut surface
（8）, in cut surface（8）And cut surface（8）Lower edges area have passivation layer（14）Covering.
2. junction barrier schottky diode according to claim 1, it is characterised in that：Knot in the active area（3）For P
+ type semiconductor.
3. junction barrier schottky diode according to claim 1, it is characterised in that：The pressure ring（1）For P+ type
Semiconductor.
4. junction barrier schottky diode according to claim 1, it is characterised in that：In the anode metal layer（4）With
Cathode metal layer（7）Surface pass through soldering-tin layer respectively（12）With the lead（11）Welding.
5. junction barrier schottky diode according to claim 4, it is characterised in that：The soldering-tin layer（12）Positioned at blunt
Change layer（14）Inside.
6. one kind being used for the manufacturing method of 1 ~ 5 any one of them junction barrier schottky diode of manufacturing claims, feature
It is, includes the following steps：
Step a, epitaxial layer（6）Surface into places oxidation processes, form oxide layer（9）, then tied in active area（3）And
Pressure ring（1）Position to oxide layer（9）Photoetching is carried out, epitaxial layer is exposed（6）Surface；
Step b, the epitaxial layer after photoetching（6）Upper surface injection boron ion and be diffused, be formed simultaneously knot in active area
（3）And pressure ring（1）；
Step c, by epitaxial layer（6）The oxide layer of upper surface（9）Removal；
Step d, in epitaxial layer（6）Upper surface forms schottky interface（2）；
Step e, in epitaxial layer（6）Surface and substrate（5）Bottom surface be respectively formed anode metal layer（4）And cathode metal layer
（7）, junction barrier schottky wafer is obtained, chip cutting position is then pressed（10）Junction barrier schottky wafer is cut, shape
At cut surface（8）, the junction barrier schottky chip that is detached；
Step f, in the anode metal layer of junction barrier schottky chip（4）Surface passes through welding lead（11）Anode is drawn, in the moon
Pole metal layer（7）Surface pass through welding lead（11）Draw cathode；
Step g carries out acid wash passivation process, in cut surface to junction barrier schottky chip（8）And lower edges form passivation
Layer（14）.
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| CN201810556262.4A CN108493259A (en) | 2018-06-01 | 2018-06-01 | A kind of junction barrier schottky diode and manufacturing method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013091872A1 (en) * | 2011-12-22 | 2013-06-27 | Diotec Semiconductor Ag | Method for producing a schottky diode |
| JP2014011342A (en) * | 2012-06-29 | 2014-01-20 | Denso Corp | Silicon-carbide semiconductor device |
| CN208352297U (en) * | 2018-06-01 | 2019-01-08 | 淄博汉林半导体有限公司 | A kind of junction barrier schottky diode |
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2018
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| JP2014011342A (en) * | 2012-06-29 | 2014-01-20 | Denso Corp | Silicon-carbide semiconductor device |
| CN208352297U (en) * | 2018-06-01 | 2019-01-08 | 淄博汉林半导体有限公司 | A kind of junction barrier schottky diode |
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