CN108491346A - A kind of BMC coding/decoding methods - Google Patents
A kind of BMC coding/decoding methods Download PDFInfo
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- CN108491346A CN108491346A CN201810250926.4A CN201810250926A CN108491346A CN 108491346 A CN108491346 A CN 108491346A CN 201810250926 A CN201810250926 A CN 201810250926A CN 108491346 A CN108491346 A CN 108491346A
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- mcu
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/20—Conversion to or from representation by pulses the pulses having more than three levels
Abstract
The invention discloses a kind of BMC coding/decoding methods, include the following steps, the start bit of MCU detection data frames；First data bit of MCU detection data frames, determines the first original levels and the first termination level；The Nth data position of MCU detection data frames successively, determines N original levels, then compares 1 original levels of N and 1 termination levels of N, determines 1 data bits evidences of N, and 1 data bits of N is cached according to deposit, determines N termination levels；The original levels and termination level of the more last a data positions MCU, determine the data of last a data position, then deposit caching；The stop position of MCU detection data frames.The present invention requires manufacturing cost that is too low and reducing USB PD fast charge equipments to the arithmetic speed and memory space of MCU, reduces requirement of the decoding process to MCU dominant frequency, and using less ram space.
Description
Technical field
The present invention relates to a kind of coding/decoding method, especially a kind of BMC coding/decoding methods.
Background technology
Power transmission protocol USB PD (USB Power Delivery) are based on USB3.1 agreements, are USB3.1 Type-C
The power transmission concept proposed behind port.With the development of USB PD rapid nitridings, people are to USB PD charging equipments
Demand increases rapidly.The core technology of USB PD fast charge equipments is the decoding to PD agreements.It is used in USB PD agreements
Mode be BMC (Biphasic Mark Coding) coding, i.e. BMC decoding processes traditional two-phase label coding to carry out
The arithmetic speed and memory space of the MCU of decoding effort has higher requirement, significantly increases USB-PD fast charge equipments
Manufacturing cost, and the key for reducing cost be that it is how fast using the MCU of fewer resource, relatively low dominant frequency
Speed, accurately decoding USB PD agreements.
Invention content
For problems of the prior art, the present invention provides a kind of arithmetic speeds to MCU and memory space to want
It seeks manufacturing cost low, that USB PD fast charge equipments can be reduced, reduce requirement of the decoding process to MCU dominant frequency, and
Using less ram space, the solution of the agreement to USB PD fast charge equipments is realized using the MCU of inexpensive low-resource
The BMC coding/decoding methods of analysis and control.
The purpose of the present invention is achieved through the following technical solutions.
A kind of BMC coding/decoding methods, include the following steps：
1) start bit of MCU detection datas frame；
2) the first data bit of MCU detection datas frame, in the front half section of the position time of first data bit, MCU detections
The level of current demand signal line, as the first original levels, in the second half section of the position time of first data bit, MCU is examined again
The level for surveying signal wire, as the first termination level；
3) the remainder data position of MCU detection data frames successively, in the front half section of the position time of Nth data position, MCU detections are worked as
The level of front signal line then compares N-1 original levels and N-1 termination levels as N original levels, determines N-1
Data bits evidence, and N-1 data bits is cached according to deposit, then in the second half section of the position time of the Nth data position,
The level of MCU signal lines again, as N termination levels；
4) original levels and termination level of the more last a data positions MCU, determine the data of last a data position,
Then deposit caching；
5) stop position of MCU detection datas frame.
Further, the number that last a data position is determined in N-1 data bit and step 4) is determined in the step 3)
According to specially judging whether the initial level of data bit and termination level are equal, if equal, the data of data bit are 0, if not
Equal, then the data of data bit are 1.
Further, MCU detection datas position, the specially level state of MCU signal lines.
Further, the level state specifically include the logic level rule suitable for MCU absolute high level or
Low level state further includes the opposite high level or low level state of the gained compared with preset datum.
Further, in the step 1) MCU detection data frames start bit, specially MCU judge signal wire release when
Between whether time-out assert that MCU detects the start bit of data frame if time-out and detecting the first failing edge of signal wire.
Further, in the step 5) MCU detection data frames stop position, whether specially MCU signal lines hold
It is continuous to be in high level, if being continuously in high level, assert the stop position for detecting data frame.
Further, in the step 3) by N-1 data bits according in deposit caching and step 4) by last one digit number
It is stored in caching according to the data of position, is specifically included deposit after the data displacement in caching or direct step-by-step deposit caching.
Compared with the prior art, the advantage of the invention is that：The present invention solves operation of traditional decoding process to MCU
Speed and memory space require the problem of manufacturing cost that is excessively high and increasing USB PD fast charge equipments, reduce decoding process
Requirement to MCU dominant frequency, and using less ram space, realized using the MCU of inexpensive low-resource fast to USB PD
The parsing and control of the agreement of fast charging equipment.
Description of the drawings
Fig. 1 is the flow chart of the present invention.
Specific implementation mode
With reference to the accompanying drawings of the specification and specific embodiment, the present invention is described in detail.
As shown in Figure 1, a kind of BMC coding/decoding methods, include the following steps, the start bit of MCU detection data frames；MCU is detected
The start bit of data frame；First data bit of MCU detection data frames, in the front half section of the position time of the first data bit, MCU detections
The level of current demand signal line, as the first original levels, in the second half section of the position time of the first data bit, MCU detects letter again
The level of number line, as the first termination level；Other data bit of MCU detection data frames successively, the position time in Nth data position
Front half section, MCU detection current demand signal line level then compare N-1 original levels and N-1 as N original levels
Termination level determines N-1 data bits evidences, and N-1 data bits is cached according to deposit, then in the position of Nth data position
The second half section of time, the level of MCU signal lines again, as N termination levels；The more last a data positions MCU
Original levels and termination level determine the data of last a data position, then deposit caching；The stopping of MCU detection data frames
Position.Wherein, the multiple that the numerical value of N is 8 or 8 depending on agreement and byte number, such as N；Determine N-1 data bit and last one digit number
According to the data of position, specially judge whether the initial level of the data bit and termination level are equal, if equal, the data
The data of position are 0, if unequal, the data of the data bit are 1；MCU detection datas position, specially MCU signal lines
Level state, wherein the level state specifically includes the absolute high level or low of the logic level rule suitable for MCU
Level state further includes the opposite high level or low level state of the gained compared with preset datum, the method compared
Include based on the comparison circuit designed by the discrete devices such as voltage comparator or operational amplifier or triode.BMC codings are per frame
There is longer signal wire release time between data, signal wire level maintains high level not change in this time, and MCU passes through detection
This time simultaneously judges time-out, and the failing edge for the first time on signal wire is the starting of data frame, therefore, MCU testing numbers after a time out
According to the start bit of frame, specially MCU judges whether signal wire release time overtime, if time-out and detect signal wire it is first under
Edge is dropped, then assert that MCU detects the start bit of data frame.The stop position of MCU detection data frames, specifically, MCU signal lines
Whether it is continuously in high level, if being continuously in high level, assert the stop position for detecting data frame；By the data of data bit
Deposit caching can be stored in or direct according to mode as defined in agreement after the data displacement being specifically including but not limited in caching
Step-by-step deposit caching.
The technical means disclosed in the embodiments of the present invention is not limited only to the technological means disclosed in the above embodiment, further includes
By the above technical characteristic arbitrarily the formed technical solution of combination.
Claims (7)
1. a kind of BMC coding/decoding methods, it is characterised in that include the following steps：
1) start bit of MCU detection datas frame；
2) the first data bit of MCU detection datas frame, in the front half section of the position time of first data bit, MCU detections are current
The level of signal wire, as the first original levels, in the second half section of the position time of first data bit, MCU detects letter again
The level of number line, as the first termination level；
3) the remainder data position of MCU detection data frames successively, in the front half section of the position time of Nth data position, the current letter of MCU detections
The level of number line then compares mono- 1 original levels of N and N-1 termination levels, determines N-1 numbers as N original levels
It is cached according to deposit according to position data, and by N-1 data bits, then in the second half section of the position time of the Nth data position, MCU
The level of signal lines again, as N termination levels；
4) original levels and termination level of the more last a data positions MCU, determine the data of last a data position, then
Deposit caching；
5) stop position of MCU detection datas frame.
2. a kind of BMC coding/decoding methods according to claim 1, it is characterised in that determine N-1 data in the step 3)
The data that last a data position is determined in position and step 4), specially judge data bit initial level and termination level whether
Equal, if equal, the data of data bit are 0, if unequal, the data of data bit are 1.
3. a kind of BMC coding/decoding methods according to claim 1 or 2, it is characterised in that MCU detection datas position, specifically
For the level state of MCU signal lines.
4. a kind of BMC coding/decoding methods according to claim 3, it is characterised in that the level state, which specifically includes, to be suitable for
The absolute high level or low level state of the logic level rule of MCU, further includes the gained compared with preset datum
Opposite high level or low level state.
5. a kind of BMC coding/decoding methods according to claim 1 or 2, it is characterised in that MCU detection datas in the step 1)
The start bit of frame, specially MCU judge whether signal wire release time is overtime, if first decline that is overtime and detecting signal wire
Edge then assert that MCU detects the start bit of data frame.
6. a kind of BMC coding/decoding methods according to claim 1 or 2, it is characterised in that MCU detection datas in the step 5)
The stop position of frame, specially whether MCU signal lines are continuously in high level, if being continuously in high level, assert detection
To the stop position of data frame.
7. a kind of BMC coding/decoding methods according to claim 1 or 2, it is characterised in that by N-1 data in the step 3)
The data of last a data position are stored in caching in position data deposit caching and step 4), are specifically included the data in caching
Deposit or directly step-by-step deposit cache after displacement.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810250926.4A CN108491346A (en) | 2018-03-23 | 2018-03-23 | A kind of BMC coding/decoding methods |
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| CN201810250926.4A CN108491346A (en) | 2018-03-23 | 2018-03-23 | A kind of BMC coding/decoding methods |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109217875A (en) * | 2018-10-24 | 2019-01-15 | 江苏沁恒股份有限公司 | Manchester's code coding/decoding method |
| CN109639613A (en) * | 2019-01-17 | 2019-04-16 | 广东高云半导体科技股份有限公司 | A kind of coding/decoding method based on two-phase symbolic coding, mobile device and storage medium |
| CN110647483A (en) * | 2019-08-02 | 2020-01-03 | 福州瑞芯微电子股份有限公司 | BMC code asynchronous receiving method suitable for USB-PD protocol and storage device |
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| EP1135877B1 (en) * | 1999-10-05 | 2008-02-06 | Samsung Electronics Co., Ltd. | Turbo Decoding with soft-output Viterbi decoder |
| CN102298565A (en) * | 2011-06-08 | 2011-12-28 | 东南大学 | Method for decoding and triggering asynchronous serial bus signals |
| CN105068966A (en) * | 2015-08-19 | 2015-11-18 | 长沙威胜信息技术有限公司 | Serial automatic identification method |
| US20160254902A1 (en) * | 2015-02-23 | 2016-09-01 | Renesas Electronics Corporation | Bmc processing circuit, usb power delivery controller, bmc reception method, and non-transitory computer readable medium storing bmc reception program |
| CN106354682A (en) * | 2016-08-30 | 2017-01-25 | 江苏沁恒股份有限公司 | Digital signal and USB signal mixed transmission device and method |
| CN107515836A (en) * | 2017-09-21 | 2017-12-26 | 英特格灵芯片(天津)有限公司 | The BMC decoding apparatus and method of a kind of dynamic bi-threshold |
-
2018
- 2018-03-23 CN CN201810250926.4A patent/CN108491346A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1135877B1 (en) * | 1999-10-05 | 2008-02-06 | Samsung Electronics Co., Ltd. | Turbo Decoding with soft-output Viterbi decoder |
| CN102298565A (en) * | 2011-06-08 | 2011-12-28 | 东南大学 | Method for decoding and triggering asynchronous serial bus signals |
| US20160254902A1 (en) * | 2015-02-23 | 2016-09-01 | Renesas Electronics Corporation | Bmc processing circuit, usb power delivery controller, bmc reception method, and non-transitory computer readable medium storing bmc reception program |
| CN105068966A (en) * | 2015-08-19 | 2015-11-18 | 长沙威胜信息技术有限公司 | Serial automatic identification method |
| CN106354682A (en) * | 2016-08-30 | 2017-01-25 | 江苏沁恒股份有限公司 | Digital signal and USB signal mixed transmission device and method |
| CN107515836A (en) * | 2017-09-21 | 2017-12-26 | 英特格灵芯片(天津)有限公司 | The BMC decoding apparatus and method of a kind of dynamic bi-threshold |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109217875A (en) * | 2018-10-24 | 2019-01-15 | 江苏沁恒股份有限公司 | Manchester's code coding/decoding method |
| CN109639613A (en) * | 2019-01-17 | 2019-04-16 | 广东高云半导体科技股份有限公司 | A kind of coding/decoding method based on two-phase symbolic coding, mobile device and storage medium |
| CN110647483A (en) * | 2019-08-02 | 2020-01-03 | 福州瑞芯微电子股份有限公司 | BMC code asynchronous receiving method suitable for USB-PD protocol and storage device |
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Application publication date: 20180904 |
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