CN108476298A - 双敏像素cmos图像传感器 - Google Patents
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Abstract
本发明提供一种CMOS图像传感器,包括:像素单元,其中,每个所述像素单元包括PD和TG;像素序列,其中,所述像素单元排列成行;像素序列单元,包括两个相邻的45度角排列的像素序列;输出电路,其将所述PD产生的电荷转换为输出信号;输出电路序列,包括多个以45度角排列成行的输出电路;其中,一个像素序列单元中的相邻PD 1和PD 2构成一个像素对;所述PD 1和PD 2具有相同的光谱灵敏度特性,并且所述PD 1和PD 2的灵敏度不相同;所述像素序列单元和所述输出电路序列交替分布。本发明在保持足够量的信号和小串扰的同时缩小了双敏像素的像素间距。
Description
技术领域
本发明涉及图像传感器领域,尤其涉及高动态范围互补型金属氧化物半导体(complementary metal oxide semiconductor,简称CMOS)图像传感器。
背景技术
双敏像素增加了图像传感器的动态范围,例如,可参见首次公开号为2008-99073的日本未审查专利申请。图1为现有技术的像素电路的电路图。图2为该像素电路排布在硅衬底表面上的俯视图。图3为该像素电路排布在硅衬底上的沿着图2中箭头的横截面图。各缩写的含义如下:PD:光电二极管,用于将光转化为信号电子;PD-L:高敏光电二极管;PD-S:低敏光电二极管;TG:将信号电荷传输到FD的传输栅极;FD:浮动扩散器,其中信号电荷被转换为信号电压;Cfd:FD的电容;RS:设置FD电压的重置栅极;AMP:放大器晶体管,将FD的信号电压转换为低阻抗输出信号;SL:选择晶体管;ADC:模拟数字转换器;G-L:用于绿PD-L的大型微透镜;G-S:用于绿PD-S的小型微透镜;B-L:用于蓝PD-L的大型微透镜;B-S:用于蓝PD-S的小型微透镜;R-L:用于红PD-L的大型微透镜;R-S:用于红PD-S的小型微透镜;ISO:植入像素隔离。
参见图1,PD-L和PD-S是成对出现的,且共享由RS、FD、AMP和SL组成的输出电路。PD将光转化为电信号。该电信号通过TG选择性地传输至FD。该FD与AMP的栅极相连,输出信号通过SL传输给信号线。因此,如果TG和SL的栅极导通,则在信号线上获得与来自PD的电信号对应的输出信号。RS选择性地重置在FD中累积的电荷。图2示出四对PD-L和PD-S。FD显示为配对的PD-L和PD-S之间的黑色小方块。如图3所示,与PD-L配对的PD-S位于PD-L的右下方,它们具有颜色相同的滤光片,并且PD-L和PD-S在滤光片上分别配有大的微透镜和小的微透镜。在图2中,颜色的排列基于拜耳排列。
图4为一般单敏像素的像素电路的电路图。图5为该像素电路排布在硅衬底表面上的俯视图。PD-1和PD-2共享输出电路(图4),它们具有颜色不同的滤光片,例如G和R或B和G(图5)。
对比图5和图2,由于双敏像素需要一种颜色的两个PD,因此不同颜色的像素间距变成单敏像素的像素间距的1.4(2的平方根)倍长。这种像素间距的增大是个问题。
发明内容
本发明提供了双敏高动态范围CMOS图像传感器的像素结构。
根据第一方面,提供了一种CMOS图像传感器,所述CMOS图像传感器包括:
像素单元,其中,每个所述像素单元包括光电二极管(photodiode,简称PD)和传输栅极(transfer gate,简称TG);
像素序列,其中,所述像素单元排列成行;
像素序列单元,包括两个相邻的45度角排列的像素序列;
输出电路,其将所述PD产生的电荷转换为输出信号;
输出电路序列,包括多个以45度角排列成行的输出电路;
其中,一个像素序列单元中的相邻PD 1和PD 2构成一个像素对;
所述PD 1和PD 2具有相同的光谱灵敏度特性,并且所述PD 1和PD 2的灵敏度不相同;所述像素序列单元和所述输出电路序列交替分布。
在第一方面的第一种可能的实现方式中,所述CMOS图像传感器包括所述PD 1和PD2上具有相同的光谱灵敏度特性的有色滤光片。
结合第一方面,在第一方面的第二种可能的实现方式中,所述CMOS图像传感器包括所述PD 1和PD 2上具有不同光采集率的微透镜。
结合第一方面,在第一方面的第三种可能的实现方式中,所述CMOS图像传感器包括与所述TG相连的浮动扩散器,其聚集所述PD产生并通过所述TG传输的电荷,其中,所述PD1和PD 2共享一个FD。
结合第一方面,在第一方面的第四种可能的实现方式中,像素序列单元中与像素对PD 1n和PD 2n相邻的像素对包括位于所述像素序列单元中倾斜方向上的所述PD 1n和PD2n的上方的像素对PD 1m和PD 2m。
结合第一方面,在第一方面的第五种可能的实现方式中,像素序列单元中与像素对PD 1n和PD 2n相邻的像素对包括位于所述像素序列单元中所述PD 1n和PD 2n的水平方向上的像素对PD 1k和PD 2k。
结合第一方面的第四种可能的实现方式,在第一方面的第六种可能的实现方式中,所述PD 1n、PD 2n、PD 1m和PD 2m共享一个FD。
结合第一方面的第五种可能的实现方式,在第三方面的第七种可能的实现方式中,所述PD 1n和PD 2n共享一个FD n,所述PD 1k和PD 2k共享一个FD k,所述FD n和FD k之间为电连接。
结合第一方面,在第一方面的第八种可能的实现方式中,深沟槽隔离用于从基板的入射面到至少一部分朝向相对侧的PD之间的绝缘体。
结合第一方面或第一方面的第八种可能的实现方式,在第三方面的第九种可能的实现方式中,PD之间的元件隔离区域从基板的入射面朝相对侧变宽。
根据各种实现方式提供了一种CMOS图像传感器,以在保持足够量的信号和小串扰的同时缩小双敏像素的像素间距。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍。显而易见地,下面描述中的附图仅仅示出本发明的一些实施例,并且对于本领域普通技术人员来说,在不付出创造性劳动的前提下,还可以根据这些附图获得其它附图。
图1为现有技术的像素电路的电路图;
图2为该像素电路排布在硅衬底表面上的俯视图;
图3为该像素电路排布在硅衬底上的沿着图2中箭头的横截面图;
图4为一般单敏像素的像素电路的电路图;
图5为该像素电路排布在硅衬底表面上的俯视图;
图6为本发明实施例提供的像素电路的电路图;
图7为该像素电路排布在硅衬底表面上的俯视图;
图8A为该像素电路排布在硅衬底上的沿着图7中箭头的横截面图;
图8B为该像素电路排布在硅衬底上的沿着图2中箭头的横截面图;
图9示出PD之间具有绝缘体隔离的另一实施例;
图10为从衬底背面看微透镜和DTI的视图;
图11示出具有绝缘体隔离的另一布局的另一实施例;
图12为从衬底背面看微透镜和DTI的视图;
图13示出图6所示的八光电二极管共享像素电路的另一个实施例;
图14示出图6所示的八光电二极管共享像素电路的又一个实施例;
图15示出光电二极管布局与图6相同并且微透镜和有色滤光片布局与图2相同的示例;
图16为一实施例中四光电二极管共享像素电路的电路图;
图17为该像素电路排布在硅衬底表面上的俯视图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅为本发明实施例的一部分,而非全部。基于本发明实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
图6为本发明实施例提供的像素电路的电路图。图7为该像素电路排布在硅衬底表面上的俯视图。CMOS图像传感器包括:像素单元,其中,每个所述像素单元包括PD和TG;像素序列,其中,所述像素单元排列成行;像素序列单元,包括两个相邻的45度角排列的像素序列;输出电路,其将所述PD产生的电荷转换为输出信号;输出电路序列,包括多个以45度角排列成行的输出电路。所述像素序列单元和所述输出电路序列交替分布。在图7中,粗线区域的八个PD共享一个由RS、FD、AMP和SL组成的输出电路。4(即2×2)个PD和TG共享一个FD(如图7所示的黑色小方块)。图7中的粗线区域中的上方四个PD可以当作像素序列单元中的像素对PD 1n和PD 2n以及位于像素序列单元中倾斜方向上的PD 1n和PD 2n的上方的相邻像素对PD 1m和PD 2m。PD 1n、PD 2n、PD 1m和PD 2m分别对应于粗线区域中的上方四个PD中的具有G-L、G-S、R-S和R-L的PD。PD 1n、PD 2n、PD 1m和PD 2m共享一个FD。粗线区域中的两个FD与一个AMP相连,也即,在CMOS图像传感器中重复倾斜的两个光电二极管行与倾斜的一个晶体管行。
一个像素序列单元中的相邻PD-L和PD-S构成一个像素对。假定PD-L和PD-S中的一个产生用于预定波长a的光的光电转换电子1a,和用于预定波长b的光的光电转换电子1b,PD-L和PD-S中的另一个产生用于预定波长a的光的光电转换电子2a,和用于预定波长b的光的光电转换电子2b,这里使用的PD具有如下特性:1a/1b与2a/2b大致相同,并且1a不等于2a,1b不等于2b。也即,所述PD-L和PD-S具有相同的光谱灵敏度特性,并且所述PD-L和PD-S的灵敏度不相同。
在图7中,在粗线区域中的上方四个PD中,右侧PD具有红色滤光片和大型微透镜(R-L),左侧PD具有绿色滤光片和大型微透镜(G-L),上方PD具有红色滤光片和小型微透镜(R-S),下方PD具有绿色滤光片和小型微透镜(G-S);在粗线区域中的下方四个PD中,右侧PD具有红色滤光片和大型微透镜(R-L),左侧PD具有绿色滤光片和大型微透镜(G-L),上方PD具有红色滤光片和小型微透镜(R-S),下方PD具有绿色滤光片和小型微透镜(G-S)。颜色的排列不限于拜耳排列。像素对中的PD-L和PD-S上提供了具有相同的光谱灵敏度特性的有色滤光片和具有不同光采集率的微透镜。
在如图6和图7所示的组成方式中,每种颜色的像素晶体管的个数为2.75个(4种颜色的11个晶体管),而在现有技术(图1)中是5个(1种颜色的5个晶体管)。因此,像素间距变小。假设单敏(图4)中像素间距是1,现有技术双敏(图2)中像素间距约为1.4(2的平方根),本发明实施例(图7)的像素间距约为1.15(实际测量值)。
在图7中,R-S和B-S分别位于R-L和B-L的左上方,而在图2中,R-S和B-S位于R-L和B-L的右下方。这是为了在共享的FD上将R-S和R-L的电荷信号添加到G-L和G-S的电荷信号,并且在共享的FD上将B-S和B-L的电荷信号添加到G-L和G-S的电荷信号。
图8A为该像素电路排布在硅衬底上的沿着图7中箭头的横截面图。采用背照(Backside illumination,简称BSI)来增加灵敏度并减少串扰。有色滤光片和微透镜位于基板的背面。图8B为该像素电路排布在硅衬底上的沿着图2中箭头的横截面图。对比图8A和图8B,其中,图8B的光来自上方而图8A的光来自底部。在图8B中,光在有色滤光片与硅衬底表面之间的栅极和金属线(未示出)处反射。因此,灵敏度降低或串扰提高。在图8A中,ISO的宽度在入射面可以更窄,因为在入射面侧不存在栅极或金属线。由图8可见,基板背面上的PD之间的绝缘体的宽度比晶体管窄。这也使串扰更小。因此,在这些实施例中,像素间距可以减小。
图9示出PD之间具有绝缘体隔离的另一实施例。采用了深沟槽隔离(deep trenchisolation,简称DTI)。深沟槽隔离用于从基板的入射面到至少一部分朝向相对侧的PD之间的绝缘体。这减小了光电二极管之间的串扰。
图10为从衬底背面看微透镜和DTI(黑色区域)的视图。DTI布局是重复简单的正方形形状。图11示出具有绝缘体隔离的另一布局的另一实施例。PD之间的元件隔离区域从基板的入射面朝相对侧变宽。图12为从衬底背面看微透镜和DTI(黑色区域)的视图。DTI区域根据微透镜区域的不同而不同。因为DTI和微透镜的孔缝基本一样,所以串扰更小。
图13示出图6所示的八光电二极管共享像素电路的另一个实施例。PD-L和PD-S相对,并共享一个FD。粗线区域的8个PD共享一个输出电路。相对的像素是成对的,具有同色的有色滤光片。PD-L具有大微透镜,而PD-S具有小微透镜。垂直方向每4对为1组,并共享输出电路。在图13中,对于一个组中的每两个对沿着一对像素的一侧提供晶体管区域。每组中的对数不限于4对,水平方向的对可以分组。图14示出图6所示的八光电二极管共享像素电路的又一个实施例。粗线区域的8个PD共享一个输出电路。与图13中一样,垂直方向每4对为1组,对于一个组中的每两个对沿着一对像素的一侧提供晶体管区域。在图14中,FD在倾斜方向上排列成行。与图13中像素电路相比,对于每一组中的第一和第三对像素,FD排列在像素相邻的一侧的一端,对于每一组中的第二和第四对像素,FD排列在像素相邻的一侧的另一端。对比图7、图13和图14中PD的面积,图7中PD的面积>图14中PD的面积>图13中PD的面积。
图15示出光电二极管布局与图6相同并且微透镜和有色滤光片布局与图2相同的示例。粗线区域的8个PD共享一个输出电路。此时,PD-L和PD-S的电荷装仓是不可用的,因为具有R-S的PD-S位于具有R-L的PD-L的右下方,而不是左上方,并且具有B-S的PD-S位于具有B-L的PD-L的右下方而不是左上方。
图16为一实施例中四光电二极管共享像素电路的电路图。图17为该像素电路排布在硅衬底表面上的俯视图。粗线区域的4个PD共享一个输出电路。粗线区域中的上面四个PD可以当作像素序列单元中的像素对PD 1n和PD 2n以及位于像素序列单元中PD 1n和PD 2n的水平方向的相邻像素对PD 1k和PD 2k。PD 1n、PD 2n、PD 1k和PD 2k分别对应于粗线区域中具有G-L、G-S、R-L和R-S的PD。PD 1n和PD 2n共享一个FD n(PD 1n和PD 2n之间的黑色小方块),PD 1k和PD 2k共享一个FD k(PD 1k和PD 2k之间的黑色小方块),FD n和FD k之间为电连接。与图13不同的是,水平方向中的每2对为1组。对于所述每两个对沿着一对像素的一侧提供晶体管区域。该像素间距小于现有技术的像素间距,但大于八光电二极管共享像素电路的像素间距。
上述披露的仅是本发明的示例实施例,当然并非旨在限制本发明的保护范围。本领域普通技术人员可以理解的是,实施前述实施例的全部或部分流程以及根据本发明权利要求进行的等效修改都应属于本发明的范围内。
Claims (10)
1.一种互补型金属氧化物半导体(complementary metal oxide semiconductor,简称CMOS)图像传感器,其特征在于,包括:
像素单元,其中,每个所述像素单元包括光电二极管(photodiode,简称PD)和传输栅极(transfer gate,简称TG);
像素序列,其中,所述像素单元排列成行;
像素序列单元,包括两个相邻的45度角排列的像素序列;
输出电路,其将所述PD产生的电荷转换为输出信号;
输出电路序列,包括多个以45度角排列成行的输出电路;
其中,一个像素序列单元中的相邻PD 1和PD 2构成一个像素对;
所述PD 1和PD 2具有相同的光谱灵敏度特性,并且所述PD 1和PD 2的灵敏度不相同;
所述像素序列单元和所述输出电路序列交替分布。
2.根据权利要求1所述的CMOS图像传感器,其特征在于,包括所述PD 1和PD 2上具有相同的光谱灵敏度特性的有色滤光片。
3.根据权利要求1所述的CMOS图像传感器,其特征在于,包括所述PD 1和PD 2上具有不同光采集率的微透镜。
4.根据权利要求1所述的CMOS图像传感器,其特征在于,包括与所述TG相连的浮动扩散器,其聚集所述PD产生并通过所述TG传输的电荷,其中,所述PD 1和PD 2共享一个FD。
5.根据权利要求1所述的CMOS图像传感器,其特征在于,像素序列单元中与像素对PD1n和PD 2n相邻的像素对包括位于所述像素序列单元中倾斜方向上的所述PD 1n和PD 2n的上方的像素对PD 1m和PD 2m。
6.根据权利要求1所述的CMOS图像传感器,其特征在于,像素序列单元中与像素对PD1n和PD 2n相邻的像素对包括位于所述像素序列单元中所述PD 1n和PD 2n的水平方向上的像素对PD 1k和PD 2k。
7.根据权利要求5所述的CMOS图像传感器,其特征在于,所述PD 1n、PD 2n、PD 1m和PD2m共享一个FD。
8.根据权利要求6所述的CMOS图像传感器,其特征在于,所述PD 1n和PD 2n共享一个FDn,所述PD 1k和PD 2k共享一个FD k,所述FD n和FD k之间为电连接。
9.根据权利要求1所述的CMOS图像传感器,其特征在于,深沟槽隔离用于从基板的入射面到至少一部分朝向相对侧的PD之间的绝缘体。
10.根据权利要求1或9所述的CMOS图像传感器,其特征在于,PD之间的元件隔离区域从基板的入射面朝相对侧变宽。
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