CN108470740A - Imaging sensor and forming method thereof - Google Patents
Imaging sensor and forming method thereof Download PDFInfo
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- CN108470740A CN108470740A CN201810181210.3A CN201810181210A CN108470740A CN 108470740 A CN108470740 A CN 108470740A CN 201810181210 A CN201810181210 A CN 201810181210A CN 108470740 A CN108470740 A CN 108470740A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000003384 imaging method Methods 0.000 title claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 264
- 229910052751 metal Inorganic materials 0.000 claims abstract description 119
- 239000002184 metal Substances 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000011229 interlayer Substances 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 35
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 25
- 238000005229 chemical vapour deposition Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000005286 illumination Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 235000019994 cava Nutrition 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Technical solution of the present invention discloses a kind of imaging sensor and forming method thereof, the wherein forming method of imaging sensor, including：Semiconductor substrate is provided；Discrete photodiode and deep trench isolation structure are formed in the semiconductor substrate, the deep trench isolation structure is between the photodiode；Interlayer dielectric layer is formed in the semiconductor substrate surface, the interlayer dielectric layer covers the photodiode and the deep trench isolation structure；Amorphous carbon layer is formed on the interlayer dielectric layer；The amorphous carbon layer is etched to the inter-level dielectric layer surface is exposed, forms groove；Insulating layer is formed in the agraphitic carbon layer surface, recess sidewall and bottom；Metal layer is formed in the surface of insulating layer；The metal layer and the insulating layer are etched to the inter-level dielectric layer surface is exposed, forms the metal grate of discrete arrangement；Remove the amorphous carbon layer.The critical size of metal grate is formed by when sufficiently small, will not cave in situation.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor devices more particularly to imaging sensors and forming method thereof, especially
Back side illumination image sensor and forming method thereof.
Background technology
Imaging sensor receives optical signal from object and converts optical signal into electric signal, and then electric signal can be transmitted
For further handling, such as digitizes, then stored in such as memory device of memory, CD or disk, or use
In display over the display, printing etc..Imaging sensor is commonly used in digital camera, video camera, scanner, facsimile machine etc.
Device.
Imaging sensor is usually two types, charge coupling device (CCD) sensor and cmos image sensor
(CIS).CCD is known as photoelectric coupled device, collects charge by photoelectric effect, often the charge of row pixel is sent to clock signal
It simulates on shift register, then serial conversion is voltage.CIS is a kind of solid state image sensor of fast development, due to
Image sensor portion and control circuit part in cmos image sensor are integrated in same chip, therefore cmos image passes
Sensor it is small, low in energy consumption, cheap, have more advantage compared to traditional CCD (Charged Couple) imaging sensor, also more
It is easily universal.
Existing cmos image sensor includes mainly preceding illuminated (Front-side Illumination, abbreviation FSI)
Cmos image sensor and back-illuminated type (Back-side Illumination, abbreviation BSI) two kinds of cmos image sensor.Its
In, in back side illumination image sensor, light from the light sensitive diode in the back surface incident to imaging sensor of imaging sensor,
To convert light energy into electric energy；Back-illuminated cmos image sensors are because its better photoelectric conversion result (i.e. imitate by quantum conversion
Rate is high) and the wider application of acquisition.
But with the continuous reduction of process node, during making back side illumination image sensor, the ruler of metal grate
It is very little to be increasingly not easily controlled.
Invention content
Technical solution of the present invention technical problems to be solved are to provide a kind of imaging sensor and forming method thereof, effectively control
The size of metal grate processed ensures the performance of imaging sensor.
In order to solve the above technical problems, technical solution of the present invention provides a kind of forming method of imaging sensor, including：It carries
For semiconductor substrate；Discrete photodiode and deep trench isolation structure, the zanjon are formed in the semiconductor substrate
Recess isolating structure is between the photodiode；Interlayer dielectric layer, the interlayer are formed in the semiconductor substrate surface
Dielectric layer covers the photodiode and the deep trench isolation structure；Agraphitic carbon is formed on the interlayer dielectric layer
Layer；The amorphous carbon layer is etched to the inter-level dielectric layer surface is exposed, forms groove；The agraphitic carbon layer surface,
Insulating layer is formed on recess sidewall and bottom；Metal layer is formed in the surface of insulating layer；Etch the metal layer and the insulation
Layer forms the metal grate of discrete arrangement to the inter-level dielectric layer surface is exposed；Remove the amorphous carbon layer.
Optionally, the material of the metal layer is tungsten or aluminium, and the technique for forming the metal layer is chemical vapour deposition technique
Or physical vaporous deposition.
Optionally, the technique for forming the interlayer dielectric layer is chemical vapour deposition technique.
Optionally, the interlayer dielectric layer is single layer structure or laminated construction；When the interlayer dielectric layer is single layer structure
When, material is silicon oxide or silicon nitride；When the interlayer dielectric layer is laminated construction, including it is located at the semiconductor substrate table
The silicon oxide layer in face is located at the silicon nitride layer on the silicon oxide layer surface.
Optionally, the material of the insulating layer is bottom anti-reflective layer material or silicon oxynitride, forms the insulating layer
Technique is chemical vapour deposition technique.
Optionally, the method for removing the amorphous carbon layer is cineration technics.
Optionally, after removing the amorphous carbon layer, further include：Passivation layer is formed on the interlayer dielectric layer, and
The passivation layer covers the metal grate and the insulating layer.
Optionally, after the surface of insulating layer forms metal layer, before etching the metal layer and the insulating layer,
Further include：Protective layer is formed in the layer on surface of metal.
Optionally, the metal layer and the insulating layer are etched while etching the protective layer.
The metal interconnection structure formed using the above method, including：Semiconductor substrate；Photodiode is located at described half
In conductor substrate, and the discrete arrangement of the photodiode；Deep trench isolation structure is located in the semiconductor substrate, and position
Between the photodiode；Interlayer dielectric layer is located at the semiconductor substrate surface, and the interlayer dielectric layer covers institute
State photodiode and the deep trench isolation structure；Metal grate, it is discrete to be arranged on the interlayer dielectric layer；Insulating layer,
Positioned at the inter-level dielectric layer surface, and positioned at the bottom of the metal grate and wherein in one side wall.
Compared with prior art, technical solution of the present invention has the advantages that：
One layer of amorphous carbon layer is initially formed on interlayer dielectric layer, since amorphous carbon layer has porosity and looseness, Neng Gouding
The position of adopted metal grate and support metal grate, therefore during etching the metal layer, the metal layer side
There is the support of the amorphous carbon layer and the insulating layer will not when the critical size of the metal grate is sufficiently small
There is a situation where cave in and peel off；And during process node is ever-reduced, effectively controls the metal grate and close
Key size reaches corresponding requirements, further ensures the performance of imaging sensor and the yield of device.In addition, due to metal grate
Critical size controllability it is good, so that the usage amount of metal material is reduced, saved cost.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of back side illumination image sensor；
Fig. 2 to Fig. 9 is the corresponding structure of each step of back side illumination image sensor forming method in first embodiment of the invention
Schematic diagram；
Figure 10 to Figure 18 is the corresponding knot of each step of back side illumination image sensor forming method in second embodiment of the invention
Structure schematic diagram.
Specific implementation mode
In the manufacturing process of existing back side illumination image sensor, need semiconductor substrate surface formed deep trouth every
From structure and metal grate.Such as：Photodiode area in semiconductor substrate, the in order to prevent photoproduction of different zones
Carrier diffusion is to adjacent area, the problem of causing image fault, can form deep trench isolation in semiconductor substrate, contribute to
It avoids the problem that photo-generated carrier diffusion occurs between different pixels region.Then in the table of the semiconductor substrate of wafer rear
Face forms metal grate.
Specifically, the back side illumination image sensor that prior art shown in FIG. 1 is formed can be referred to.
Referring to Fig.1, semiconductor substrate 10 is provided, discrete photodiode 20, institute are formed in the semiconductor substrate
It states and is isolated by deep trench isolation structure 30 between discrete photoelectric diode 20, the depth of the deep trench isolation structure 30
It is deeper than the photodiode 20, to obtain better isolation effect, avoid that photoproduction load occurs between different pixels region
The problem of stream diffusion.
It then proceedes to, with reference to figure 1, be formed with silicon oxide or silicon nitride or both group on the surface of the semiconductor substrate 10
It is combined into the interlayer dielectric layer 40 of material；Metal layer 50 and insulating layer 60 and photoresist are sequentially formed on the interlayer dielectric layer 40
Layer (not shown)；After patterning photoresist layer, using photoresist layer as mask, insulating layer 60, metal layer 50 are performed etching, into
And form metal grate.
The present inventor is by the study found that constantly becoming smaller with process node, the critical size of metal grate
(Critical Dimension, CD) also constantly reduce, therefore by existing etching technics formed metal grate during, by
Bad in size assurance, metal grate, which is easy to happen, caves in and peels off (Peeling), not only influences the size control of metal grate
System, but also follow-up electricity conversion can be influenced, so that the yield of imaging sensor is reduced.
To solve the technical problem, a kind of image sensor architecture of present invention offer and forming method thereof, it is situated between in interlayer
It is initially formed one layer of amorphous carbon layer on matter layer, since amorphous carbon layer has the characteristic of porosity and looseness, is etching the metal layer
During, since there is the support of the amorphous carbon layer and the insulating layer in the metal layer side, the metal grate
It, will not there is a situation where cave in and peel off when critical size is sufficiently small；And in the ever-reduced process of process node
In, effectively control the metal grate critical size and reach corresponding requirements, further ensure imaging sensor performance and
The yield of device.In addition, the critical size controllability due to metal grate is good, the usage amount of metal material is made to reduce, saved
Cost.
Technical solution of the present invention is described in detail with reference to embodiment and attached drawing.
First embodiment
Fig. 2 to Fig. 9 is the corresponding structure of each step of back side illumination image sensor forming method in first embodiment of the invention
Schematic diagram.
With reference to figure 2, semiconductor substrate 110 is provided, forms discrete photodiode in the semiconductor substrate 110
120；Deep trench isolation structure 130 is formed in the semiconductor substrate 110, the deep trench isolation structure 130 is located at photoelectricity
Between diode 120, and the depth of the deep trench isolation structure 130 is deeper than the photodiode 120, more preferable to obtain
Isolation effect, avoid the problem that between different pixels region occur photo-generated carrier diffusion；In the semiconductor substrate 110
Surface forms interlayer dielectric layer 140, and the interlayer dielectric layer 140 covers the photodiode 120 and the deep trench isolation
Structure 130.
In the present embodiment, the semiconductor substrate 110 can be silicon substrate or the material of the semiconductor substrate 110
Can also be germanium, SiGe, silicon carbide, GaAs or gallium indium, the semiconductor substrate 110 can also be the silicon on insulator
Germanium substrate on substrate or insulator, or growth have the substrate of epitaxial layer.
In the present embodiment, the photodiode 120 is sensor devices, and the optical signal received is converted to telecommunications
Number.In order to meet the semiconductor substrate 110 overall thickness thinning requirement, usual each photodiode 120 is in institute
It states the position in semiconductor substrate 110 and lies substantially in same depth.
In the present embodiment, the technique for forming the deep trench isolation structure 130 is as follows：In the semiconductor substrate 110
Surface forms photoresist layer (not shown)；Graphical photoresist layer defines deep trench isolation figure；With patterned photoresist
Layer is mask, along semiconductor substrate 110 described in deep trench isolation pattern etching, to obtain deep trench；The photoresist layer is removed,
Then insulation material layer, and the full deep trench of insulation material layer filling are formed in the semiconductor substrate 110；To exhausted
Edge material layer is planarized, until exposing the semiconductor substrate 110, forms deep trench isolation structure 130.
Wherein, the insulation material layer may include silicon oxide or silicon nitride.
In other embodiments, resistance can be formed in the zanjon groove sidewall and bottom before fill insulant layer
Barrier, the problem of further preventing light crosstalk and cross talk of electrons.
In the present embodiment, the interlayer dielectric layer 140 can be the lamination of silica and silicon nitride, i.e., partly led prior to described
Body substrate surface forms silicon oxide layer, then forms silicon nitride layer then at silicon oxide layer surface；Or the oxidation for single layer structure
The silicon nitride of silicon or single layer structure.The technique for forming the interlayer dielectric layer 140 can be chemical vapour deposition technique.
With reference to Fig. 3, amorphous carbon layer 150 is formed on the interlayer dielectric layer 140.
In the present embodiment, the technique for forming the amorphous carbon layer 150 can be chemical vapour deposition technique, in the present embodiment
Process node in, the thickness of the amorphous carbon layer 150 is 2000 angstroms~3000 angstroms.The effect of the amorphous carbon layer 150
It is the height for defining metal grate, supports the formation of metal grate.
With reference to figure 4, the amorphous carbon layer 150 is etched to 140 surface of interlayer dielectric layer is exposed, forms groove
150a, for the metal grate reserved location being subsequently formed.
In the present embodiment, the technique for etching the amorphous carbon layer 150 can be dry etching method, used etching gas
Body is oxygen.
With reference to figure 5, insulating layer 160 is formed in 150 surface of the amorphous carbon layer, groove 150a side walls and bottom.
In the present embodiment, the material of the insulating layer 160 can be silicon oxynitride or other bottom anti-reflective layer materials,
The technique for forming the insulating layer 160 can be chemical vapour deposition technique.The effect of the insulating layer 160 is for buffering.
With reference to figure 6, in 160 forming metal layer on surface 170 of the insulating layer.
In the present embodiment, the material of the metal layer 170 can be tungsten or aluminium etc..When the material of the metal layer 170 is
Chemical vapor deposition (Chemical Vapor Deposition, CVD) technique may be used when tungsten to be formed, when the metal layer
170 material may be used physical gas-phase deposition when being aluminium and be formed.In the process node of the present embodiment, the metal layer
100 angstroms~200 angstroms of 170 thickness.
With reference to figure 7, the metal layer 170 and the insulating layer 160 shown in fig. 6 are etched to the exposing interlayer dielectric layer
140 surfaces form metal grate 170a.
In the present embodiment, the concrete technology for forming metal grate 170a is as follows：The metal layer shown in Fig. 6
170 surface forms photoresist layer (not shown)；Graphical photoresist layer defines metal grate figure；With patterned light
Photoresist layer is mask, and the metal layer 170 and the insulating layer 160 are sequentially etched to the exposing interlayer along metal grate figure
140 surface of dielectric layer obtains metal grate 170a.
In the present embodiment, used etching technics is dry etching, and used gas can be Cl2、O2Or CxFy
Deng.
In the present embodiment, during etching metal layer 170, since there is the nothing in 170 side of the metal layer
When the critical size of the support of amorphous carbon layer 150 and the insulating layer 160, the metal grate 170a is sufficiently small, also not
There is a situation where caving in and peeling off imaging sensor can be also ensured while ensure that the metal grate 170a critical sizes
Yield.In addition, the critical size controllability due to metal grate 170a is good, the metal material used is less, saves
Cost.
With reference to figure 8, the amorphous carbon layer 150 is removed, is completely exposed the metal grate 170a of discrete arrangement, and
It is surrounded by half in the insulating layer 160 of the metal grate 170a.
In the present embodiment, the technique for removing the amorphous carbon layer 150 is ashing method, and the temperature of ashing is 100 DEG C~200
℃。
With reference to figure 9, passivation layer 180 is formed on the interlayer dielectric layer 140, and the passivation layer 180 covers the gold
Belong to grid 170a and the insulating layer 160.
In the present embodiment, the material of the passivation layer 180 can be ethyl orthosilicate (TEOS).To protect metal grate
The top of 170a, and prevent metal layer from diffusing into imaging sensor, to generate dark current or white point, influence image biography
The performance of sensor.
In subsequent technique, filter layer is formed between the metal grate 170a, forms lens on filter layer
Layer.
Above-described embodiment formed imaging sensor include：Semiconductor substrate 110；Photodiode 120 is located at described half
In conductor substrate 110, and 120 discrete arrangement of the photodiode, and 120 upper surface of the photodiode is partly led with described
110 surface of body substrate flushes；Deep trench isolation structure 130 is located in the semiconductor substrate 110, for each light to be isolated
Electric diode 120, and the depth of the deep trench isolation structure 130 is deeper than the photodiode 120；Interlayer dielectric layer 140,
Positioned at 110 surface of the semiconductor substrate, and the interlayer dielectric layer 140 covers the photodiode 120 and the zanjon
Recess isolating structure 130；Metal grate 170a, it is discrete to be arranged on the interlayer dielectric layer 140；Insulating layer 160 is located at the gold
Belong to the bottom of grid 170a and wherein in one side wall, and the insulating layer 160 positioned at the bottoms the metal grate 170a is located at
140 surface of the interlayer dielectric layer；Passivation layer 180 is located on the interlayer dielectric layer 140, and the passivation layer 180 covers institute
State metal grate 170a and the insulating layer 160, the passivation layer 180 to protect the top of the metal grate 170a, with
And prevent metal layer from diffusing into imaging sensor, to generate dark current or white point.
Completely imaging sensor further includes：Filter layer, between the metal grate 170a；Lens jacket is located at institute
State filter layer.
Second embodiment
Figure 10 to Figure 18 is the corresponding knot of each step of back side illumination image sensor forming method in second embodiment of the invention
Structure schematic diagram.
With reference to figure 10, semiconductor substrate 210 is provided, forms discrete photodiode in the semiconductor substrate 210
220；Deep trench isolation structure 230 is formed in the semiconductor substrate 210, the deep trench isolation structure 230 is located at photoelectricity
Between diode 220, and the depth of the deep trench isolation structure 230 is deeper than the photodiode 220, more preferable to obtain
Isolation effect, avoid the problem that between different pixels region occur photo-generated carrier diffusion；In the semiconductor substrate 210
Surface forms interlayer dielectric layer 240, and the interlayer dielectric layer 240 covers the photodiode 220 and the deep trench isolation
Structure 230.
In the present embodiment, material used by semiconductor substrate 210, the technique for forming deep trench isolation structure 230, zanjon
The material of the insulating materials and interlayer dielectric layer 240 filled in slot and formation process etc. are identical with first embodiment,
It is repeated no more in this embodiment.
It is sensor devices in the photodiode 220, and the optical signal received is converted into telecommunications in the present embodiment
Number.In order to meet the semiconductor substrate 210 overall thickness thinning requirement, usual each photodiode 220 is in institute
It states the position in semiconductor substrate 210 and lies substantially in same depth.
Referring to Fig.1 1, amorphous carbon layer 250 is formed on the interlayer dielectric layer 240.
In the present embodiment, the technique for forming the amorphous carbon layer 250 can be chemical vapour deposition technique, in the present embodiment
Process node in, the thickness of the amorphous carbon layer 250 is 2000 angstroms~3000 angstroms.The effect of the amorphous carbon layer 250
It is the height for defining metal grate, supports the formation of metal grate.
With reference to figure 12, the amorphous carbon layer 250 is etched to 240 surface of interlayer dielectric layer is exposed, forms groove
250a, for the metal grate reserved location being subsequently formed.
In the present embodiment, the technique for etching the amorphous carbon layer 250 can be dry etching method, used etching gas
Body is oxygen.
With reference to figure 13, insulating layer 260 is formed in 250 surface of the amorphous carbon layer and groove 250a side walls and bottom.
In the present embodiment, the material of the insulating layer 260 can be silicon oxynitride, the technique for forming the insulating layer 260
It can be chemical vapour deposition technique.The effect of the insulating layer 260 is for buffering.
With reference to figure 14, in 260 forming metal layer on surface 270 of the insulating layer.
In the present embodiment, the material of the metal layer 270 can be tungsten or aluminium etc..When the material of the metal layer 270 is
Chemical vapor deposition (Chemical Vapor Deposition, CVD) technique may be used when tungsten to be formed, when the metal layer
270 material may be used physical gas-phase deposition when being aluminium and be formed.In the process node of the present embodiment, the metal layer
100 angstroms~200 angstroms of 270 thickness.
With reference to figure 15, protective layer 280 is formed on 270 surface of the metal layer.
In the present embodiment, the material of the protective layer 280 can be silicon oxynitride or silica etc..Form the protective layer
280 technique is chemical vapour deposition technique.
The effect of the protective layer 280 is to protect the top of metal grate 270a, and prevents metal layer from diffusing into
Imaging sensor influences the performance of imaging sensor to generate dark current or white point.
With reference to figure 16, it is sequentially etched the protective layer 280, the metal layer 270 and the insulating layer shown in figure 15
260, form metal grate 270a.
In the present embodiment, the concrete technology for forming metal grate 270a is as follows：In the protective layer shown in figure 15
280 surface forms photoresist layer (not shown)；Graphical photoresist layer defines metal grate figure；With patterned light
Photoresist layer is mask, the protective layer 280 being sequentially etched along metal grate figure, the metal layer 270 and the insulating layer
260, to 240 surface of interlayer dielectric layer is exposed, obtain metal grate 270a.
In the present embodiment, used etching technics is dry etching, and used gas is that used gas can be with
It is Cl2、O2Or CxFyDeng.
In the present embodiment, during etching metal layer 270, since there is the nothing in 270 side of the metal layer
The support of amorphous carbon layer 250 and the insulating layer 260, and top and another side wall are stated protective layer protection, therefore described
When the critical size of metal grate 270a is sufficiently small, the metal will not ensure that there is a situation where caving in and peeling off
The performance of imaging sensor is also ensured while grid 270a critical sizes.In addition, due to the crucial ruler of metal grate 270a
Very little controllability is good, and the metal material used is less, has saved cost.
With reference to figure 17, the amorphous carbon layer 250 is removed, is completely exposed the metal grate 270a of discrete arrangement, with
And surround the insulating layer 260 and the protective layer 280 of the metal grate 270a.
In the present embodiment, the technique for removing the amorphous carbon layer 250 is ashing method.
With reference to figure 18, passivation layer 290 is formed on the interlayer dielectric layer 240, and the passivation layer 290 covers the guarantor
Sheath 280, the metal grate 270a and the insulating layer 260.
In subsequent technique, filter layer is formed between the metal grate 270a, forms lens on filter layer
Layer.
In the present embodiment, the material of the passivation layer 290 can be ethyl orthosilicate (TEOS).
Above-described embodiment formed imaging sensor include：Semiconductor substrate 210；Photodiode 220 is located at described half
In conductor substrate 210, and 220 discrete arrangement of the photodiode, and 220 upper surface of the photodiode is partly led with described
210 surface of body substrate flushes；Deep trench isolation structure 230 is located in the semiconductor substrate 210, for each light to be isolated
Electric diode 220, and the depth of the deep trench isolation structure 230 is deeper than the photodiode 220；Interlayer dielectric layer 240,
Positioned at 210 surface of the semiconductor substrate, and the interlayer dielectric layer 240 covers the photodiode 220 and the zanjon
Recess isolating structure 230；Metal grate 270a, it is discrete to be arranged on the interlayer dielectric layer 240；Insulating layer 260 is located at the gold
Belong to the bottom of grid 270a and wherein in one side wall, and the insulating layer 260 positioned at the bottoms the metal grate 270a is located at
240 surface of the interlayer dielectric layer；Protective layer 280, positioned at the metal grate 270a top and with the insulating layer 260
On another side wall of the opposite metal grate, the protective layer 280 to protect the top of the metal grate 270a, with
And prevent metal layer from diffusing into imaging sensor, to generate dark current or white point；Passivation layer 290 is located at the interlayer
On dielectric layer 240, and the passivation layer 290 covers the protective layer 280, the metal grate 270a and the insulating layer 260.
Completely imaging sensor further includes：Filter layer, between the metal grate 270a；Lens jacket is located at institute
State filter layer.
Although the present invention discloses as above in a preferred embodiment thereof, it is not for limiting the present invention, any ability
Field technique personnel without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this
Inventive technique scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to this hair
Bright technical spirit belongs to the technology of the present invention to any simple modifications, equivalents, and modifications made by embodiment of above
The protection domain of scheme.
Claims (10)
1. a kind of forming method of imaging sensor, which is characterized in that including：
Semiconductor substrate is provided；
Discrete photodiode and deep trench isolation structure, the deep trench isolation structure are formed in the semiconductor substrate
Between the photodiode；
Interlayer dielectric layer is formed in the semiconductor substrate surface, and the interlayer dielectric layer covers the photodiode and described
Deep trench isolation structure；
Amorphous carbon layer is formed on the interlayer dielectric layer；
The amorphous carbon layer is etched to the inter-level dielectric layer surface is exposed, forms groove；
Insulating layer is formed in the agraphitic carbon layer surface, recess sidewall and bottom；
Metal layer is formed in the surface of insulating layer；
The metal layer and the insulating layer are etched to the inter-level dielectric layer surface is exposed, forms the metal gate of discrete arrangement
Lattice；
Remove the amorphous carbon layer.
2. the forming method of imaging sensor as described in claim 1, which is characterized in that the material of the metal layer be tungsten or
Aluminium, the technique for forming the metal layer are chemical vapour deposition technique or physical vaporous deposition.
3. the forming method of imaging sensor as described in claim 1, which is characterized in that the technique for forming the interlayer dielectric layer
For chemical vapour deposition technique.
4. the forming method of imaging sensor as claimed in claim 3, which is characterized in that the interlayer dielectric layer is single layer structure
Or laminated construction；When the interlayer dielectric layer is single layer structure, material is silicon oxide or silicon nitride；When the interlayer dielectric layer
For laminated construction when, include the silicon oxide layer positioned at the semiconductor substrate surface, be located at the silicon oxide layer surface nitridation
Silicon layer.
5. the forming method of imaging sensor as described in claim 1, which is characterized in that the material of the insulating layer is that bottom is anti-
Reflector material or silicon oxynitride, the technique for forming the insulating layer are chemical vapour deposition techniques.
6. the forming method of imaging sensor as described in claim 1, which is characterized in that the method for removing the amorphous carbon layer
For cineration technics.
7. the forming method of imaging sensor as described in claim 1, which is characterized in that after removing the amorphous carbon layer,
Further include：Passivation layer is formed on the interlayer dielectric layer, and the passivation layer covers the metal grate and the insulating layer.
8. the forming method of imaging sensor as described in claim 1, which is characterized in that form metal in the surface of insulating layer
After layer, before etching the metal layer and the insulating layer, further include：Protective layer is formed in the layer on surface of metal.
9. the forming method of imaging sensor as claimed in claim 8, which is characterized in that etch the metal layer and the insulation
Layer etches the protective layer simultaneously.
10. a kind of imaging sensor formed such as claim 1~9 any one of them method, which is characterized in that including：
Semiconductor substrate；
Photodiode is located in the semiconductor substrate, and the discrete arrangement of the photodiode；
Deep trench isolation structure is located in the semiconductor substrate, and between the photodiode；
Interlayer dielectric layer is located at the semiconductor substrate surface, and the interlayer dielectric layer covers the photodiode and institute
State deep trench isolation structure；
Metal grate, it is discrete to be arranged on the interlayer dielectric layer；
Insulating layer is located at the inter-level dielectric layer surface, and positioned at the bottom of the metal grate and wherein in one side wall.
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| CN201810181210.3A CN108470740A (en) | 2018-03-06 | 2018-03-06 | Imaging sensor and forming method thereof |
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| CN201810181210.3A CN108470740A (en) | 2018-03-06 | 2018-03-06 | Imaging sensor and forming method thereof |
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| CN109860219A (en) * | 2019-04-10 | 2019-06-07 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
| CN110010634A (en) * | 2019-02-27 | 2019-07-12 | 德淮半导体有限公司 | Isolation structure and forming method thereof, imaging sensor and its manufacturing method |
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| CN110010634A (en) * | 2019-02-27 | 2019-07-12 | 德淮半导体有限公司 | Isolation structure and forming method thereof, imaging sensor and its manufacturing method |
| CN110010634B (en) * | 2019-02-27 | 2021-07-06 | 德淮半导体有限公司 | Isolation structure and forming method thereof, image sensor and manufacturing method thereof |
| CN109860219A (en) * | 2019-04-10 | 2019-06-07 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
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| JP2023123331A (en) * | 2022-02-24 | 2023-09-05 | 采▲ぎょく▼科技股▲ふん▼有限公司 | Solid-state imaging element |
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Application publication date: 20180831 |