CN1084639A - Intelligent power cable fault flash tester - Google Patents
Intelligent power cable fault flash tester Download PDFInfo
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- CN1084639A CN1084639A CN 92110989 CN92110989A CN1084639A CN 1084639 A CN1084639 A CN 1084639A CN 92110989 CN92110989 CN 92110989 CN 92110989 A CN92110989 A CN 92110989A CN 1084639 A CN1084639 A CN 1084639A
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Abstract
The present invention is a kind of power cable fault method of testing, is again a kind of testing tool.It is by adopting microprocessing to realize collection and processing to information changing the method testing power cable fault with the test of storage oscillatron record, make power cable and telecommunication cable fault test intellectuality, robotization, improved measuring accuracy.Realize that gordian technique of the present invention is to have adopted high frequency sampling of 30MHz and Storage Techniques, has finished the processing and the demonstration of high speed and high pressure single transient signal.The present invention also has operation Hanzify and printing function, so simple to operate, easy to use.
Description
The present invention relates to a kind of testing tool of power cable fault.
At present both at home and abroad the method for low-resistance, high resistant flashover and the leaks fault of testing power cable all can adopt inductance to dash the sudden strain of a muscle method, directly dodge method, terminal flashover method and Low Voltage Impulse Method.But the difference that the information processing method is existed essence.As the domestic DGC-711 type flash tester of having popularized is exactly the transient pulse information that produces on the cable when writing down test with the storage oscillatron, and shows the original analog without any processing.Because the simulating signal of storing the oscillatron record is after showing the several seconds on the screen, just the background that is become clear gradually on the oscillatron is flooded, so can't continue to observe and interpretation.Observe as if continuing, the flashover that must add high pressure again, and the waveform that each flashover obtains can not overlap fully, brings very big difficulty for observation and interpretation.In addition, in test during long distance fault, owing to echoed signal a little less than, the reflection echo waveform seriously distorts, the waveform flex point slyness of interpretation adds apart from electrograving degree very dense again, so more increase the interpretation difficulty, causes bigger reading error, even above 100 meters.In order to address this problem, begin to adopt the method for computer-aided analysis cable fault abroad, as EEA1989Vol92no1093,473, what 81.30BPower Cables 6565 articles were said is exactly this.But the intelligent electric power cable fault checkout equipment that does not still have moulding up to now.
The objective of the invention is to change the information processing method of existing power cable fault flash tester, get rid of the storage oscillatron record test of existing equipment, adopt microprocessing to realize to information processing, promptly just can be after a flashover sampling monitoring the stable test waveform that clearly shows on the screen, so that accurate interpretation fault; Further purpose of the present invention is that to make with CPU be the center, is the intelligent monolithic devices power cable fault signal Processing detecting instrument that peripheral hardware constitutes with read-only memory, random memory and other specific function.
Realize that technical scheme of the present invention is to have developed conversion of 30MHz high-speed a/d and high speed Storage Techniques, and data processing and Real-Time Display Software.Wherein the 30MHzA/D chip has been selected the ultra-large integrated chip of flash-mode A/D for use, and designs a cover control circuit and a memory board according to its sequential relationship.For high-speed a/d conversion and memory board can normally be worked accurately, the method for employing is:
1, the signal that the 90MHz crystal oscillator is produced becomes the 30MHz signal that dutycycle is about 1: 3 behind three frequency division.Its high level " 1 " is 10ns, and low level " 0 " is 23ns, satisfies the requirement of the sampling pulse clock signal of flash-mode A/D.
2, open the pulse of 30MHz sampling clock under the triggering that is controlled at flashover signal of starting or stopping control circuit, this starting or stopping control circuit is guaranteed the complete output of pulse under the situation of asynchronous triggering.
3, sampling pulse CLOK signal is added on the CLK input end of high-speed a/d, and the while also is added on the CLK end with data latches 74F374, finishes the digital signal that latchs the output of high-speed a/d transducer, and this signal data bus direct and high-speed RAM joins.
4, sampling pulse CLOK signal through the two-stage door the time delay, be added on the CP end of address counter 74F161, time clock as the high speed address counter, simultaneously also as the WR write signal of high-speed memory RAM, address counter sends writing address signal and write signal during finishing high-speed a/d transducer stable output signal, and the result that assurance goes out the conversion of high-speed a/d transducer correctly deposits among the high-speed memory.
Realize technical scheme of the present invention except that complete machine must be equipped with certain hardware guarantees, also must have a cover multiple functional, control software support flexibly, the software program of native system mainly contains: the data acquisition signal handling procedure; Double vernier control automatic range program; The CRT graphic display program; Character reminding operation and 12 kinds of characteristic fault waveform library programs; Electric wave tests the speed, medium is selected, frequency is selected man-machine exchanger; Graphic printing, report program.
Intelligent power cable fault flash tester of the present invention mainly is made up of the peripheral hardware (display, printer, keyboard special) of CPU microprocessor CPU and ROM, RAM and various I/O interfacing equipment (display interface, printer interface, keyboard interface, high-speed a/d interface) and typing, the high-speed a/d interface is mainly finished the high speed acquisition and the storage of data, is feature of the present invention place.
Accompanying drawing drawing of the present invention is described as follows:
Fig. 1 is the intelligent power cable fault flash tester schematic diagram.
Fig. 2 is the high-speed data acquisition timing diagram.
Fig. 3 is high-speed a/d and memory board.
Fig. 4 is the software flow pattern of system, wherein:
Fig. 4 a is the system monitoring software process flow diagram;
Fig. 4 b is the system break service routine.
Now in conjunction with the accompanying drawings-embodiments of the invention are described further invention.
Flash tester schematic diagram shown in Figure 1 is a single transient signal processor, observe flashover signal in real time without distortion, and the gordian technique of complete machine hardware is conversion of 30MHz high-speed a/d and high speed Storage Techniques.After the power-on reset system initialization, computing machine is in waiting status, in case several ten thousand volts of high pressure discharge moment through sphere gap, start the work of high-speed a/d transducer, simultaneously by the order of distance quantifying unit successively with the deposit data of being adopted in the cache memory of 2k byte, send interrupt request to CPU when having adopted 2048 range units, CPU response interrupts taking away the data in the cache memory, with the peripheral hardware that reaches high-speed cruising and the speeds match between the master processor.Be sent on the CRT graphic alphanumeric display after the data processing that CPU will adopt is handled and show intuitively.
Fig. 2 is the high-speed data acquisition timing diagram.Be example with the highest sample frequency 30MHz now, the level"1" of sampling pulse CLK signal is 10ns, and level "0" is 23ns.A/D converter begins to change at the rising edge of this pulse, and effective in the negative edge A/D of this pulse translation data, meanwhile the high-speed memory address is effective, and data stabilization is sent the memory write signal constantly.Finished high-speed a/d conversion and storage in time at of short duration 33ns, the result of analog-digital conversion has correctly been write in the memory.
In Fig. 3 high-speed a/d and memory board, by BG
1, R
1, R
2, C
1, C
2, 90MHz crystal and U
16The king oscillator of forming produces the 90MHz pulse signal, and this signal is through U
17, U
18It is 10ns that formation three frequency division circuit produces level"1", and level "0" is the standard sample clock signal of 23ns.The signal of 30MHz is selected different sample frequency through the sampling pulse of the different frequency of two divided-frequency, three frequency division, two divided-frequency generation 15MHz, 10MHz, 5MHz when the fault of test different distance.The data of A/D transducer output correctly to be left in the cache memory of 2k byte, must design one overlap the close-fitting control circuit of sequential relationship, U after the power-on reset
13, U
14, U
15Address counter is in closed condition, and at this moment sampling pulse can not be added to the CP end of address counter, only under the triggering of flashover signal, and U
27, U
28, U
29, U
30, U
31, U
32, U
33, U
34Start sampling pulse door U
26Open.The A/D transducer begins conversion, and address counter is counted simultaneously, stores write signal accordingly by U
21U is provided
23Control is passed through U with the address of high speed address counter
10, U
11, U
12Receive U
4, U
5, U
6, U
7On the high-speed memory address wire.When adopting enough 2048 data, U
34Produce and judge signal, cut off sampling pulse CLK signal; U
23Control is passed through U with the address bus of memory
10, U
11, U
12The address switcher of forming is transferred on the address bus of CPU, and makes memory be in read states, U
24, U
25Produce interrupt request singal INT notice CPU and take data away.U
1, U
8, U
9Form bus buffer, finish data bus and the address bus buffering buffer action of CPU.U
2, U
3Be high-speed a/d transducer and data latches, finish that outside input flashover echoed signal is converted to digital signal, after latching under the sampling clock effect, be convenient to be stored among the RAM.U
20, U
22The component frequency selector switch can be according to the requirement of range finding, and CPU gives an order and selects the different art frequencies of adopting.U among the figure
4, U
5, U
6, U
7The buffer storage of forming the 2k byte, it adopts than the 2148-H chip of low speed forms, and its visit cycle of depositing is 45ns, and the sampling rate that reach 33ns is a little also low.In order to use the work of finishing higher rate than the memory of low velocity, the present invention adopts the memory alternate mode of two 1k bytes, and promptly parity bytes is deposited respectively, and the CPU reading of data also reads by parity bytes.
The course of work of Fig. 4 a system monitoring software flow process is: after electricity applying system resets, the system stack pointer at first is set, treat that stack pointer is 1FE7H behind the system initialization, then display controller CRTC is carried out initialization, according to display mode, show that standard carries out preset parameter.Then be that host computer system is carried out the self check self-correcting, if having fault on display, promptly occur prompt "! ", if there is not fault then to show: caption content such as " welcoming to use the DGC intelligent power cable fault flash tester ".At this moment again to keyboard interface, printer interface initialization.The keyboard interface initialization is mainly seeks key interpretation value and prepares.The printer interface initialization is mainly between main frame and the printer exchange of information communication and gets in touch.Be exactly that systematic parameter presets again, as some constant variable buffer units, definition interrupt vector table address is opened interruption backward.Finish after the above preliminary work, on CRT monitor, demonstrate coordinate (range of a signal is 0 meter temporarily below time shaft for time shaft x, amplitude axis y), vernier and preset various parameters that (how many megahertzes as sample frequency is; Cable dielectric is any character, if not four kinds of dielectrics that preset in the present invention such as oil-paper medium commonly used, cross-linked ethylene cable, non-drain cable, all-plastic cable, all right free medium, and the speed of setting radio wave propagation.After aforesaid operations was finished, system enters sought keyboard, if having key to press according to the result of keyboard scan, then reads key assignments, entered corresponding handling procedure through the decoding of key door.Here mainly contain that sample waveform shows, vernier moves, six module subroutines such as medium is selected, sample frequency is selected, reference waveform shows, printing.
Fig. 4 b shown data sampling finish after interrupt service routine.
It is technical that the present invention is that the microprocessing with the advanced person is used for cable fault detect, realized power cable and telecommunication cable fault test intellectuality, robotization, and measuring accuracy is improved greatly.The processing and the demonstration of high speed and high pressure single transient signal have been finished with high frequency sampling of 30MHz and Storage Techniques.The all operations Hanzify, and have printing function, so simple to operate, easy to use.
Claims (4)
1, a kind of method of carrying out the power cable fault test with microprocessing is characterized in that having adopted conversion of 30MHz high-speed a/d and high speed Storage Techniques, and data processing and Real-Time Display Software, and the pass of 30MHzA/D conversion and memory board operate as normal is:
A, the signal that the 90MHz crystal oscillator is produced become the 30MHz signal that dutycycle is about 1: 3 behind three frequency division, its high level " 1 " is 10ns, and low level is 23ns, satisfies the requirement of the sampled clock signal of high-speed a/d converter;
B, open the pulse of 30MHz sampling clock under the triggering that is controlled at flashover signal of starting or stopping control circuit, this starting or stopping control circuit is guaranteed the complete output of pulse under the situation of asynchronous triggering;
C, sampling pulse CLOK signal are added on the CLK input end of high-speed a/d, also are added on the CLK end of data latches 74F374 simultaneously, finish the digital signal that latchs the output of high-speed a/d transducer, and this signal data bus direct and high-speed RAM joins;
D, sampling pulse CLOK signal through the two-stage door the time delay, be added on the CP end of address counter 74F161, time clock as the high speed address counter, simultaneously also as the WR write signal of high-speed memory RAM, address counter sends writing address signal and write signal during finishing high-speed a/d transducer stable output signal, and high-speed a/d transducer transformation results is left in the high-speed memory.
2, a kind of power cable fault flash tester is characterized in that flash tester mainly is made up of typing peripheral hardwares such as I/O interfacing equipments such as CPU microprocessor CPU and ROM, RAM and demonstration, printing, keyboard, high-speed a/d and display, printer, keyboard specials.
3, method of testing according to claim 1 is characterized in that data processing and Real-Time Display Software comprise that mainly the main flow of system monitoring software and waveform show, vernier moves, six module subroutines such as medium is selected, sample frequency is selected, reference waveform shows, printing.
4, flash tester according to claim 2 is characterized in that the high-speed a/d chip selected the ultra-large integrated chip of flash-mode for use, and is equipped with memory board and the control circuit that designs with this chip sequential relationship.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 92110989 CN1030546C (en) | 1992-09-20 | 1992-09-20 | Intelligent power cable fault flash tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 92110989 CN1030546C (en) | 1992-09-20 | 1992-09-20 | Intelligent power cable fault flash tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1084639A true CN1084639A (en) | 1994-03-30 |
| CN1030546C CN1030546C (en) | 1995-12-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 92110989 Expired - Fee Related CN1030546C (en) | 1992-09-20 | 1992-09-20 | Intelligent power cable fault flash tester |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1030546C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1038276C (en) * | 1993-05-07 | 1998-05-06 | 韩伯锋 | High-intelligent cable fault scintillation detector |
| CN100538380C (en) * | 2006-03-16 | 2009-09-09 | 重庆大学 | Based on the online distance-finding method of the cable fault of artificial nerve network model |
| CN103531059A (en) * | 2013-09-10 | 2014-01-22 | 国家电网公司 | Teaching tool for testing faults of power cable |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100410675C (en) * | 2005-02-03 | 2008-08-13 | 淄博博鸿电气有限公司 | Power cable damage synchronous magnetic field directioning positioning method |
-
1992
- 1992-09-20 CN CN 92110989 patent/CN1030546C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1038276C (en) * | 1993-05-07 | 1998-05-06 | 韩伯锋 | High-intelligent cable fault scintillation detector |
| CN100538380C (en) * | 2006-03-16 | 2009-09-09 | 重庆大学 | Based on the online distance-finding method of the cable fault of artificial nerve network model |
| CN103531059A (en) * | 2013-09-10 | 2014-01-22 | 国家电网公司 | Teaching tool for testing faults of power cable |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1030546C (en) | 1995-12-20 |
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