CN108461514A - The isolation structure and forming method thereof of CMOS image sensors - Google Patents
The isolation structure and forming method thereof of CMOS image sensors Download PDFInfo
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- CN108461514A CN108461514A CN201810262371.5A CN201810262371A CN108461514A CN 108461514 A CN108461514 A CN 108461514A CN 201810262371 A CN201810262371 A CN 201810262371A CN 108461514 A CN108461514 A CN 108461514A
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- 238000002955 isolation Methods 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 27
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000000926 separation method Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 description 15
- 230000000873 masking effect Effects 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000010276 construction Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 208000027418 Wounds and injury Diseases 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Abstract
The present invention relates to a kind of isolation structures of cmos image sensor and forming method thereof, and this method includes：Semiconductor substrate is provided, the semiconductor substrate includes logic region, is used to form the logic circuit of CMOS image sensors；Insulating buried layer is formed in the logic region of the semiconductor substrate；The logic region for etching the semiconductor substrate, forms the first isolated groove in the logic region, and first isolated groove is located at the top of the insulating buried layer.The performance of CMOS image sensors can be improved by forming isolation structure using the above method.
Description
Technical field
The present invention relates to the isolation structure of CMOS image sensors field more particularly to a kind of CMOS image sensors and its
Forming method.
Background technology
Cmos image sensor is during forming trench isolations at present, due to the logic region (Logic) and pixel
(Pixel) demand of the region to trench isolations depth is different, need to be etched with two steps to be carried out to Logic region trenches isolation depth
It adjusts.Specifically, etching forms groove and then has been formed to the regions Logic simultaneously on the regions Logic and the regions Pixel
Groove, further perform etching so that the gash depth in the regions Logic increases.
This method can form prodigious difference in height in the regions Logic and the regions Pixel, be generated to subsequent CMP process
Prodigious burden.Meanwhile this multiple etching processing procedure is complicated, easily causes to damage to substrate during secondarily etched, influences most
The performance of whole CMOS image sensors.
Therefore, it is necessary to a kind of isolation structures of new CMOS image sensors to improve the performance of CMOS image sensors.
Invention content
The technical problem to be solved by the invention is to provide a kind of isolation structure of CMOS image sensors and its formation sides
Method, to improve the performance of CMOS image sensors.
To solve the above-mentioned problems, the present invention provides a kind of forming method of the isolation structure of CMOS image sensors,
Including：Semiconductor substrate is provided, the semiconductor substrate includes logic region, is used to form the logic electricity of CMOS image sensors
Road；Insulating buried layer is formed in the logic region of the semiconductor substrate；The logic region for etching the semiconductor substrate, in institute
It states and forms the first isolated groove in logic region, first isolated groove is located at the top of the insulating buried layer.
Optionally, first isolated groove exposes the part insulating buried layer or first isolated groove bottom
There is spacing with the insulating buried layer surface.
Optionally, the semiconductor substrate further includes pixel region, is used to form the pixel sensing of CMOS image sensors
Unit；While etching the logic region of the semiconductor substrate, the pixel region is etched, the shape in the pixel region
At the second isolated groove, the depth of second isolated groove is consistent with the depth of the first isolated groove.
Optionally, the depth bounds of the insulating buried layer are 50nm~1000nm, and thickness range is 100nm~1000nm.
Optionally, the insulating buried layer is the stacking knot of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer
Structure.
Optionally, the insulating buried layer is formed using ion implantation technology.
Optionally, further include filling separation layer in first isolated groove and the second isolated groove.
Technical scheme of the present invention also provides a kind of isolation structure of CMOS image sensors, including：Insulating buried layer is located at
In logic region in semiconductor substrate, the logic region is used to form the logic circuit of CMOS image sensors；Positioned at institute
The first isolated groove in logic region is stated, first isolated groove is located above the insulating buried layer.
Optionally, first isolated groove exposes the part insulating buried layer or first isolated groove bottom
There is spacing with the insulating buried layer surface.
Optionally, semiconductor substrate further includes pixel region, is used to form the pixel sensor cell of CMOS image sensors；
The isolation structure further includes：The second isolated groove in the pixel region, the depth of second isolated groove with
The depth of first isolated groove is consistent.
Optionally, the depth bounds of the insulating buried layer are 50nm~1000nm, and thickness range is 100nm~1000nm.
Optionally, the insulating buried layer is the stacking knot of silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer
Structure.
Optionally, further include the separation layer filled in first isolated groove and the second isolated groove.
The isolation structure forming method of the CMOS image sensors of the present invention is formed in the logic region of semiconductor substrate
Insulating buried layer and then the first isolated groove is formed on the insulating buried layer, can improve isolation effect.The insulating buried layer
It can to form fully- depleted or part depletion in the MOS transistor subsequently formed on logic region, electric leakage and work(can be reduced
Consumption, to improve the performance of cmos image sensor.
Further, semiconductor substrate includes simultaneously logic region and pixel region, forms insulation in logic region and buries
After layer, while the first isolated groove is formed in logic region, the second isolated groove is formed in pixel region.Due to described
Logic region has insulating buried layer, to improve isolation effect.The insulating buried layer can subsequently to be formed on logic region
MOS transistor in form fully- depleted or part depletion, electric leakage and power consumption can be reduced, to improve cmos image sensor
Performance.The depth by the first isolated groove in multiple etching technique adjustment logic region is no longer needed to, is carved so as to reduce
Deteriorate wound, reduces cost.
Description of the drawings
Fig. 1 to Fig. 5 is the forming process of the isolation structure of the CMOS image sensors of a specific mode of the invention
Structural schematic diagram；
Fig. 6 to Figure 10 is the forming process of the isolation structure of the CMOS image sensors of a specific mode of the invention
Structural schematic diagram.
Specific implementation mode
Below in conjunction with the accompanying drawings to the specific of the isolation structure of CMOS image sensors provided by the invention and forming method thereof
Embodiment elaborates.
Fig. 1 to Fig. 5 is the forming process of the isolation structure of the CMOS image sensors of a specific mode of the invention
Structural schematic diagram.
Referring to FIG. 1, providing semiconductor substrate, the semiconductor substrate includes logic region 100, is used to form CMOS figures
The logic circuit of shape sensor.
The semiconductor substrate can be monocrystalline substrate, Ge substrates, SiGe substrate etc..It is described in specific implementation mode
Semiconductor substrate is the monocrystalline substrate of p-type doping.In other specific described modes of the present invention, the semiconductor substrate is also
Can be other doping types.The logic region 100 that semiconductor substrate is illustrated only in Fig. 1, subsequently in the logic region 100
The upper logic circuit for forming CMOS image sensors.
Referring to FIG. 2, forming insulating buried layer 101 in the logic region 100 of the semiconductor substrate.
The material of the insulating buried layer 101 can be the stacking of silica, silicon nitride or silicon oxide layer and silicon nitride layer
Structure.According to the requirement of the isolation effect of specific device, the insulating buried layer 101 can also be other insulating materials and insulation material
The combination of material.
In the specific implementation mode of the present invention, the insulating buried layer 101 can be formed by ion implantation technology.This is specific
In embodiment, the material of the insulating buried layer 101 is silica, by carrying out O +ion implanted to the logic region 100
The silicon oxide insulation buried layer 101 is formed, and is made annealing treatment after ion implantation, with activation injection ion and is reduced
Due to defect caused by ion implanting in the logic region 100.
The depth of the insulating buried layer 101 is configured according to the depth of follow-up first isolated groove to be formed so that
The insulating buried layer 101 is located at the lower section of follow-up first isolated groove to be formed.
In the specific mode of the present invention, the depth bounds of the insulating buried layer 101 can be 50nm~1000nm,
The thickness range of the insulating buried layer 101 is 100nm~1000nm.
Since the dielectric coefficient of different insulating materials is different, in the specific mode, different materials can be directed to
Different depth and thickness is arranged in insulating buried layer 101.
When the material of the insulating buried layer 101 is silica, the depth of the insulating buried layer 101 is 50nm~1000nm,
Thickness is 100nm~1000nm；Use the dosage of O +ion implanted for 1E16/cm2~5E18/cm2, energy be 100KeV~
250KeV, annealing time are 0.5h~6h, and temperature is 600 DEG C~1350 DEG C.
When the material of the insulating buried layer 101 is silicon nitride, the depth of the insulating buried layer 101 is 100nm~800nm,
Thickness is 200nm~800nm；Use the dosage of N~+ implantation for 1E15/cm2~1E18/cm2, energy be 100KeV~
230KeV, annealing time are 0.5h~6h, and temperature is 800 DEG C~1300 DEG C.
The insulating buried layer 101 can also include the silicon nitride layer on oxide sublayer and oxide sublayer surface, at this time
The depth of oxide sublayer is 300nm~800nm, and the depth of silicon nitride sublayer is 100nm~300nm；Sequentially form the oxygen
SiClx sublayer and silicon nitride sublayer.Specifically, when forming oxide sublayer, use the dosage of O +ion implanted for 1E16/cm2~
5E18/cm2, energy is 100KeV~250KeV, and the annealing time is 0.5h~6h, and temperature is 600 DEG C~1350 DEG C；It is formed
When silicon nitride sublayer, use the dosage of N~+ implantation for 1E15/cm2~1E18/cm2, energy is 100KeV~230KeV, is moved back
Fiery processing time is 0.5h~6h, and temperature is 800 DEG C~1300 DEG C.In other specific described modes, the insulating buried layer 101
May include the oxide sublayer and silicon nitride sublayer of multiple stacked spaced aparts.
Referring to FIG. 3, forming Patterned masking layer 110, the Patterned masking layer tool on 100 surface of the logic region
There is opening 113, exposes the surface of the part logic region 100.
The Patterned masking layer 110 includes silicon oxide layer 111 and the silicon nitride layer positioned at the silicon oxide layer surface
112.In other specific implementation modes of the present invention, the Patterned masking layer 110 can also use other mask materials,
This is not construed as limiting；110 surface of the Patterned masking layer can also have graphical photoresist layer.Specifically, described graphical
The forming method of mask layer 110 is included in 100 surface of the logic region and is formed after mask layer, in the mask material
Layer surface forms photoresist layer, and carries out photoetching, etching processing to the photoresist layer, forms graphical photoresist layer；Then
Using the graphical photoresist layer as mask, the mask layer is etched, forms the opening 113.
The opening 113 defines position, shape and the size of follow-up first isolated groove to be formed.
Referring to FIG. 4, along the logic region 100 of the 113 etching semiconductor substrate of the opening, in the logic region
The first isolated groove 102 is formed in 100, first isolated groove 102 is located at 101 top of the insulating buried layer.
The logic region 100 is performed etching using anisotropic dry etch process.In the specific mode,
Using the insulating buried layer 101 as etching stop layer so that 102 bottom-exposed of the first isolated groove of formation goes out the insulation and buries
The part surface of layer 101.In other specific implementation modes, first isolated groove 102 can be adjusted by etch period
Depth so that first isolated groove 102 is located at the top of insulating buried layer 101, first isolated groove 102 and insulation
Have between buried layer 101 at regular intervals.
In the specific implementation mode, first isolated groove 102 is shallow trench, is used to form fleet plough groove isolation structure
(STI), in other specific described modes of the present invention, first isolated groove 102 can also be deep trench.
Referring to FIG. 5, filling separation layer in first isolated groove 102, groove isolation construction 103 is formed.
The material of the separation layer can be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride or silicon oxide carbide.
Chemical vapor deposition method, atom layer deposition process or spin coating proceeding etc. may be used to fill out in first isolated groove 102
Insulating dielectric materials are filled, and the insulating dielectric materials are planarized, while removing the graphical hard mask layer 110,
Form the groove isolation construction 104.In other specific described modes, the figure can also be retained according to actual demand
Change hard mask layer 110, is not limited thereto.
104 bottom of groove isolation construction on the logic region 100 is insulating buried layer 101, improves isolation depth, from
And improve isolation effect.In the specific mode, the groove isolation construction 104 is connect with the surface of insulating buried layer 101, meeting
So that forming fully- depleted in the MOS transistor subsequently formed on logic region 100, electric leakage and power consumption can be reduced, to carry
The performance of high cmos image sensor.In other specific described modes, the groove isolation construction 104 and insulating buried layer 101
Between also have at regular intervals, can to form part depletion in the MOS transistor subsequently formed on logic region 100, together
Sample can reduce electric leakage and power consumption, improve the performance of cmos image sensor.
Fig. 6 to Figure 10 is please referred to, for another specifically isolation structure of the CMOS image sensors of the mode of the present invention
The structural schematic diagram of forming process.
Referring to FIG. 6, providing semiconductor substrate, the semiconductor substrate includes logic region 201 and pixel region 202.
The logic region 201 is used to form the logic circuit of CMOS image sensors；The pixel region 202 is used for shape
At the pixel sensor cell of CMOS image sensors.
By the 202 adjacent presentation of the logic region 201 and pixel region in Fig. 6, wherein being distinguished with dotted line.Actual half
On conductor substrate, between the logic region 201 and pixel region 202 can also between be separated with other regions or the logic
Between region 201 and pixel region 202 there is isolation structure to be isolated, is not shown herein.The logic region 201 and picture
The relative position in plain region 202, is not construed as limiting.
Referring to FIG. 7, forming insulating buried layer 203 in the logic region 201 of the semiconductor substrate.
By ion implantation technology, insulating buried layer 203 is formed in the logic region 201.
Specifically, the mask layer for exposing logic region 201 can be formed on the semiconductor substrate, then with described
Mask layer is that mask carries out ion implanting to the logic region 201, is formed at the certain depth of the logic region 201 absolutely
Edge buried layer 203.After ion implantation, it can also anneal, to activate injection ion, eliminate implant damage.
The insulating buried layer 203 can be the insulation such as the stacked structure of silica, silicon nitride or silica and silicon nitride
Dielectric layer.
Referring to FIG. 8, Patterned masking layer 210 is formed in the logic region 201 and 202 surface of pixel region, it is described
Patterned masking layer has opening 213, exposes the surface of the part logic region 201 and pixel region 202.
The opening 213 define the position of follow-up first isolated groove and the second isolated groove to be formed, shape and
Size.Be open in the specific mode, on the logic region 201 and pixel region 202 213 be of the same size and
Shape.In other specific described modes, different open can also be formed on the logic region 201 and pixel region 202
Mouthful.
The Patterned masking layer 210 includes silicon oxide layer 211 and the silicon nitride layer positioned at 211 surface of the silicon oxide layer
212.In other specific described modes of the present invention, the Patterned masking layer 210 can also use other mask materials.
Referring to FIG. 9, along 213 etching of the opening logic region 201 and pixel region 202, in the logic area
The first isolated groove 204 is formed in domain 201, and the second isolated groove 205 is formed in the pixel region 202.
The logic region 201 and pixel region 202 are etched using anisotropic dry etch process simultaneously so that formed
Second isolated groove 205 depth it is consistent with the depth of first isolated groove 204.But the logic region
201 and when pixel region 202, using the insulating buried layer 203 in the logic region 201 as etching stop layer so that described to patrol
The bottom for collecting the first isolated groove 204 formed in region 201 is located on the insulating buried layer 203, and it is described absolutely to expose part
The surface of edge buried layer 203.In other specific implementation modes, first isolating trenches can also be controlled by adjusting etch period
The depth of slot 204 and the second isolated groove 205 so that first isolated groove 204 is located at the top of insulating buried layer 203, institute
State have between the first isolated groove 204 and insulating buried layer 203 it is at regular intervals.
Referring to FIG. 10, separation layer is filled in first isolated groove, 204 and second isolated groove 205, described
First groove isolation structure 206 is formed in logic region 201, and second groove isolation structure is formed in the pixel region 202
207。
The material of the separation layer can be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride or silicon oxide carbide.
Chemical vapor deposition method, atom layer deposition process or spin coating proceeding etc. may be used in first isolated groove 204 and
Insulating dielectric materials are filled in two isolated grooves 205, and the insulating dielectric materials are planarized, while removing the figure
Shape hard mask layer 210 forms the first groove isolation structure 206 and second groove isolation structure 207.In other specific institutes
It states in mode, can also retain the graphical hard mask layer 210 according to actual demand, be not limited thereto.
First groove isolation structure 206 in the logic region 201 and the second groove isolation junction in pixel region 202
The depth of structure 207 is identical, but since 206 bottom of first groove isolation structure in the logic region 201 is insulating buried layer
203, isolation effect can be improved.Also, after the insulating buried layer 203 can make when being contacted with first groove isolation structure 206
Continue and forms fully- depleted in the MOS transistor formed on logic region 201, the insulating buried layer 203 and first groove isolation junction
It can make that part is formed in the MOS transistor subsequently formed on logic region 201 to be consumed when having at regular intervals between structure 206
To the greatest extent, electric leakage and power consumption can be reduced, to improve the performance of cmos image sensor.It no longer needs to through multiple etching technique adjustment
The depth of groove isolation construction in logic region reduces cost so as to reduce etching injury.
The specific implementation mode of the present invention also provides a kind of isolation structure of CMOS image sensors.
Referring to FIG. 5, in a specific embodiment, the isolation structure of the CMOS image sensors includes：It is located at
Insulating buried layer 101 in the logic region 100 of semiconductor substrate；The first isolated groove in the logic region 100, institute
It states the first isolated groove and is located at 101 top of the insulating buried layer, expose SI semi-insulation buried layer 101；First isolated groove
It is interior to be filled with separation layer, the first groove isolation structure 103 as 101 top of insulating buried layer.In other specific described modes,
First isolated groove is located at 101 top of the insulating buried layer, has between the insulating buried layer 101 at regular intervals.
The material of the insulating buried layer 101 can be the stacking of silica, silicon nitride or silicon oxide layer and silicon nitride layer
Structure.The depth bounds of the insulating buried layer 101 can be 50nm~1000nm, and the thickness range of the insulating buried layer 101 is
100nm~1000nm.
Since the dielectric coefficient of different insulating materials is different, in the specific mode, different materials can be directed to
Different depth and thickness is arranged in insulating buried layer 101.When the material of the insulating buried layer 101 is silica, the insulating buried layer
101 depth is 50nm~1000nm, and thickness is 100nm~1000nm；When the material of the insulating buried layer 101 is silicon nitride,
The depth of the insulating buried layer 101 is 100nm~800nm, and thickness is 200nm~800nm；The insulating buried layer 101 can be with
Silicon nitride layer including oxide sublayer and oxide sublayer surface, at this time the depth of oxide sublayer be 300nm~
The depth of 800nm, silicon nitride sublayer are 100nm~300nm.
Referring to FIG. 6, the structure for the isolation structure of the CMOS image sensors of another specific implementation mode of the present invention is shown
It is intended to.
The isolation structure includes the insulating buried layer 203 in the logic region 201 of semiconductor substrate, the semiconductor
Substrate further includes pixel region 202.
The isolation structure further includes：The first isolated groove in the logic region 201, and it is located at the picture
The second isolated groove in plain region 202, first isolated groove bottom are located at 203 surface of the insulating buried layer, expose
The surface of SI semi-insulation buried layer 203.The depth of first isolated groove is consistent with the depth of the second isolated groove.At it
In his the specific mode, first isolated groove bottom may be located on 203 top of the insulating buried layer and with it is described absolutely
Have between edge buried layer 203 at regular intervals.
The isolation structure further includes：First groove isolation structure 206 in first isolated groove and it is located at
Second groove isolation structure 207 in second isolated groove.
First groove isolation structure 206 in the logic region 201 and the second groove isolation junction in pixel region 202
The height of structure 207 is identical, but since the first groove isolation structure 206 in the logic region 201 is located at insulating buried layer 203
Top can improve isolation effect.The first groove isolation structure 206 is connect with 203 surface of insulating buried layer, can be made follow-up
Fully- depleted is formed in the MOS transistor formed on logic region 201；Alternatively, the first groove isolation structure 206 and insulation
Have between buried layer 203 it is at regular intervals, can make in the MOS transistor subsequently formed on logic region 201 formed part consume
To the greatest extent, electric leakage and power consumption can be reduced, to improve the performance of cmos image sensor.Can be formed simultaneously the first groove every
From structure 206 and second groove isolation structure 207, no longer need to through the trench isolations in multiple etching technique adjustment logic region
The depth of structure reduces cost so as to reduce etching injury.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (13)
1. a kind of forming method of the isolation structure of CMOS image sensors, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes logic region, is used to form the logic electricity of CMOS image sensors
Road；
Insulating buried layer is formed in the logic region of the semiconductor substrate；
The logic region for etching the semiconductor substrate, forms the first isolated groove in the logic region, described first every
From the top that groove is located at the insulating buried layer.
2. the forming method of isolation structure according to claim 1, which is characterized in that first isolated groove exposes
The part insulating buried layer or first isolated groove bottom have spacing with the insulating buried layer surface.
3. the forming method of isolation structure according to claim 1, which is characterized in that the semiconductor substrate further includes picture
Plain region is used to form the pixel sensor cell of CMOS image sensors；Etching the logic region of the semiconductor substrate
Meanwhile the pixel region is etched, the second isolated groove, the depth of second isolated groove are formed in the pixel region
It is consistent with the depth of the first isolated groove.
4. the forming method of isolation structure according to claim 1, which is characterized in that the depth bounds of the insulating buried layer
For 50nm~1000nm, thickness range is 100nm~1000nm.
5. the forming method of isolation structure according to claim 1, which is characterized in that the insulating buried layer is silica
The stacked structure of layer, silicon nitride layer or silicon oxide layer and silicon nitride layer.
6. the forming method of isolation structure according to claim 1, which is characterized in that form institute using ion implantation technology
State insulating buried layer.
7. the forming method of isolation structure according to claim 3, which is characterized in that further include in first isolating trenches
Separation layer is filled in slot and the second isolated groove.
8. a kind of isolation structure of CMOS image sensors, which is characterized in that including：
Insulating buried layer is located in the logic region in semiconductor substrate, and the logic region is used to form CMOS image sensors
Logic circuit；
The first isolated groove in the logic region, first isolated groove are located above the insulating buried layer.
9. isolation structure according to claim 8, which is characterized in that it is described absolutely that first isolated groove exposes part
Edge buried layer or first isolated groove bottom have spacing with the insulating buried layer surface.
10. isolation structure according to claim 8, which is characterized in that the semiconductor substrate further includes pixel region, is used
In the pixel sensor cell for forming CMOS image sensors；The isolation structure further includes：In the pixel region
Two isolated grooves, the depth of second isolated groove are consistent with the depth of the first isolated groove.
11. isolation structure according to claim 8, which is characterized in that the depth bounds of the insulating buried layer be 50nm~
1000nm, thickness range are 100nm~1000nm.
12. isolation structure according to claim 8, which is characterized in that the insulating buried layer is silicon oxide layer, silicon nitride layer
Or the stacked structure of silicon oxide layer and silicon nitride layer.
13. isolation structure according to claim 10, which is characterized in that further include filling first isolated groove and the
Separation layer in two isolated grooves.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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