CN108459972B - Efficient cache management design method for multi-channel solid state disk - Google Patents
Efficient cache management design method for multi-channel solid state disk Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1021—Hit rate improvement
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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Abstract
The invention belongs to the field of airborne embedded computers, and relates to a high-efficiency cache management design method of a multi-channel solid state disk. The method comprises the following steps: step 1, reading a request service flow; step 2, identifying the cold and hot attributes of the write request, and determining the door card of the cold and hot request by adding a basic threshold value to the average size of the latest request; step 3, managing the internal caches of the cold data cache and the hot data cache, dynamically adjusting a write-back threshold value according to requirements, and writing back data in the idle period of the chip; and step 4, dynamically adjusting the size of the cache according to the requirements of performance and service life of the cold data cache and the hot data cache. The method utilizes different characteristics of different data updating to write back the data in the data cache in advance in the idle period of the chip of the multi-channel solid state disk, and combines the data with the dynamic adjustment between the cold data cache and the hot data cache, thereby not only ensuring the cache service capability of the multi-channel solid state disk, but also not causing great service life loss.
Description
Technical Field
The invention belongs to the field of airborne embedded computers, and relates to a high-efficiency cache management design method of a multi-channel solid state disk.
Background
With the rapid development of modern avionic systems, higher requirements are put forward on a new generation of airborne storage equipment, the traditional mechanical hard disk has inherent limitations, so that the traditional mechanical hard disk is difficult to apply under the condition of airborne loading, and the flash memory provides a new choice for the airborne storage system. Flash memory has been widely noticed as a new storage medium, and its unique advantages of low energy consumption, small size, light weight and vibration resistance make it widely used in many kinds of embedded devices. A NAND Flash based solid-state drive (SSD) has a shorter start-up time, a faster random access speed, and lower energy consumption by eliminating mechanical overhead in the disk, which makes its storage performance more superior than the disk, becomes a powerful substitute for the disk, and is more suitable for an onboard environment. Some inherent structural defects of the NAND Flash can be shielded by a Flash Translation Layer (FTL), so that the NAND Flash can be conveniently used like a conventional magnetic disk, and on the basis of the FTL, the performance and durability of the solid state disk can be further improved by using the cache.
Caching in a solid state disk plays a crucial role, firstly, caching is generally used for two parts, namely a mapping cache and a data cache, the mapping cache stores required mapping entries, and the data cache stores latest write request data; secondly, the read-write speed of the data cache is far higher than that of Flash, and the performance of the solid state disk can be remarkably improved by reading and writing through the cache; and finally, the data cache can absorb the write data which is frequently updated, and the write times of the Flash are reduced, so that the service life of the SSD is prolonged. Most of the existing cache scheduling focuses on how to select write-back data and improve the hit rate of the cache under the condition that the cache is full, but the passive write-back mode has a very unstable effect on improving the performance of the solid-state disk, and when the hit rate of a request is low, the performance improvement is very small, and the performance which the cache should have is difficult to exert.
Disclosure of Invention
The purpose of the invention is as follows:
the invention provides a cache management design method facing a multi-channel solid state disk aiming at the requirement of an airborne embedded computer on read-write performance, and the method is characterized in that the performance is remarkably improved at the cost of a small amount of service life by utilizing the characteristics of different chip idle periods and different cache data updating frequencies of the multi-channel solid state disk.
The technical scheme of the invention is as follows:
a high-efficiency cache management design method of a multi-channel solid state disk comprises the following steps:
step 1, when a read request reaches a multi-channel solid-state disk, firstly judging whether the read request hits a data cache, and if the read request hits the data cache, directly serving by the data cache. If the data cache is not hit, whether the mapping item corresponding to the data is in the mapping cache needs to be judged next, if the corresponding mapping item is not in the mapping cache, the mapping item corresponding to the data needs to be read first, and finally the target data is read; and if the corresponding mapping item is in the mapping cache, directly reading data from the corresponding position of the Flash to finish the reading operation.
And 2, determining a threshold of a large request by using a mode of adding a threshold to the average value of the sizes of the latest requests, and ensuring that the large request not only exceeds a basic value, but also exceeds the average size of the latest requests. Data that exceeds this threshold is determined to be cold data, otherwise it is considered to be hot data.
And 3, dividing the data cache into a cold data cache and a hot data cache, wherein the cold data cache and the hot data cache are respectively used for storing the obtained cold data and the hot data, when the write request reaches the multi-channel solid-state disk, firstly judging whether the data cache is hit, if so, performing cache service by the hit data cache, and if not, adding the data cache into the corresponding data cache for service according to the judged cold and hot attributes. After the service is finished, if the chip is in an idle state, writing back a certain amount of data at the tail node in the LRU linked list of the cold data cache and the hot data cache to Flash in advance according to the size of the write-back threshold.
And 4, when data is written into the data cache, if the free space of the current data cache is insufficient, the data cache seizes the free space from another data cache, so that the current data can be served by the cache.
The invention has the advantages and effects that:
the method utilizes different characteristics of different data updating to write back the data in the data cache in advance in the idle period of the chip of the multi-channel solid state disk, and combines the data with the dynamic adjustment between the cold data cache and the hot data cache, thereby not only ensuring the cache service capability of the multi-channel solid state disk, but also not causing great service life loss.
Drawings
FIG. 1 is a flow diagram of cache management.
FIG. 2 is a flow chart of the internal service of the cold and hot data cache.
Fig. 3 is a schematic diagram illustrating dynamic adjustment of a hot and cold data buffer in embodiment 1.
Detailed Description
The present invention will be described in further detail.
A cache design method for a multi-channel solid state disk, as shown in fig. 1, includes:
step 1, when a read request reaches a multi-channel solid-state disk, firstly judging whether the read request hits a data cache, and if the read request hits the data cache, directly serving by the data cache. If the data cache is not hit, whether the mapping item corresponding to the data is in the mapping cache needs to be judged next, if the corresponding mapping item is not in the mapping cache, the mapping item corresponding to the data needs to be read first, and finally the target data is read; and if the corresponding mapping item is in the mapping cache, directly reading data from the corresponding position of the Flash to finish the reading operation.
When the size of the incoming write request is judged, the relation between the judged threshold value s and the latest request is as follows:
wherein N is the inclusion currentThe number of requests including 64, n in example 1iIndicating the size of the ith request and Base indicating a basic threshold, which may be determined by counting historical data of the applied system, 32 in example 1. And substituting the size of the latest request into a formula to obtain a threshold value S, comparing the threshold value S with the size of the current request, and if the threshold value S is larger than the size of the current request, determining that the request is a large request, namely cold data, and otherwise, determining that the request is a small request and hot data.
And 3, dividing the data cache into a cold data cache and a hot data cache, wherein the cold data cache and the hot data cache are respectively used for storing the obtained cold data and the hot data, when the write request reaches the multi-channel solid-state disk, firstly judging whether the data cache is hit, if so, performing cache service by the hit data cache, and if not, adding the data cache into the corresponding data cache for service according to the judged cold and hot attributes.
The strategy adopted when the cold data cache and the hot data cache serve the data is the same, and the data nodes comprise two types, wherein a clean node indicates that the data inside the node is written back to Flash, and a dirty node indicates that the data inside the node is not written back to Flash. Next, taking the hot data cache as an example, the service policies of the cold data cache and the hot data cache are described. If the write request hits the hot data cache, further judgment on the attributes of the data node hit by the write request is needed. If the hit node is a clean node, indicating that the written-back data is excessive, subtracting a corresponding value from the write-back threshold, placing the data node at the head end of the LRU linked list, and modifying the state of the data node into a dirty node; if a dirty node is hit, the data node is placed directly at the head of the LRU linked list. If the hot data cache is missed and the write request needs to be written into the hot data cache, whether a free space exists in the hot data cache is checked, wherein the free space comprises a node which is not written with data and a clean node, if the free space exists, the data is directly written into the hot data cache, the node is promoted to the head of the LRU queue, if the free space does not exist, the free space needs to be taken from another data cache, namely a cold data cache, as shown in FIG. 3, and the write-back threshold value is correspondingly increased. After the hot data caching service is completed, when a chip in an idle state appears in the multi-channel solid state disk, writing back a certain amount of data in the cold data cache and the hot data cache LRU linked list at the tail node to Flash in advance according to the size of the write-back threshold.
And 4, the size of the cold and hot data cache in the write cache is not fixed, but can be dynamically changed along with the requirement of the cold and hot data cache on the memory, so that the balance between the speed and the service life is achieved. On the one hand, the hot data cache represents the service life of Flash, and the larger the hot data cache is, the more updating operations can be absorbed, and the longer the Flash service life is; on the other hand, the larger the cold data cache, the more likely an incoming large request will be serviced by the cache, and thus the faster.
In the hot data cache, when the hot data misses the hot data cache and there is no free space in the hot data cache, the H-DAT will take free space from the cold data cache. As shown in fig. 3(a), in embodiment 1, data 15 is to be added to the hot data cache, but no free node exists in the hot data cache, and the cold data cache deletes its own free node and adds the obtained free space to the hot data cache.
In a cold data cache, as in a hot data cache, when there is insufficient cold data cache space, space is obtained from the hot data cache. However, there are two cases:
(1) if there is free space in the hot data cache, the space in the hot data cache will be directly added to the cold data cache to serve incoming data, as shown in fig. 3 (a);
(2) if there is no free space in the hot cache and the write-back threshold WB in the cold data cache exceeds the size of the cold cache, then in order to allow future large requests to be serviced by the cache, the dirty node is deleted from the hot data cache and the data stored in the node is written back to Flash. The resulting space is added to the cold data cache to serve the incoming data, as shown in FIG. 3 (b).
Claims (2)
1. A high-efficiency cache management design method of a multi-channel solid state disk is characterized by comprising the following steps:
step 1, when a read request reaches a multi-channel solid-state disk, firstly judging whether the read request hits a data cache, and if the read request hits the data cache, directly serving by the data cache; if the data cache is not hit, whether the mapping item corresponding to the data is in the mapping cache needs to be judged next, if the corresponding mapping item is not in the mapping cache, the mapping item corresponding to the data needs to be read first, and finally the target data is read; if the corresponding mapping item is in the mapping cache, directly reading data from the corresponding position of the Flash to finish the reading operation;
step 2, determining a threshold of a large request by using a mode of adding a threshold to an average value of the size of the latest request, and ensuring that the large request not only exceeds a basic value, but also exceeds the average size of the latest request; data above this threshold is determined to be cold data, otherwise it is considered to be hot data;
step 3, dividing the data cache into a cold data cache and a hot data cache, wherein the cold data cache and the hot data cache are respectively used for storing the obtained cold data and the hot data, when a write request reaches the multi-channel solid-state disk, firstly judging whether the data cache is hit, if so, performing cache service by the hit data cache, and if not, adding the data cache into the corresponding data cache for service according to the judged cold and hot attributes; after the service is finished, if the chip is in an idle state, writing back a certain amount of data at the tail node in the LRU chain table of the cold data cache and the hot data cache to Flash in advance according to the size of the write-back threshold;
the strategy adopted when the cold data cache and the hot data cache serve the data is the same and comprises two types of data nodes, a clean node indicates that the data in the node is written back to Flash, and a dirty node indicates that the data in the node is not written back to Flash;
step 4, the size of the cold and hot data cache in the write cache is not fixed, but dynamically changes along with the requirement of the cold and hot data cache on the memory, so as to achieve the balance between speed and service life;
when data is written into a data cache, if the free space of the current data cache is insufficient, the data cache deprives the free space from another data cache, so that the current data can be served by the cache.
2. The efficient cache management design method for the multi-channel solid state disk as claimed in claim 1, wherein when the size of the incoming write request is determined, the relationship between the determined threshold s and the latest request is:
n is the number of requests including the current request, ni represents the size of the ith request, and Base represents a basic threshold, and the threshold can be determined by counting the historical data of the applied system.
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| CN109324761A (en) * | 2018-10-09 | 2019-02-12 | 郑州云海信息技术有限公司 | A kind of data cache method, device, equipment and storage medium |
| WO2021189203A1 (en) * | 2020-03-23 | 2021-09-30 | 华为技术有限公司 | Bandwidth equalization method and apparatus |
| CN112527194B (en) * | 2020-12-04 | 2024-02-13 | 北京浪潮数据技术有限公司 | Method, system and device for setting write amplification of solid state disk and readable storage medium |
| CN113342265B (en) * | 2021-05-11 | 2023-11-24 | 中天恒星(上海)科技有限公司 | Cache management method and device, processor and computer device |
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