WO2021189203A1

WO2021189203A1 - Bandwidth equalization method and apparatus

Info

Publication number: WO2021189203A1
Application number: PCT/CN2020/080729
Authority: WO
Inventors: 王锦
Original assignee: 华为技术有限公司
Priority date: 2020-03-23
Filing date: 2020-03-23
Publication date: 2021-09-30
Also published as: CN114930306A

Abstract

Provided are a bandwidth equalization method and apparatus. The method comprises: monitoring the frequency of access to a plurality of caches; determining a cold spot cache and a hot spot cache from among the plurality of caches; determining hot spot information in the hot spot cache; and recording first index information of the hot spot information and identification information of the cold spot cache in a target table entry, with the target table entry being a table entry in a redirection data table. In the present application, the problem of uneven distribution of requests is greatly alleviated, thereby improving the problem of serious imbalances in bandwidth acquisition, and improving the performance of information acquisition.

Description

Bandwidth equalization method and device

Technical field

This application relates to the field of data communication, and in particular to a bandwidth equalization method and device.

Background technique

In order to improve the efficiency of fetching instructions, a cache (high-speed buffer memory) is usually set between the processor core and the main memory, and the frequently fetched instructions from the main memory are cached in the cache, and then the instructions to be fetched are fetched on the processor core At this time, it is first judged whether there is a command to be fetched in the cache by a matching method. If so, the command to be fetched is fetched from the cache; if not, the command to be fetched is fetched from the main memory.

With the vigorous development of 5G technology, the requirements for the bandwidth and delay of obtaining instructions are getting higher and higher, and the processor cores are also developing in the direction of multi-core parallel computing. The original single cache is more and more difficult to meet the demand for obtaining instructions. . In order to solve the above problems, multiple caches are usually used to solve the problem of bandwidth and delay of obtaining instructions.

However, in a solution that uses multiple caches, the mapping relationship between the storage block in the main memory and the multiple caches is determined by the physical address of the storage block in the main memory. In this way, the storage in the main memory is stored in the multiple caches. In the case of an instruction in a block, it is necessary to determine the cache storing the instruction according to the physical address of the storage block storing the instruction. Since the physical address of the instruction is the physical address of the storage block storing the instruction, it can be understood as the storage in the main memory The way instructions are deployed in multiple caches is only determined by the physical address of the instruction. Based on this, when executing a request to acquire instructions to be acquired, if most of the physical addresses of the instructions to be acquired point to the same cache, the problem of uneven request distribution will occur, which will cause a serious imbalance in the instruction acquisition bandwidth and a decrease in instruction acquisition performance. problem.

Summary of the invention

This application provides a bandwidth equalization method and device, which is used to solve the uneven distribution of requests due to the fact that the deployment mode of instructions in the main memory in multiple caches is only determined by the physical addresses of the instructions in the main memory. The problem of serious imbalance in acquisition bandwidth and degraded instruction acquisition performance.

In a first aspect, a bandwidth equalization method is provided, including: monitoring the access frequency of a plurality of cache memories; determining a cold spot cache memory and a hot spot cache memory among the plurality of cache memories; Hot spot information is determined in the memory; the first index information of the hot spot information and the identification information of the cold spot cache memory are recorded in a target entry, where the target entry is an entry in the redirection data table .

By monitoring the access frequency of multiple caches, and determining the cold spot cache and hot spot cache in multiple caches, and recording the first index information of the hot spot information in the hot spot cache and the id of the cold spot cache in the target of the redirect data table In entry, the hotspot information in the cache with high access frequency is redirected to the cache with low access frequency, which changes the deployment method of information in multiple caches, and the deployment method of information in multiple caches is the same as that of each cache. Access frequency is related, so that when obtaining information according to the request, it can greatly alleviate the problem of uneven request distribution, thereby improving the problem of serious imbalance of access bandwidth, and improving the performance of information acquisition; in addition, because the information is stored in multiple caches The distribution is related to the access frequency of each cache, so the information acquisition performance can be estimated; in addition, the hotspot information can be redirected only according to the access frequency of each cache, and the steps are simple and easy to implement.

In a possible implementation manner, the monitoring the access frequency of the plurality of cache memories includes: in response to a frequency monitoring instruction, monitoring the access frequency of the plurality of cache memories in each of the monitoring periods based on a monitoring period .

In a possible implementation manner, the determining the cold spot cache memory and the hot spot cache memory among the plurality of cache memories includes: according to the access frequency of each of the cache memories, selecting the one with the highest access frequency The cache memory is determined to be the hot spot cache memory, and the cache memory with the smallest access frequency is determined to be the cold spot cache memory; or the access frequency is determined according to the access frequency of each cache memory A cache with a frequency greater than a first preset frequency is determined to be the hot spot cache, and a cache with an access frequency less than a second preset frequency is determined to be the cold spot cache, wherein the first preset The frequency is greater than the second preset frequency.

In a possible implementation manner, the determining hotspot information in the hotspot cache includes: determining whether the access frequency of the hotspot cache reaches the frequency configured by the register and the access frequency of the hotspot cache Whether the difference between the access frequency of the cold spot cache memory and the cold spot cache memory is greater than the configured value; if so, hot spot information is determined in the hot spot cache memory.

By judging whether the access frequency of the hot spot cache memory reaches the frequency configured by the register and whether the difference between the access frequency of the hot spot cache memory and the access frequency of the cold spot cache memory is greater than the configured value, and when this condition is met, the hot spot cache The hot-spot instruction is determined in the memory to record the first index information of the hot-spot instruction and the identification information of the cold-spot cache memory in the target entry, so as to realize the redirection of the hot-spot instruction. In other words, a restriction condition is provided for starting the redirection process, and the redirection process can be started only when the restriction condition is met, which improves the accuracy of starting the redirection process.

In a possible implementation manner, the determining hot spot information in the hot spot cache memory includes: determining whether the access frequency of the hot spot cache memory is greater than n times the access frequency of the cold spot cache memory; If yes, the hot spot information is determined in the hot spot cache memory.

By judging whether the access frequency of the hot spot cache memory is greater than n times the access frequency of the cold spot cache memory, and when this condition is met, the hot spot instruction is determined in the hot spot cache memory to combine the first index information of the hot spot instruction with The identification information of the cold spot cache memory is recorded in the target table entry, thereby realizing the redirection of the hot spot instruction. In other words, a restriction condition is provided for starting the redirection process, and the redirection process can be started only when the restriction condition is met, which improves the accuracy of starting the redirection process.

In a possible implementation manner, the determining hotspot information in the hotspot cache memory includes: monitoring the access frequency of each buffer line in the hotspot cache memory; according to the access of each cache line Frequency, determine a hotspot buffer line in the hotspot cache memory; determine the information stored in the hotspot buffer line as hotspot information.

In a possible implementation manner, the redirection data table includes a plurality of table entries, each of the table entries includes a first identifier and a second identifier, the first identifier is a valid mark or an invalid mark, so The second mark is a hot spot mark or a non-hot spot mark.

In a possible implementation manner, the recording the first index information of the hot spot information and the identification information of the cold spot cache memory in a target entry includes: according to each of the multiple entries The first identifier and the second identifier of each entry, and the candidate entry is determined among the multiple entries, wherein the candidate entry includes the first identifier of the multiple entries that is an invalid flag The entry and the entry with the second identifier as a non-hot spot mark; determine the target entry in the candidate entry; record the first index information of the hot spot information and the identification information of the cold spot cache In the target table entry.

In a possible implementation manner, after recording the first index information of the hot spot information and the identification information of the cold spot cache memory in the target entry, the method further includes: recording the first index in the target entry The second mark is set as a hot spot mark, and the first mark in the target entry is set as a valid mark.

In a possible implementation, the method further includes: monitoring the access frequency of each entry in the redirection data table; judging whether the access frequency of the first entry is less than a third preset frequency, wherein, The first entry is an entry with the second identifier being the hot spot tag; the second identifier of the first entry whose access frequency is less than the third preset frequency is modified to a non-hot spot tag; determining Whether the access frequency of the second entry is greater than the fourth preset frequency, where the second entry is the entry with the second identification as the non-hot spot flag; the access frequency is greater than the fourth preset frequency The second identifier of the second table entry is modified to a hot spot label; wherein, the fourth preset frequency is greater than the third preset frequency.

By monitoring the access frequency of each entry in the redirection data table, and according to the comparison result of the access frequency of the entry with the third preset frequency or the fourth preset frequency, it is determined whether to change the second identifier in the entry Status, that is, to determine whether to change the hot and cold state of the instruction corresponding to the first index information in the entry, so as to realize real-time monitoring and monitoring of the hot and cold state of the instruction corresponding to the first index information of each entry in the data table. Update to ensure the timeliness and accuracy of the information in the redirection data table.

In a possible implementation manner, the method further includes: filling the hot spot information into a cold spot buffer line in the cold spot cache memory.

In a possible implementation manner, the method further includes: determining any one of the buffer lines in the cold spot cache memory as the cold spot buffer line; or determining the access in the cold spot cache memory The buffer line whose frequency is less than the fifth preset frequency is determined as the cold spot buffer line; or the buffer line with the smallest access frequency in the cold spot cache memory is determined as the cold spot buffer line.

In a possible implementation, the method further includes: reading a first request, where the first request is a request for obtaining information to be obtained, the first request carries second index information, and the second index The information is the index information used to obtain the information to be obtained; the first index information of the information to be obtained is determined according to the second index information; the first index information of the information to be obtained is combined with the redirection data table Match the first index information in each entry of the entry; if the first index information in one entry matches the first index information of the information to be obtained, it will match the first index information of the information to be obtained The cache memory corresponding to the identification information of the cache memory in the entry matching the index information is determined as the first target cache memory; the second index information is sent to the first target cache memory, so that all The first target cache memory obtains the to-be-obtained information according to the second index information.

Determine the first index information of the information to be obtained according to the second index information, match the first index information of the information to be obtained with the first index information in each entry in the redirection data table, and if there is a matching table Item, the cache memory corresponding to the identification information of the cache memory in the matching entry is determined as the first target cache memory, and the second index information is sent to the first target cache memory, so that the first The target cache obtains the information to be obtained according to the second index information, so the first request is split based on the redirected data table, which greatly alleviates the problem of uneven request distribution, thereby improving the problem of serious imbalance in request acquisition bandwidth and improving Improved information acquisition performance.

In a possible implementation manner, the method further includes: if the first index information in each of the entries does not match the first index information of the information to be obtained, then according to the second index The information and the mapping rule determine the first target cache memory; the second index information is sent to the first target cache memory, so that the first target cache memory obtains all data according to the second index information. Describe the information to be obtained.

In a possible implementation manner, the method further includes: receiving third index information sent by the first target cache, the third index information being calculated from the second index information and the storage interval, the The third index information is generated by the first target cache memory when it is determined that the acquisition of the information to be acquired has not been completed according to the end identifier in the information to be acquired; the information to be acquired is determined according to the third index information The first index information; the first index information of the information to be obtained is matched with the first index information in each entry in the redirected data table; if the first index information in one of the entries matches If the first index information of the information to be obtained matches, the cache memory corresponding to the identification information of the cache memory in the entry matching the first index information of the information to be obtained is determined as the second target cache memory ; Send the third index information to the second target cache memory, so that the second target cache memory obtains the to-be-obtained information according to the third index information.

In a possible implementation, the method further includes: if the first index information in each of the entries does not match the first index information of the information to be obtained, then according to the third index The information and the mapping rule determine the second target cache memory; the third index information is sent to the second target cache memory, so that the second target cache memory obtains all data according to the third index information. Describe the information to be obtained.

In a second aspect, a bandwidth equalization device is provided, including: a first monitoring module for monitoring the access frequency of a plurality of cache memories; a first determination module for determining a cold spot among the plurality of cache memories. A buffer memory and a hot spot cache memory; a second determination module, used to determine hot spot information in the hot spot cache memory; a recording module, used to compare the first index information of the hot spot information with the cold spot cache memory The identification information of is recorded in a target entry, where the target entry is an entry in the redirection data table.

In a possible implementation manner, the first monitoring module is specifically configured to respond to a frequency monitoring instruction and monitor the access frequency of the plurality of cache memories in each monitoring period based on a monitoring period.

In a possible implementation manner, the first determining module is specifically configured to determine, according to the access frequency of each cache memory, the cache memory with the highest access frequency as the hot spot cache memory, Determine the cache memory with the smallest access frequency as the cold spot cache memory; or determine the cache memory with an access frequency greater than a first preset frequency as the cold spot cache memory according to the access frequency of each cache memory A hot spot cache memory, which determines a cache memory with an access frequency less than a second preset frequency as the cold spot cache memory, wherein the first preset frequency is greater than the second preset frequency.

In a possible implementation manner, the second determining module is specifically configured to determine whether the access frequency of the hot spot cache memory reaches the frequency configured by the register and the access frequency of the hot spot cache memory and the cold spot Whether the difference in the access frequency of the cache memory is greater than the configured value; if so, hot spot information is determined in the hot spot cache memory.

In a possible implementation manner, the second determining module is specifically configured to determine whether the access frequency of the hot spot cache memory is greater than n times the access frequency of the cold spot cache memory; The hot spot information is determined in the hot spot cache memory.

In a possible implementation manner, the second determining module is specifically configured to monitor the access frequency of each buffer line in the hotspot cache; according to the access frequency of each buffer line, the A hot spot buffer line is determined in the hot spot cache memory; the information stored in the hot spot buffer line is determined as hot spot information.

In a possible implementation manner, the recording module is specifically configured to determine the candidate table among the multiple table items according to the first identifier and the second identifier of each of the multiple table items Item, wherein the candidate entry includes an entry whose first identification is an invalid flag and an entry whose second identification is a non-hot spot flag among the plurality of entries; in the candidate entry Determine the target entry; record the first index information of the hot spot information and the identification information of the cold spot cache in the target entry.

In a possible implementation manner, the method further includes: a setting module, configured to set the second identifier in the target entry as a hotspot label, and set the first identifier in the target entry as a valid label.

In a possible implementation manner, it further includes: a second monitoring module for monitoring the access frequency of each entry in the redirection data table; a first judging module for judging the access of the first entry Whether the frequency is less than the third preset frequency, wherein the first entry is the entry with the second identification as the hotspot mark; the first modification module is configured to set the access frequency to be less than the third preset frequency The second identifier of the first entry is modified to a non-hot spot flag; the second determination module is used to determine whether the access frequency of the second entry is greater than the fourth preset frequency, wherein the second entry is all The second identifier is an entry of the non-hot-spot label; a second modification module is configured to modify the second identifier of the second entry whose access frequency is greater than the fourth preset frequency to a hot-spot label; wherein, The fourth preset frequency is greater than the third preset frequency.

In a possible implementation manner, it further includes: a filling module, configured to fill the hot spot information into the cold spot buffer row in the cold spot cache memory.

In a possible implementation manner, the method further includes: a third determining module, configured to determine any buffer line in the cold spot cache memory as the cold spot buffer line; or to cache the cold spot A buffer line with an access frequency less than the fifth preset frequency in the memory is determined as a cold spot buffer line; or a buffer line with the smallest access frequency in the cold spot cache memory is determined as a cold spot buffer line.

In a possible implementation manner, it further includes: a reading module, configured to read a first request, the first request is a request for obtaining information to be obtained, the first request carries second index information, the The second index information is the index information used to obtain the information to be obtained; the fourth determining module is used to determine the first index information of the information to be obtained according to the second index information; the first matching module is used to The first index information of the information to be obtained is matched with the first index information in each entry in the redirection data table; the fifth determining module is configured to determine the first index information in one of the entries If it matches the first index information of the information to be obtained, the cache memory corresponding to the identification information of the cache memory in the entry matching the first index information of the information to be obtained is determined as the first target cache Memory; a first sending module, configured to send the second index information to the first target cache, so that the first target cache obtains the to-be-obtained according to the second index information information.

In a possible implementation manner, it further includes: a sixth determining module, configured to: if the first index information in each of the entries does not match the first index information of the information to be obtained, then according to the The second index information and the mapping rule determine the first target cache memory; the second sending module is used to send the second index information to the first target cache memory, so that the first target is high-speed The buffer memory obtains the to-be-obtained information according to the second index information.

In a possible implementation manner, it further includes: a receiving module, configured to receive third index information sent by the first target cache memory, where the third index information is calculated from the second index information and the storage interval, The third index information is generated by the first target cache memory when it is determined that the acquisition of the information to be acquired has not been completed according to the end identifier in the information to be acquired; the seventh determining module is configured to The three index information determines the first index information of the information to be obtained; the second matching module is used to compare the first index information of the information to be obtained with the first index information in each entry in the redirect data table Matching; an eighth determining module, configured to match the first index information of the information to be obtained if the first index information in one of the entries matches the first index information of the information to be obtained The cache memory corresponding to the identification information of the cache memory in the entry is determined to be the second target cache memory; the third sending module is configured to send the third index information to the second target cache memory, So that the second target cache memory obtains the to-be-obtained information according to the third index information.

In a possible implementation manner, it further includes: a ninth determining module, configured to: if the first index information in each entry does not match the first index information of the to-be-obtained information, according to the The third index information and the mapping rule determine the second target cache memory; the fourth sending module is configured to send the third index information to the second target cache memory, so as to make the second target high-speed The buffer memory obtains the to-be-obtained information according to the third index information.

In a third aspect, a computer-readable storage medium is provided, including a computer program, which when executed on a computer, causes the computer to execute the method described in any one of the first aspects.

In a fourth aspect, a computer program is provided, when the computer program is executed by a computer, it is used to execute the method described in any one of the first aspect.

In a fifth aspect, a chip is provided, including a processor and a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute any one of the first aspect The method described.

Description of the drawings

FIG. 1 is a schematic diagram of an application scenario of a bandwidth equalization method provided by an embodiment of the application;

FIG. 2 is a schematic flowchart of a bandwidth equalization method provided by an embodiment of the application;

FIG. 3 is a schematic diagram of the process of recording the first index of the hot spot instruction thank you and the id of the cold spot cache in the target entry provided by an embodiment of the application;

FIG. 4 is the first part of a schematic flowchart of an information acquisition method provided by an embodiment of this application;

FIG. 5 is the second part of a schematic flowchart of an information acquisition method provided by an embodiment of this application;

FIG. 6 is the third part of a schematic flowchart of an information acquisition method provided by an embodiment of this application;

FIG. 7 is the fourth part of a schematic flowchart of an information acquisition method provided by an embodiment of this application;

FIG. 8 is a schematic diagram of an application scenario including multiple caches provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a slice cache provided by an embodiment of the application;

FIG. 10 is the first part of a schematic flowchart of another information acquisition method provided by an embodiment of this application;

FIG. 11 is the second part of a schematic flowchart of another information acquisition method provided by an embodiment of the application;

FIG. 12 is the third part of a schematic flowchart of another information acquisition method provided by an embodiment of this application;

FIG. 13 is a schematic structural diagram of a bandwidth equalization device provided by an embodiment of the application.

Detailed ways

The technical solution in this application will be described below in conjunction with the accompanying drawings.

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be described clearly and completely in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , Not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

The terms "first", "second", etc. in the specification embodiments, claims, and drawings of this application are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating Or imply the order. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device need not be limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

It should be understood that in this application, "at least one (item)" refers to one or more, and "multiple" refers to two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A, only B, and both A and B , Where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "The following at least one item (a)" or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a). For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ", where a, b, and c can be single or multiple.

Fig. 1 is a schematic diagram of an application scenario of a bandwidth equalization method provided by an embodiment of the application. As shown in Fig. 1, the application scenario may include: multiple caches, multiple processor cores, and main memory. (Not shown in the figure), redirection module, redirection data table and crossbar (crossbar). in:

The main memory includes multiple storage blocks, each storage block is composed of a number of storage units, and each storage module is used to store information. The main memory can be a data main memory, that is, the information stored in the main memory is data, or it can be an instruction main memory, that is, the information stored in the main memory is an instruction, which is not specifically limited in this application.

In the following, taking the main memory as the command main memory as an example, the principle of each module in this application scenario will be explained.

The way of storing instructions to be stored in main memory can be: judging whether the size of the instructions to be stored is greater than the capacity of the storage block in the main memory, and if the size of the instructions to be stored is equal to or less than the storage capacity of the storage block, the instructions to be stored are Stored in a storage block as a whole; if the size of the instruction to be stored is greater than the storage capacity of the storage block, the instruction to be stored is divided into multiple instruction segments according to the size of the instruction to be stored and the storage capacity of the storage block, and then The divided instruction segments are stored in multiple storage blocks.

In addition, the end indicator (EI) can also be set for the instruction stored in the storage block. When the EI flag is 0, it means that the instruction stored in the storage block is one of the instruction segments corresponding to the instructions to be stored and is not The last instruction segment of the instruction to be stored, if the EI flag is 1, it indicates that the instruction stored in the storage block is the last instruction segment of the corresponding instruction to be stored, or the instruction stored in the storage block is The corresponding instruction to be stored. Based on this, if the size of the instruction to be stored is equal to or less than the storage capacity of the storage block, the instruction to be stored is stored in a storage block as a whole, and the EI of the instruction in the storage block (that is, the instruction to be stored) The flag is set to 1. If the size of the instruction to be stored is greater than the storage capacity of the storage block, the instruction to be stored is divided into multiple instruction segments according to the size of the instruction to be stored and the capacity of the storage block, and then the multiple instruction segments are stored in multiple storage blocks , Where the number of multiple instruction segments is the same as the number of multiple storage blocks, and one instruction segment corresponds to one storage block. Finally, set the EI flag for the instructions stored in each storage block. If the instructions stored in the storage block are not pending To store the last instruction segment of the instruction, set the EI flag of the instruction stored in the storage block to 0. If the instruction stored in the storage block is the last instruction segment of the instruction to be stored, then the instruction stored in the storage block is The EI flag is set to 1. In this way, when storing instructions to be stored, by setting the EI flag of the instructions stored in each storage block, when obtaining the instructions to be stored, the instructions stored in the storage block can be judged by the EI flag of the instructions stored in the storage block. Whether it is an instruction segment of the instruction to be stored or the instruction to be stored, the detailed process will be described in the information acquisition part below, and will not be repeated here.

Each cache includes multiple cache lines (cachelines), each cacheline is composed of multiple storage units, each cacheline is used to store instructions in the storage block in the main memory, and the storage capacity of each cacheline is the same as that in the main memory. The storage capacity of each storage block is the same. It should be noted that the cache here may be, for example, a slice cache (slice-based cache memory), etc., which is not specifically limited in this application.

The mapping rules between storage blocks in the main memory and multiple caches include the mapping relationship between the storage blocks in the main memory and multiple caches, and the mapping relationship between the storage blocks in the main memory and the cache lines in the cache. Among them, the mapping relationship between the storage block in the main memory and multiple caches can be set according to specific application scenarios, which is not specifically limited in this application. The mapping relationship between the storage block in the main memory and the buffer line in the cache can be, for example, any one of group connection, full connection, direct mapping, etc., which is not specifically limited in this application.

Through the above mapping rules, the instructions stored in the storage block in the main memory can be cached in the cache. Specifically, the cache corresponding to the storage block and the corresponding cache line in the corresponding cache may be determined according to the mapping rule, and then the instructions stored in the storage block are buffered in the corresponding cache line in the corresponding cache.

The redirection module is used to monitor the access frequency of each cache in multiple caches, and adjust the storage location of hotspot instructions in multiple caches according to the access frequency of each cache, and then balance the access frequency of each cache to achieve the requested Balanced allocation, balanced acquisition of bandwidth, and improved performance of information acquisition.

The redirection data table is used to record the adjustment record of the redirection module to the hotspot instruction. It should be noted that the redirection module and the redirection data table will be described in detail below, so they will not be repeated here.

It should be noted that when the main memory is the data main memory, the working principle of each module in this application scenario is the same as the principle when the main memory is the command main memory, so it will not be repeated here.

It should be noted that the above application scenarios are only exemplary and are not used to limit the application.

FIG. 2 is a schematic flowchart of a bandwidth equalization method provided by an embodiment of the application. The execution subject of the method may be, for example, a device or chip that can execute the method shown in FIG. 2 such as the redirection module in the above application scenario. Here, the application will be explained by taking the main memory as the command main memory, that is, the information stored in the main memory as the command as an example. As shown in Figure 2, the method includes the following steps:

Step 201: Monitor the access frequency of multiple caches.

In the embodiment of the present application, the monitoring method may include the following two types, among which:

The first is to regularly monitor the access frequency of each of the multiple caches during the monitoring period. Specifically, multiple monitoring moments can be set, and at the beginning of each monitoring moment, the access frequency of each cache in the monitoring period is monitored. Multiple monitoring moments and monitoring periods can be set according to specific application scenarios, which are not specifically limited here. For example, the monitoring period can be 0.01 ms.

The second type is to monitor the access frequency of multiple caches in each monitoring cycle based on a monitoring cycle in response to a frequency monitoring command. Specifically, when the access frequency of each cache in multiple caches needs to be monitored, a frequency monitoring instruction can be sent to the execution subject of the method (for example, the redirection module), that is, enable the execution subject of the method, so that the method The main body of execution receives and responds to the frequency monitoring instruction, and immediately starts the statistics of timing and the number of visits. When the timing reaches the monitoring period, the statistics of the number of visits are recorded and the visit frequency is calculated.

In the above two methods, the access frequency of each cache in the monitoring period is obtained as follows: first, the number of accesses of each cache in the monitoring period can be obtained through a counter, and then, the number of accesses of each cache in the monitoring period The ratio of the number of accesses to the duration of the monitoring period is determined as the access frequency of the corresponding cache. It should be noted that in the above method, the monitoring period of each cache is the same, and the number of accesses of each cache in the monitoring period is positively correlated with the access frequency. Therefore, it is also possible to directly set each cache in the monitoring period. The number of accesses is determined as the access frequency of the corresponding cache in the monitoring period, which can reduce the amount of calculation while ensuring the accuracy of the data, improve the calculation efficiency, and save the calculation cost.

Through periodic monitoring or regular monitoring, the dynamic monitoring of the access frequency of each cache is realized.

It should be noted that the above method of monitoring the access frequency of each of the multiple caches is only exemplary, and is not intended to limit the present invention.

Step 202: Determine a cold spot cache and a hot spot cache among multiple caches.

In the embodiment of the present application, the cold spot cache and the hot spot cache can be determined in the following two ways, among which:

Method 1: According to the access frequency of each cache, the cache with the largest access frequency is determined as a hot spot cache, and the cache with the smallest access frequency is determined as a cold spot cache. Specifically, each cache can be sorted in descending order of access frequency, the first cache is determined to be a hot spot cache, and the last cache is determined to be a cold spot cache.

Method 2: According to the access frequency of each cache, the cache with an access frequency greater than the first preset frequency is determined as a hot cache, and the cache with an access frequency less than the second preset frequency is determined as a cold spot cache, where the first preset The frequency is greater than the second preset frequency. It should be noted that the first preset frequency and the second preset frequency can be set according to the statistical result of historical data.

It should be noted that the above two methods are only exemplary and are not used to limit the present invention. For example, multiple caches can be sorted in descending order of access frequency, and the top X caches are ranked It is determined as a hot spot cache, and the cache at the bottom M position is determined as a cold spot cache. Among them, the values of X and M can be the same or different. Various other methods can also be used to select a hot spot cache and a cold spot cache from multiple caches.

Step 203: Determine the hotspot instruction in the hotspot cache.

In the embodiment of the present application, if the main memory is the command main memory, the hotspot information is the hotspot instruction, and if the main memory is the data main memory, the hotspot information is the hotspot data. Since the main memory is used as the command main memory as an example for description, the hot spot information here is a hot spot command.

For step 203, firstly, monitor the access frequency of each cacheline in the hotspot cache, then determine the hotspot cacheline in the hotspot cache according to the access frequency of each cacheline, and finally determine the instructions stored in the hotspot cacheline as hotspot instructions.

Specifically, the principle of monitoring the access frequency of each cacheline in the hotspot cache is as follows:

The counter is used to obtain the number of accesses of each cacheline in the hotspot cache during the same time interval, and then the ratio of the number of accesses of each cacheline in the same time interval to the same time interval is determined as the access frequency of the corresponding cacheline. It should be noted that since each cacheline corresponds to the same time interval, and the number of accesses of each cacheline in the same time interval is positively related to the access frequency, it is also possible to directly place each cacheline in the same time interval. The number of accesses is determined as the access frequency of the corresponding cacheline in the same time interval, which reduces the amount of calculation while ensuring the accuracy of the data, improves the calculation efficiency, and saves the calculation cost.

According to the access frequency of each cacheline in the hotspot cache, the way to determine the hotspot cacheline in the hotspot cache can, for example, be: according to the access frequency of each cacheline, the cachelines in the hotspot cache are sorted in descending order of access frequency. The first cacheline is determined as a hot cacheline; or the access frequency of each cacheline is compared with a set value, and the cacheline with an access frequency greater than the set value is determined as a hot cacheline. It should be noted that the above manner is only exemplary and is not used to limit the present invention.

It should be noted that when there are multiple hotspot caches, the hotspot cacheline in each hotspot cache can be determined according to the above principle, and then the hotspot instruction corresponding to each cacheline is determined according to each hotspot cacheline.

Step 204: Record the first index information of the hot spot instruction and the identification information (id) of the cold spot cache in a target entry (entry), where the target entry is an entry in the redirection data table.

In the embodiment of the present application, the first index information of the hotspot instruction may be determined according to a mapping rule between a storage block in the main memory and multiple caches.

Next, the structure of the redirection data table will be described.

The redirection data table includes multiple entries, and each entry may include a first identifier and a second identifier, where the first identifier is a valid tag or an invalid tag, that is, the value of the first identifier has two values. There are two options. The two options are valid and invalid tags. If the first identifier in the entry is a valid tag, then there is valid information in the entry, and if the first identifier in the entry is an invalid tag, then there is no entry in the entry. Valid information; the second identifier is a hotspot tag or a non-hotspot tag, that is, there are two options for the value of the second tag. The two options are hotspot tags and non-hotspot tags. If the second tag of the entry is a hotspot tag, this The instruction corresponding to the first index information recorded in the entry is a hot spot instruction. If the second identifier of the entry is a non-hot spot mark, the instruction corresponding to the first index information recorded in the entry is a cold spot instruction. Based on this, each entry includes four areas. One area is used to record the first identifier, one area is used to record the second identifier, one area is used to record the first index information of the command, and one area is used to record the id of the cache. .

It should be noted that the first index information of the instruction in each entry can be determined according to the mapping rule between the storage block in the main memory and multiple caches.

On this basis, as shown in Figure 3, the steps of recording the first index information of the hot spot instruction and the id of the cold spot cache in the target entry are as follows:

Step 301: According to the first identification and the second identification of each entry in the plurality of entries, a candidate entry is determined among the plurality of entries, wherein the candidate entry includes the entry whose first identification is an invalid mark and the first identification among the plurality of entries. 2. The entry identified as a non-hot spot mark, that is, the candidate entry is an entry that does not have valid information among multiple entries, and the entry corresponding to the first index information recorded in the entry is an entry that is a cold spot instruction.

Step 302: Determine the target entry among the candidate entries. Specifically, any one of the candidate entries can be determined as the target entry; or if the candidate entry includes the entry with the first identification as an invalid mark and the entry with the second identification as a non-hot spot, it is preferable to select the first entry among the candidate entries. Any entry identified as an invalid mark is determined as the target entry; or if the candidate entries only include entries with the second identification as a non-hot-spot mark, then any entry identified as a hot-spot mark as a non-hot-spot mark is determined as the target entry.

It should be noted that when the number of hotspot instructions is multiple, that is, there are multiple hotspot caches and at least one hotspot cache includes at least one hotspot cacheline, or there is one hotspot cache and the hotspot cache includes multiple In the case of a hotspot cacheline, the target entry of each hotspot instruction needs to be determined by the above principles.

Step 303: Record the first index information of the hot spot instruction and the id of the cold spot cache in the target entry.

In the embodiment of the present application, if there are multiple hot spot instructions, it is first necessary to determine the corresponding cold spot cache for each hot spot instruction respectively, and then combine the first index information of each hot spot instruction and its corresponding cold spot cache The id of the cache is recorded in the corresponding target entry.

If there is one hot spot instruction, it is first necessary to determine the cold spot cache for the hot spot instruction, and then record the first index information of the hot spot instruction and the determined id of the cold spot cache in the corresponding target entry.

After step 303 is performed, the second identifier in the target entry can also be set as a hot spot flag to indicate that the instruction corresponding to the first index information recorded in the target entry is a hot spot instruction, and the first identifier in the target entry can be set to A valid flag to indicate that there is valid information in the target entry.

The way to determine the cold spot cache corresponding to each hot spot instruction can be: determine the corresponding cold spot cache for each hot spot cache respectively, and then determine the cold spot cache corresponding to each hot spot cache as the corresponding hot spot cache The hot spot instruction corresponds to the cold spot cache. in:

The method of determining the corresponding cold spot cache for each hot spot cache can include:

If there is one cold spot cache, the cold spot cache is determined as the cold spot cache corresponding to each hot spot cache. That is, the cold spot cache corresponding to each hot spot cache is the same.

If there are multiple cold spot caches, the corresponding cold spot cache can be determined for each hot spot cache in the multiple cold spot caches. Among them, the cold spot cache corresponding to each hot spot cache can be exactly the same or completely different. It may also be partly the same or partly different, etc., and there is no special limitation here.

At the same time or after recording the first index information of the hot-spot instruction and the id of the cold-spot cache in the target entry, the hot-spot instruction can also be filled into the cold-spot cacheline in the cold-spot cache. That is, the cold spot cache line is determined in the cold spot cache, and the hot spot instructions are filled into the cold spot cache line in the cold spot cache. Specifically, the method of determining the cold spot cacheline in the cold spot cache may include: determining any cacheline in the cold spot cache as a cold spot cacheline; or, monitoring the access frequency of each cacheline in the cold spot cache, and setting the cold spot The cache line whose access frequency in the cache is less than the fifth preset frequency is determined as a cold spot cacheline; or the access frequency of each cache line in the cold spot cache is monitored, and the cache line with the smallest access frequency in the cold spot cache is determined as a cold spot cache line. It should be noted that the above process is only exemplary and is not used to limit the application.

It should be noted that when there are multiple hot-spot instructions, each hot-spot instruction is respectively filled into the cold-spot cacheline in its corresponding cold-spot cache.

Further, in order to update the hot and cold state of the instruction corresponding to the first index information in each entry in the redirection data table, this application also includes: monitoring the access frequency of each entry in the redirection data table, and determining Whether the access frequency of the first entry is less than the third preset frequency, and modify the second identification of the first entry whose access frequency is less than the third preset frequency to a non-hot spot mark, and determine whether the access frequency of the second entry is greater than the fourth preset frequency Set the frequency, and modify the second identifier of the second entry whose access frequency is greater than the fourth preset frequency to a hotspot tag, where the first entry is the entry with the second identifier in the redirection data table as the hotspot tag, and the second entry In order to redirect the entry in the data table whose second mark is a non-hot spot mark, the fourth preset frequency is greater than the third preset frequency.

The process of monitoring the access frequency of each entry in the redirection data table includes: judging that the first index information stored in each entry in the redirection data table is successfully matched by the index information of the instruction to be obtained within a preset time interval The number of times, and the ratio of the number of times the first index information stored in each entry is successfully matched within the preset time interval to the preset time interval is determined as the access frequency of the corresponding entry. It should be noted that since the preset time interval corresponding to each entry is the same, and the number of times that the first index information stored in each entry is successfully matched within the preset time interval is positively correlated with its access frequency, it is also possible The number of times the first index information stored in each entry is successfully matched within a preset time interval is determined as the access frequency of the corresponding entry, which can improve the calculation efficiency, reduce the calculation amount and the calculation cost while ensuring the accuracy of the data. .

By monitoring the access frequency of each entry in the redirection data table, and according to the comparison result of the entry access frequency with the third preset frequency or the fourth preset frequency, determine whether to change the instruction corresponding to the first index information in the entry The hot-cold and hot-spot status of each entry in the redirected data table can be monitored and updated in real time, and the timeliness and accuracy of the information in the redirected data table can be ensured.

In order to further confirm whether to redirect the hotspot instruction, and to further improve the accuracy of starting the redirection process, the hotspot instruction can be determined in the hotspot cache in the following two ways. in:

Method 1: Determine whether the access frequency of the hot spot cache reaches the frequency configured by the register and whether the difference between the access frequency of the hot spot cache and the access frequency of the cold spot cache is greater than the configured value. If so, determine the hot spot instruction in the hot spot cache. The frequency configured by the register may be 1000 MOPS, for example.

In the above method 1, if there are multiple hot spot caches, the cold spot cache corresponding to each hot spot cache can be determined in the cold spot cache to determine whether the access frequency of each hot spot cache reaches the frequency configured by the register and the number of hot spot caches for each hot spot cache. Whether the difference between the access frequency and the access frequency of the corresponding cold spot cache is greater than the configured value, the hot spot instruction is determined in the hot spot cache that meets the above conditions. It should be noted that the method of determining the cold spot cache corresponding to each hot spot cache has been described above, so it will not be repeated here.

Method 2: Determine whether the access frequency of the hot spot cache is greater than n times the access frequency of the cold spot cache, and if so, determine the hot spot instruction in the hot spot cache.

In the second method above, if there are multiple hot spot caches, the cold spot cache corresponding to each hot spot cache can be determined in the cold spot cache to determine whether the access frequency of each hot spot cache is greater than n times the corresponding cold spot cache The access frequency of, and the hotspot instruction is determined in the hotspot cache that meets the above conditions.

Obviously, through the restriction conditions for determining the hot spot instruction provided in the above method 1 and method 2, only when the restriction condition is met, the hot spot instruction can be determined in the hot spot cache, thereby combining the first index information of the hot spot instruction and the cold spot cache The id is recorded in the target entry to realize the redirection of hot instructions. It can be understood that: the above method 1 and method 2 provide restriction conditions for starting the redirection process, and the redirection process can be started only when the restriction conditions are met, which improves the accuracy of starting the redirection process.

It should be noted that the execution principle of the bandwidth equalization method when the main memory is the data main memory is the same as the execution principle of the bandwidth equalization method when the main memory is the command main memory, so it will not be repeated here.

To sum up, by monitoring the access frequency of multiple caches, and determining the cold spot cache and hot spot cache in the multiple caches, and recording the first index information of the hot spot information in the hot spot cache and the id of the cold spot cache in the re In the target entry of the directional data table, the hot information in the cache with high access frequency is redirected to the cache with low access frequency, which changes the way information is deployed in multiple caches, and the way information is deployed in multiple caches It is related to the access frequency of each cache. This can greatly alleviate the problem of uneven distribution of requests when obtaining information according to the request, thereby improving the problem of serious imbalance of access bandwidth and improving the performance of information acquisition; in addition, because the information is in The distribution of multiple caches is related to the access frequency of each cache, so the information acquisition performance can be estimated; in addition, the hotspot information can be redirected only according to the access frequency of each cache, the steps are simple and easy to implement .

Below, based on the above bandwidth equalization method, the information acquisition process will be described. FIG. 4 is the first part of a schematic flowchart of an information acquisition method provided by an embodiment of this application, and FIG. The second part of the schematic flow chart of an information acquisition method, FIG. 6 is the third part of the schematic flow chart of an information acquisition method provided by an embodiment of this application, and FIG. 7 is a flow chart of an information acquisition method provided by an embodiment of this application The fourth part of the schematic. The execution subject of the information acquisition method may be the same as or different from the execution subject of the above bandwidth equalization method, which is not specifically limited in this application. In the following, the information acquisition process will be described by taking the execution body as the redirection module in FIG. 1, the main memory as the instruction main memory, and the information to be acquired as the instruction to be acquired as an example. As shown in Figure 4 to Figure 7, the information acquisition process may include:

Step 401: The redirection module reads the first request. The first request is a request for obtaining an instruction to be obtained, the first request carries second index information, and the second index information is index information for obtaining an instruction to be obtained.

The number of second index information carried in the first request is at least one. If there are multiple second index information carried in the first request, the first request is a request for obtaining the instruction to be obtained corresponding to each second index information.

It should be noted that if the size of the instruction to be acquired is greater than the capacity of the storage block in the main memory, the second index information is the index information of the storage block of the first instruction segment storing the instruction to be acquired; If the size is less than or equal to the capacity of the storage block in the main memory, the second index information is the index information of the storage block storing the instruction to be acquired.

Step 402: The redirection module binds the execution thread for the first request. It should be noted that the execution thread is mapped to the processor Core one-to-one, and only the execution thread corresponding to the processor Core that has completed the previous instruction acquisition request can bind the first request again. When there are multiple binding execution threads, the first request is bound to the execution thread with shallow Inst Q according to the depth of the instruction queue (Instruction Queue, Inst Q) of the execution thread.

Step 403: The redirection module determines the first index information of the instruction to be acquired according to the second index information. The principle of determining the first index information of the instruction to be acquired in the second index information is: the first index information of the instruction to be acquired is determined in the second index information according to the mapping rule between the storage block in the main memory and multiple caches. The first index of the acquisition instruction may be, for example, the second index information, or a part of the second index information. For example, if the second index information is the physical address of the instruction to be acquired, the first index information of the instruction to be acquired may be the physical address of the instruction to be acquired or a part of the fields in the physical address of the instruction to be acquired.

It should be noted that if the first request carries multiple second index information, one of the second index information is selected in step 403, and step 403 and the following steps are executed according to the selected second index information.

Step 404: The redirection module matches the first index information of the instruction to be acquired with the first index information in each entry in the redirection data table.

Step 405: If the first index information in an entry matches the first index information of the instruction to be acquired, the redirection module determines the cache corresponding to the id of the cache in the entry that matches the first index information of the instruction to be acquired as The first target cache.

Step 406: The redirection module sends the second index information to the first target cache, so that the first target cache obtains the instruction to be obtained according to the second index information.

It can be known from step 403 and step 406 that the first index information of the instruction to be acquired is determined according to the second index information, and the first index information of the instruction to be acquired is combined with the first index information in each entry in the redirection data table. Matching is used to determine whether the instruction to be acquired has been redirected according to the matching result. If so, the cache corresponding to the instruction to be acquired after redirection is determined, that is, the first target cache, so as to acquire the instruction to be acquired in the first target cache. If not, determine the cache corresponding to the instruction to be fetched according to the mapping rules between the storage block in the main memory and multiple caches, combined with the second index information, that is, the first target cache, and fetch the instruction to be fetched in the first target cahce , See step 407 for the specific process.

Step 407: If the first index information in each entry does not match the first index information of the instruction to be obtained, the redirection module determines the first target cache according to the second index information and the mapping rule.

The mapping rule is the mapping relationship between the storage block in the main memory and multiple caches, and the mapping relationship between the storage block and cachelines in multiple caches. The principle of determining the first target cache according to the instruction to be acquired and the mapping rule is: based on the mapping relationship between the storage block and multiple caches, and in combination with the second index information, the cache corresponding to the instruction to be acquired is determined, that is, the first target cache.

In the following, an example is given to describe the process of determining the cache corresponding to the instruction to be obtained based on the mapping relationship between the storage block and the multiple caches in combination with the second index information.

If the mapping relationship between the storage block and multiple caches is set according to the physical address of the storage block and the id of the cache, and the mapping relationship between the preset field in the physical address of the storage block and the id of the cache is established, the physical address and the cache The ids are all expressed in binary, and the number of bits in the preset field of the physical address is the same as the number of the id of the cache. That is, if the preset field of the physical address of the storage block is the same as the id of a cache, the cache is determined to be The cache corresponding to this storage block. In this way, the second index information is the physical address of the instruction to be acquired. The preset field in the physical address of the instruction to be acquired is compared with the id of each cache, and the id is compared with the preset field in the physical address of the instruction to be acquired. The same cache is determined as the cache corresponding to the instruction to be fetched.

Step 408: Send the second index information to the first target cache, so that the first target cache obtains the instruction to be obtained according to the second index information.

Step 409: The first target cache receives the second index information, and determines whether there is a cacheline corresponding to the second index information in the first target cache according to the second index information and the mapping relationship between the storage block in the main memory and the cacheline in the cache. , If it exists, get the command to be fetched in the corresponding cacheline.

Step 410: The first target cache sends the command to be obtained to the crossbar.

Step 411: The crossbar sends the instruction to be obtained to the Processor Core corresponding to the execution thread bound to the first request.

Step 412: The first target cache determines whether the acquisition of the instruction to be acquired has been completed according to the EI identifier in the acquired instruction to be acquired (that is, the instruction to be acquired from the corresponding cacheline in step 409).

Step 413: If the EI flag is 1, it is determined that the acquisition of the instruction to be acquired has been completed, and then jump to step 421.

Step 414: If the EI flag is 0, it is determined that the acquisition of the instruction to be acquired has not been completed, and the first target cache calculates the third index information according to the second index information and the storage interval. It should be noted that the storage interval is the address interval when different instruction segments of an instruction are stored in the main memory.

Step 415: The first target cache sends the third index information to the redirection module.

Step 416: The redirection module receives the third index information sent by the first target cache, and determines the first index information of the instruction to be acquired according to the third index information, and compares the first index information of the instruction to be acquired with the data in the redirection data table. The first index information in each entry is matched.

Step 417: If the first index information in an entry matches the first index information of the instruction to be acquired, the redirection module determines the cache corresponding to the id of the cache in the entry that matches the first index information of the instruction to be acquired as The second target cache.

Step 418: The redirection module sends the third index information to the second target cache, so that the second target cache obtains the instruction to be obtained according to the third index information.

Step 419: If the first index information in each entry does not match the first index information of the instruction to be obtained, the redirection module determines the second target cache according to the third index information and the mapping rule.

Step 420: The redirection module sends the third index information to the second target cache, so that the second target cache obtains the instruction to be obtained according to the third index information.

It should be noted that the principle of determining the second target cache according to the third index information is the same as the principle of determining the first target cache according to the second index information, so it will not be repeated here. The principle that the second target cache obtains the instruction to be acquired according to the third index information and the principle of the subsequent processing flow are the same as the principle of step 409 and the principle of the subsequent processing flow, so it will not be repeated here.

Step 421: If the EI flag is 1, the redirection module determines whether there is other available second index information in the first request, and selects one second index information from the other available second index information in the first request. And based on the second index information selected in this step, step 403 and subsequent steps are repeated.

Specifically, in this step, if the EI flag is 1, it means that the acquisition of the instruction to be acquired corresponding to the second index information selected in step 403 has been completed. Since the number of second index information in the first request is at least one, when the number of second index information is more than one, other available second index information should be selected from the first request and based on the reselected first index information. For the second index information, the above process is repeated to obtain the to-be-obtained instruction corresponding to the reselected second index information.

It should be noted that if the EI flag is 1 and there is no other available first index information in the first request, it is determined that the processing of the first request is completed, and the redirection module can read the new request and process the new request.

Step 422: In step 409, if there is no cacheline corresponding to the second index information in the first target cache, the first target cache generates a Refill (backfill) request according to the second index information.

Step 423: The first target cache sends the Refill request to the main memory.

Step 424: The main memory acquires the instruction to be acquired according to the second index information in the Refill request, and generates response information according to the instruction to be acquired and the second index information, and sends the instruction to be acquired to the execution thread bound to the first request through the crossbar. Corresponding Processor Core.

Step 425: The main memory sends the response information to the redirection module.

Step 426: The redirection module determines the first index information of the instruction to be acquired according to the second index information in the response information, and compares the first index information of the instruction to be acquired with the first index stored in each entry in the redirection data table. Information to match.

Step 427: If the first index information of the instruction to be acquired matches the first index information in an entry in the redirection data table, the redirection module will match the first index information of the instruction to be acquired to the cache entry in the entry. The cache corresponding to the id is determined to be the third target cache.

Step 428: The redirection module sends the response information to the third target cache.

Step 429: If the first index information of the instruction to be obtained does not match the first index information in any entry in the redirection data table, the redirection module determines according to the second index information in the response information in combination with the mapping rule The third target cache.

Step 430: The redirection module sends the response information to the third target cache.

Step 431: The third target cache receives the response information, and stores the to-be-obtained instruction in the response information in a cacheline in the third target cache.

It should be noted that the information acquisition process in which the main storage is the data main storage and the information to be obtained is the data to be obtained is the same as the foregoing steps 401 to 431, and therefore, details are not described here.

It can be seen from the above that the first index information of the information to be obtained is determined according to the second index information, and the first index information of the information to be obtained is matched with the first index information in each entry in the redirection data table, and when there is When matching entries, the cache corresponding to the id of the cache in the matching entry is determined as the first target cache, and the second index information is sent to the first target cache, so that the first target cache obtains it according to the second index information Information to be acquired, therefore, the first request is split based on the redirect data table, which greatly alleviates the problem of uneven request distribution, thereby improving the problem of severe imbalance in request acquisition bandwidth, and improving information acquisition performance.

In the following, the above process will be described with an example. FIG. 8 provides a schematic diagram of an application scenario including multiple caches according to an embodiment of the application. As shown in FIG. 8, the application scenario includes Slice cache (that is, the cache in the application scenario is Slice cache. ), processor core, IBUF (Input Buffer, input buffer) REDIR1 (redirection module 1), Redirect Table (redirection data table), main memory (not shown in Figure 8). Among them, IBUF includes input IFIFO (Input FIFO, First In First Out and REDIR0 (redirection module 0), the number of slice caches is 16, and the number of slice caches is from 0 to 15. Each slice cache includes 256 cachelines and the number of processor cores is 16 , Respectively, processor core 0-15. The main memory is the command main memory, that is, the information stored in the main memory is the command. An 8-way group association is used between the cacheline in each slice cache and the main memory, and the instructions stored in each storage block in the main memory are deployed in a zigzag pattern in multiple slice caches.

It should be noted that when storing instructions to be stored in the main memory, if the size of the instructions to be stored is greater than the capacity of the storage block in the main memory, the instructions to be stored are divided into multiple instruction segments according to the capacity of the storage block, and The divided instruction segments are stored in multiple storage blocks, where the number of divided instruction segments is equal to the number of multiple storage blocks, and the physical addresses of the storage blocks stored in adjacent instruction segments are separated by 8, that is, relative The interval of the physical address of the adjacent instruction segment is 8. It should be noted that the interval 8 here is decimal. If the size of the instruction to be stored is less than or equal to the capacity of the storage block, the instruction to be stored is stored as a whole in a In the storage block.

The mapping rule between the storage block in the main memory and the 16 slice cache is: each storage block in the main memory is mapped to 16 slice caches in a Z-shape, and between each slice cache and the storage block in the main memory Use 8-way group association. It should be noted that the mapping rule is set according to the physical address of the storage block and the id of each slice cache.

The number of bits (binary) of the physical address of the storage block can be determined by the total number of storage blocks in the main memory and the storage bytes of each storage block. Here, the physical address of the storage block includes 18 bits, that is, the physical address of the storage block. The address can be represented by PC[17:0]. It should be noted that the physical address of the storage block is the physical address of the instruction stored in the storage block, that is, the physical address of the instruction in the storage block is represented by PC[17:0] .

The number of bits required to represent the slice cache id in binary can be determined by the total number of slice caches. Since the number of slice cache is 16, the number of digits of the slice cache id is 4, that is, the slice cache id can be represented by SLID[3:0].

Next, the above mapping rules will be described.

Each memory block in the main memory is mapped to 16 slice caches in a zigzag pattern as follows: According to the physical address of the memory block in the main memory, the memory block in the main memory is divided in units of 8 to obtain multiple Storage block groups, where each storage block group includes 8 storage blocks and the physical addresses of the 8 storage blocks are adjacent; then, the storage blocks in the storage block group a+16b are mapped to the ath Slice cache (That is, in Slice cache a), the value range of a is [0,15], and a is an integer, and b is greater than or equal to 0 and is an integer. In other words, storage in storage block group 0 (that is, storage blocks with physical addresses 0-7), storage block group 16 (that is, storage blocks with physical addresses 128-135) based on 0 and separated by 16 storage blocks Blocks are mapped to Slice cache0; storage block group 1 (that is, storage blocks with physical addresses 8 to 15), storage block group 17 (that is, storage blocks with physical addresses 136 to 143), etc., which are based on 1 and are stored 16 apart The storage blocks in the block group are mapped to Slice cache1; and so on, storage block group 15 (that is, storage blocks with physical addresses of 120 to 127), storage block group 31 (that is, storage blocks with physical addresses of 248 to 255), etc. The storage blocks in the storage block group based on 15 and separated by 16 are mapped to Slice cache15. It should be noted that the physical addresses in this section are all decimal.

In this way, based on the above-mentioned zigzag mapping method, PC[6:3] in the PC[17:0] of the storage block is used as a preset field to determine the slice corresponding to the storage block according to the PC[6:3] of the storage block Cache, that is, if the PC[6:3] of a storage block is the same as the SLID[3:0] of a slice cache, then the slice cache is the slice cache corresponding to the storage block. Since the physical address of the storage block is the physical address of the instruction stored in the storage block, when the instruction stored in a storage block is cached to one of the 16 slice caches, the PC of the instruction stored in the storage block [6:3] Compare with the SLID[3:0] of each slice cache, and determine the slice cache with the same SLID[3:0] and the instruction PC[6:3] as the slice cache corresponding to the instruction, And cache the instruction to its corresponding slice cache.

In the following, the structure of each slice cache will be described with reference to FIG. 9. Each slice cache includes Cache data and TAG Table tables. Since the structure of each slice cache is the same, the following only describes the Cache data and TAG Table tables in one slice cache.

Specifically, the Cache data includes 256 cachelines (ie, cachelines 0 to 255), and each cacheline is used to cache instructions in the storage block in the main memory. Because the slice cache and the main memory adopt an 8-way group association method, it can The 256 cachelines are divided into 32 groups of cachelines in units of 8, where each group of cachelines includes 8 cachelines. The TAG Table table consists of multiple rows and columns. One row corresponds to a set of cachelines, each row includes 8 large columns, and one large column is represented by one way, that is, each row includes a total of 8 ways, which are way0～way7. , The 8 ways in each line correspond to the 8 cachelines in the corresponding set of cachelines one-to-one, and each way stores the relevant information of the instructions stored in the corresponding cacheline.

Specifically, each way includes four parameters, namely VLD, TAG, lock, and dirty. Among them, the VLD in the way is used to indicate whether there are instructions stored in the cacheline corresponding to the way. If VLD is 0, it means that there are no instructions in the cacheline corresponding to the way. If the VLD is 1, it means that there are instructions stored in the cacheline corresponding to the way. ；

The TAG in the way is the tag bit in the physical address of the instruction stored in the cacheline corresponding to the way;

The lock in the way indicates whether the instructions stored in the cacheline corresponding to the way can be replaced. If the lock is 1, it indicates that the instructions stored in the cacheline corresponding to the way cannot be replaced. If the lock is 0, it indicates the cacheline corresponding to the way. The stored instructions can be replaced;

The dirty in the way indicates whether the instructions stored in the cacheline corresponding to the way are consistent with the information that should be stored. If dirty is 0, it indicates that the instructions stored in the cacheline corresponding to the way are not consistent with the information that should be stored. It is 1, indicating that the instructions stored in the cacheline corresponding to the way are consistent with the information that should be stored.

The row number corresponding to each way is the index bit in the physical address of the instruction stored in the cacheline corresponding to the way.

Based on the above mapping rules, the PC[17:13] of the instruction in the storage block is used as the index bit, and the PC[12:3] of the instruction in the storage block is used as the tag bit. In this way, when the instruction in the storage block is cached in the Slice cache, the slice cache corresponding to the instruction can be determined according to the PC[6:3] of the instruction, and then the PC[17:13] according to the instruction is in its corresponding Slice cache determines the line number corresponding to the instruction, and determines the set of cachelines corresponding to the instruction according to the line number corresponding to the instruction, and then stores the instruction in one of the corresponding set of cachelines. Finally, according to The cacheline storing the instruction determines the way corresponding to the cacheline storing the instruction in the TAG Tab table in the slice cache corresponding to the instruction, and updates the TAG Tab table in the corresponding slice cache according to the PC [12:3] of the instruction TAG in the corresponding way in.

On this basis, after determining the slice cache corresponding to the instruction to be obtained, the process of obtaining the instruction to be obtained from the corresponding slice cache is described.

First, determine the row corresponding to the instruction to be obtained in the TAG Tab table of the corresponding Slice cache according to the PC[17:13] of the instruction to be obtained, and then, according to the PC[12:3] of the instruction to be obtained and the corresponding row The TAG in each way is matched. If it is matched, the matched way is determined as the way corresponding to the instruction to be obtained. Finally, according to the PC [17:13] of the instruction to be obtained and the id of the corresponding way in the corresponding Slice Find the corresponding cacheline in the Cache data in the cache, and obtain the command to be obtained in the corresponding cacheline.

Based on the foregoing mapping rule, the first index information of the instruction is the PC[17:3] of the instruction, and the second index information is the physical address of the instruction to be obtained, that is, PC[17:0].

It should be noted that if the size of the instruction to be fetched is less than or equal to the capacity of the storage block, the PC[17:0] of the instruction to be fetched is the PC[17:0] of the memory block storing the instruction to be fetched in the main memory, The PC [17:13] of the instruction to be fetched is the PC [17:13] of the storage block in the main memory that stores the instruction to be fetched. If the size of the instruction to be fetched is greater than the capacity of the storage block, the PC[17:0] of the instruction to be fetched in the main memory stores PC[17:0] of the storage block of the first instruction segment of the instruction to be fetched, The PC [17:13] of the instruction to be fetched is the PC [17:13] of the storage block in the main memory that stores the first instruction segment of the instruction to be fetched.

The Redirect Table includes multiple entries. As shown in Figure 8, an entry includes four parameters, which are the first identification VLD, the second identification HOT, the hot spot information PC[17:3], and the cold spot slice cache id (ie SLID[3:0]). In FIG. 8, if the first identification VLD is 0, the first identification VLD is determined to be an invalid mark, and if the first identification VLD is 1, then the first identification VLD is determined to be a valid mark. If the second identifier HOT is 0, the second identifier is determined to be a non-hot spot marker, and if the second identifier HOT is 1, the second identifier is determined to be a hot spot marker.

In the initial state of the above application scenario, the instructions stored in the storage block in the main memory can be cached into 16 slice caches according to the above mapping rule. Then, in the process of obtaining the instructions to be obtained based on the above application scenarios, the above-mentioned method of equalizing to be wide is used to adjust the deployment position of the hot instructions in the hot slice cache in the 16 slice caches to realize the redirection of the hot instructions in the hot slice cache , And then achieve a balanced effect.

Specifically, the process of bandwidth equalization is: REDIR1 detects the access frequency of each slice cache in Slice cache 0-15; then, according to the access frequency of each slice cache, determine the cold spot slice cache and hot slice cache in the slice cache 0-15 Then, determine the hot instruction in the hot slice cache; finally, record the PC[17:3] of the hot instruction and the SLID[3:0] of the cold slice cache in the target entry of the Redirect Table. It should be noted that since the implementation principle of bandwidth equalization has been described above, it will not be repeated here.

As shown in Figure 10 to Figure 12, the process of obtaining the instruction to be obtained may include the following steps:

Step 1001: IBUF receives the first request and buffers the first request in the IFIFO. The first request is a request to obtain the instruction to be acquired, and the first request carries second index information, that is, the PC[17:0] of the instruction to be acquired. It should be noted that, here, the first request includes a second index information as an example for description.

Step 1002, if the IFIFO is not empty and at least one processor core has completed the previous instruction acquisition request, REDIR0 reads the first request from the IFIFO, and binds the corresponding execution thread to the first request. It should be noted that there is a one-to-one correspondence between the execution thread and the processor core. Since the number of processor cores is 16, there are also 16 execution threads. It should be noted that the bound execution thread is the execution thread corresponding to the processor core that has completed the previous instruction acquisition request. In addition, if there are multiple bindable execution threads, that is, the previous instruction acquisition request is completed in multiple processor cores, the first request is allocated to the execution thread with shallow Inst Q according to the Inst Q depth of the execution thread.

Step 1003: REDIR0 determines the first index information of the instruction to be acquired according to the PC[17:0] of the instruction to be acquired. That is, PC[17:3] in the PC[17:0] of the instruction to be acquired is used as the first index information of the instruction to be acquired.

Step 1004: REDIR0 matches the PC[17:3] of the instruction to be obtained with the PC[17:3] in each entry in the Redirect Table.

Step 1005: If the PC[17:3] in an entry in the Redirect Table matches the PC[17:3] of the instruction to be obtained, REDIR0 matches the PC[17:3] in the Redirect Table with the instruction to be obtained The slice cache corresponding to the SLID[3:0] in the entry is determined as the first target slice cache.

Step 1006: REDIR0 sends the PC[17:0] of the command to be obtained to the first target slice cache.

Step 1007: If the PC[17:3] in each entry in the Redirect Table does not match the PC[17:3] of the instruction to be acquired, REDIR0 determines the pending instruction according to the PC[6:3] of the instruction to be acquired. Obtain the slice cache corresponding to the instruction, and determine the corresponding slice cache as the first target slice cache.

Step 1008: REDIR0 sends the PC[17:0] of the command to be obtained to the first target slice cache.

Step 1009: The first target slice cache receives the PC[17:0] of the instruction to be acquired, and determines the target row in the TAG Table according to the PC[17:13] (ie index bit) of the instruction to be acquired, and then transfers the instruction to be acquired The PC[12:3] (ie tag bit) matches the TAG in each way in the target line. If it matches, the way corresponding to the TAG that matches the PC[12:3] of the instruction to be obtained will be determined It is the target way, and then, according to the PC [17:13] of the instruction to be acquired and the id of the target way, the cacheline corresponding to the instruction to be acquired is determined in the Cache data, and the instruction to be acquired is acquired from the cacheline corresponding to the instruction to be acquired.

Step 1010: The slice cache of the first target sends the acquired instruction to be acquired to the crossbar.

Step 1011. The crossbar sends a to-be-obtained instruction to the Processor Core corresponding to the execution thread bound by the first request.

Step 1012: The slice cache of the first target determines whether the acquisition of the instruction to be acquired has been completed according to the EI flag in the instruction to be acquired.

Step 1013: If the EI flag is 1, the slice cache of the first target determines that the acquisition of the instruction to be acquired has been completed, and jumps to step 1021.

Step 1014: If the EI flag is 0, the slice cache of the first target determines that the acquisition of the instruction to be acquired has not been completed, and obtains the third index information according to the PC[17:0] and the storage interval of the instruction to be acquired. Here, since the interval between physical addresses of adjacent instruction segments is 8, the value of the storage interval is 8, that is, the third index information is the binary sum of PC[17:0] and 8 of the instruction to be acquired.

Step 1015: The first target slice cache sends the third index information to REDIR1.

Step 1016: REDIR1 receives the third index information sent by the slice cache of the first target, and matches the PC[17:3] of the third index information with the PC[17:3] in each entry in the redirection data table.

Step 1017: If the PC[17:3] in an entry matches the PC[17:3] of the third index information, REDIR1 will match the SLID[ in the entry that matches the PC[17:3] of the third index information. 3:0] The corresponding slice cache is determined to be the second target slice cache.

Step 1018: REDIR1 sends the third index information to the second target slice cache.

Step 1019: If the PC[17:3] in each entry does not match the PC[17:3] of the third index information, REDIR1 determines the third index according to the PC[6:3] in the third index information The slice cache corresponding to the information determines the slice cache corresponding to the third index information as the second target slice cache.

Step 1020: REDIR1 sends the third index information to the second target slice cache.

It should be noted that the second target Slice cache receives the third index information, and obtains the instruction to be obtained according to the third index information. The principle and subsequent principles are the same as the principle of step 1009 and subsequent principles, so it will not be here any more. Go ahead and repeat.

Step 1021: If the EI flag is 1, REDIR1 can read the new request and process the new request. Since the first request here only includes one second index information, if the EI flag is 1, read the new request and perform corresponding processing.

Step 1022: In step 1009, if there is no way corresponding to the PC[12:3] of the instruction to be acquired in the row corresponding to the PC[17:13] of the instruction to be acquired in the TAGTable table, then the first target Slice The cache generates a Refill request according to the PC[17:0] of the command to be fetched.

Step 1023: The first target slice cache sends the Refill request to the main memory.

Step 1024: The main memory acquires the instruction to be acquired according to the PC[17:0] of the instruction to be acquired in the Refill request, and generates response information according to the instruction to be acquired and the PC[17:0] of the instruction to be acquired, and transfers the instruction to be acquired Send the crossbar to the Processor Core corresponding to the execution thread bound by the first request.

Step 1025: The main memory sends the response information to REDIR1.

Step 1026: REDIR1 matches the PC[17:3] of the command to be obtained in the response message with the PC[17:3] stored in each entry in the redirection data table.

Step 1027: If the PC[17:3] of the instruction to be obtained matches the PC[17:3] in an entry in the redirection data table, then REDIR1 will match the PC[17:3] of the instruction to be obtained The slice cache corresponding to SLID[3:0] in the entry is determined to be the third target slice cache.

Step 1028: REDIR1 sends the response information to the third target slice cache.

Step 1029: If the PC[17:3] of the instruction to be acquired does not match the PC[17:3] in any entry in the redirection data table, REDIR1 sets the PC[6:3] of the instruction to be acquired The corresponding slice cache is determined as the third target slice cache.

Step 1030: REDIR1 sends the response information to the third target slice cache.

Step 1031: The slice cache of the third target receives the response information, and stores the command to be obtained in the response information in a cacheline in the Cache data in the slice cache of the third target, and according to the PC of the command to be obtained in the response information [ 17:0] Update the information in the corresponding way in the TAG Table of the cacheline storing the instruction to be obtained, that is, set the VLD in the corresponding way to 1, TAG set to the PC of the instruction to be obtained [12:3], lock set to 1. Dirty is set to 1.

FIG. 13 is a schematic structural diagram of a bandwidth equalization device provided by an embodiment of the application. As shown in FIG. 13, the device 1300 may include: a first monitoring module 1301, a first determining module 1302, a second determining module 1303, and a recording module 1304. The first monitoring module 1301 is used to monitor multiple cache memories. The first determining module 1302 is used to determine the cold spot cache memory and the hot spot cache memory among the multiple cache memories; the second determining module 1303 is used to determine the hot spot cache memory in the Hot spot information; recording module 1304, used to record the first index information of the hot spot information and the identification information of the cold spot cache in a target entry, where the target entry is in the redirection data table Table entry.

In a possible implementation manner, the first monitoring module 1301 is specifically configured to respond to a frequency monitoring command and monitor the access frequency of the plurality of cache memories in each monitoring period based on a monitoring period.

In a possible implementation manner, the first determining module 1302 is specifically configured to determine, according to the access frequency of each cache memory, the cache memory with the largest access frequency as the hot spot cache memory , Determine the cache memory with the smallest access frequency as the cold spot cache memory; or determine the cache memory with an access frequency greater than the first preset frequency as the cold spot cache memory according to the access frequency of each cache memory In the hot spot cache memory, a cache memory with an access frequency less than a second preset frequency is determined as the cold spot cache memory, wherein the first preset frequency is greater than the second preset frequency.

In a possible implementation manner, the second determining module 1303 is specifically configured to determine whether the access frequency of the hot spot cache memory reaches the frequency configured by the register, and the access frequency of the hot spot cache memory is equal to the cold frequency. Whether the difference in the access frequency of the point cache is greater than the configured value; if so, the hot spot information is determined in the hot spot cache.

In a possible implementation, the second determining module 1303 is specifically configured to determine whether the access frequency of the hot spot cache memory is greater than n times the access frequency of the cold spot cache memory; if so, then Hot spot information is determined in the hot spot cache memory.

In a possible implementation, the second determining module 1303 is specifically configured to monitor the access frequency of each buffer line in the hotspot cache; according to the access frequency of each buffer line, The hot spot cache line is determined in the hot spot cache memory; the information stored in the hot spot buffer line is determined as hot spot information.

In a possible implementation manner, the recording module 1304 is specifically configured to determine a candidate among the multiple entries according to the first identifier and the second identifier of each entry in the multiple entries Entry, wherein the candidate entry includes an entry whose first identifier is an invalid flag and an entry whose second identifier is a non-hot spot flag among the multiple entries; in the candidate entry The target entry is determined in the target entry; the first index information of the hot spot information and the identification information of the cold spot cache memory are recorded in the target entry.

The above-mentioned device of the present application can be used to implement the technical solutions of the method embodiments shown in FIGS. 2-7, and the implementation principles and technical effects are similar, and will not be repeated here.

The present application also provides a computer-readable storage medium, including a computer program, which when executed on a computer, causes the computer to execute any one of the methods in FIGS. 2-7.

This application also provides a computer program, when the computer program is executed by a computer, it is used to execute any one of the methods in FIGS. 2-7.

The present application also provides a chip including a processor and a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute any one of FIGS. 2-7 Item method.

Further, the chip may also include a memory and a communication interface. The communication interface may be an input/output interface, a pin, an input/output circuit, or the like.

In the implementation process, the steps of the foregoing method embodiments may be completed by hardware integrated logic circuits in the processor or instructions in the form of software. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other Programming logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware encoding processor, or executed and completed by a combination of hardware and software modules in the encoding processor. The software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

The memory mentioned in the above embodiments may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), and electrically available Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of exemplary but not restrictive description, many forms of RAM are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), and synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) ) And direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memories of the systems and methods described herein are intended to include, but are not limited to, these and any other suitable types of memories.

A person of ordinary skill in the art may realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (personal computer, server, or network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program code .

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A bandwidth equalization method is characterized in that it includes:

Monitor the access frequency of multiple cache memories;

Determining a cold spot cache memory and a hot spot cache memory among the plurality of cache memories;

Determining hotspot information in the hotspot cache memory;

The first index information of the hot spot information and the identification information of the cold spot cache memory are recorded in a target entry, where the target entry is an entry in a redirection data table.
The method according to claim 1, wherein the monitoring the access frequency of a plurality of cache memories comprises:

In response to the frequency monitoring command, the access frequency of the plurality of cache memories in each monitoring period is monitored based on a monitoring period.
The method according to claim 1, wherein the determining a cold spot cache memory and a hot spot cache memory in the plurality of cache memories comprises:

According to the access frequency of each of the cache memories, the cache memory with the largest access frequency is determined as the hot spot cache memory, and the cache memory with the smallest access frequency is determined as the cold spot cache memory ;or

According to the access frequency of each of the cache memories, the cache memory with the access frequency greater than the first preset frequency is determined as the hot spot cache memory, and the cache memory with the access frequency less than the second preset frequency is determined as the hot spot cache memory. In the cold spot cache memory, the first preset frequency is greater than the second preset frequency.
The method according to claim 1, wherein the determining hotspot information in the hotspot cache memory comprises:

Determining whether the access frequency of the hot spot cache memory reaches the frequency configured by the register and whether the difference between the access frequency of the hot spot cache memory and the access frequency of the cold spot cache memory is greater than a configured value;

If yes, the hot spot information is determined in the hot spot cache memory.
The method according to claim 1, wherein the determining hotspot information in the hotspot cache memory comprises:

Judging whether the access frequency of the hot spot cache memory is greater than n times the access frequency of the cold spot cache memory;

If yes, the hot spot information is determined in the hot spot cache memory.
The method according to any one of claims 1 to 5, wherein the determining hotspot information in the hotspot cache memory comprises:

Monitoring the access frequency of each buffer line in the hotspot cache memory;

Determining a hot spot buffer line in the hot spot cache memory according to the access frequency of each buffer line;

The information stored in the hot spot buffer row is determined as hot spot information.
The method according to any one of claims 1 to 5, wherein the redirection data table includes a plurality of table entries, each of the table entries includes a first identifier and a second identifier, and the first identifier One of the marks is a valid mark or an invalid mark, and the second mark is a hot mark or a non-hot mark.
The method according to claim 7, wherein the recording the first index information of the hot spot information and the identification information of the cold spot cache memory in a target table entry comprises:

According to the first identifier and the second identifier of each of the multiple entries, a candidate entry is determined from the multiple entries, wherein the candidate entry includes the multiple entries The first identifier is an entry with an invalid flag and the second identifier is an entry with a non-hot spot flag;

Determining a target entry in the candidate entry;

Record the first index information of the hot spot information and the identification information of the cold spot cache memory in a target entry.
The method according to claim 8, wherein after recording the first index information of the hot spot information and the identification information of the cold spot cache memory in a target entry, the method further comprises:

The second identifier in the target entry is set as a hot spot label, and the first identifier in the target entry is set as a valid label.
The method according to claim 7, wherein the method further comprises:

Monitoring the access frequency of each entry in the redirection data table;

Judging whether the access frequency of the first entry is less than the third preset frequency, wherein the first entry is the entry whose second identifier is the hot spot mark;

Modifying the second identifier of the first entry whose access frequency is less than the third preset frequency to a non-hot spot mark;

Judging whether the access frequency of the second entry is greater than the fourth preset frequency, where the second entry is the entry whose second identifier is the non-hot spot mark;

Modifying the second identifier of the second entry whose access frequency is greater than the fourth preset frequency into a hot spot mark;

Wherein, the fourth preset frequency is greater than the third preset frequency.
The method according to any one of claims 1-10, wherein the method further comprises:

The hot spot information is filled into the cold spot buffer line in the cold spot cache memory.
The method according to claim 11, wherein the method further comprises:

Determine any buffer line in the cold spot cache memory as the cold spot buffer line; or

Determining a buffer line whose access frequency in the cold spot cache memory is less than the fifth preset frequency as a cold spot buffer line; or

The buffer line with the smallest access frequency in the cold spot cache memory is determined as the cold spot buffer line.
The method according to any one of claims 1-12, wherein the method further comprises:

Reading a first request, where the first request is a request for obtaining information to be obtained, the first request carries second index information, and the second index information is index information used to obtain the information to be obtained;

Determining the first index information of the to-be-obtained information according to the second index information;

Matching the first index information of the information to be obtained with the first index information in each entry in the redirection data table;

If the first index information in one of the entries matches the first index information of the information to be obtained, then the identification information of the cache memory in the entry that matches the first index information of the information to be obtained is changed The corresponding cache memory is determined to be the first target cache memory;

The second index information is sent to the first target cache memory, so that the first target cache memory obtains the to-be-obtained information according to the second index information.
The method according to claim 13, wherein the method further comprises:

If the first index information in each entry does not match the first index information of the information to be obtained, determining the first target cache memory according to the second index information and the mapping rule;

The second index information is sent to the first target cache memory, so that the first target cache memory obtains the to-be-obtained information according to the second index information.
The method according to claim 13 or 14, wherein the method further comprises:

Receive the third index information sent by the first target cache, the third index information is calculated from the second index information and the storage interval, and the third index information is calculated by the first target cache according to Generated when the end identifier in the information to be acquired determines that the acquisition of the information to be acquired has not been completed;

Determining the first index information of the to-be-obtained information according to the third index information;

Matching the first index information of the information to be obtained with the first index information in each entry in the redirection data table;

If the first index information in one of the entries matches the first index information of the information to be obtained, then the identification information of the cache memory in the entry that matches the first index information of the information to be obtained is changed The corresponding cache memory is determined to be the second target cache memory;

The third index information is sent to the second target cache memory, so that the second target cache memory obtains the to-be-obtained information according to the third index information.
The method according to claim 15, wherein the method further comprises:

If the first index information in each entry does not match the first index information of the information to be obtained, determining the second target cache memory according to the third index information and the mapping rule;

The third index information is sent to the second target cache memory, so that the second target cache memory obtains the to-be-obtained information according to the third index information.
A bandwidth equalization device is characterized in that it comprises:

The first monitoring module is used to monitor the access frequency of multiple cache memories;

A first determining module, configured to determine a cold spot cache memory and a hot spot cache memory among the plurality of cache memories;

The second determining module is configured to determine hotspot information in the hotspot cache memory;

The recording module is configured to record the first index information of the hot spot information and the identification information of the cold spot cache memory in a target entry, where the target entry is an entry in a redirection data table.
The device according to claim 17, wherein the first monitoring module is specifically configured to respond to a frequency monitoring command and monitor the access frequency of the plurality of cache memories in each monitoring period based on a monitoring period .
The device according to claim 17, wherein the first determining module is specifically configured to determine the cache memory with the highest access frequency as the hot spot according to the access frequency of each of the cache memories A cache memory, which determines the cache memory with the smallest access frequency as the cold spot cache memory; or, according to the access frequency of each of the cache memories, a cache memory with an access frequency greater than a first preset frequency It is determined as the hot spot cache memory, and a cache memory with an access frequency less than a second preset frequency is determined as the cold spot cache memory, wherein the first preset frequency is greater than the second preset frequency.
The device according to claim 17, wherein the second determining module is specifically configured to determine whether the access frequency of the hotspot cache memory reaches the frequency configured by the register, and the access frequency of the hotspot cache memory is equal to that of the register configuration. Whether the difference in the access frequency of the cold spot cache memory is greater than the configured value; if so, hot spot information is determined in the hot spot cache memory.
The device according to claim 17, wherein the second determining module is specifically configured to determine whether the access frequency of the hot spot cache memory is greater than n times the access frequency of the cold spot cache memory; if so , The hot spot information is determined in the hot spot cache memory.
The device according to any one of claims 17 to 21, wherein the second determining module is specifically configured to monitor the access frequency of each buffer line in the hotspot cache; The access frequency of each buffer line is determined in the hot spot cache memory; the information stored in the hot spot buffer line is determined as hot spot information.
The device according to any one of claims 17 to 21, wherein the redirection data table includes a plurality of entries, each of the entries includes a first identifier and a second identifier, and the first identifier One of the marks is a valid mark or an invalid mark, and the second mark is a hot mark or a non-hot mark.
23. The device according to claim 23, wherein the recording module is specifically configured to determine the number of entries in the plurality of entries according to the first identifier and the second identifier of each entry in the plurality of entries. Candidate entries are determined in the multiple entries, wherein the candidate entries include entries in the plurality of entries whose first identification is an invalid flag and entries whose second identification is a non-hot spot flag; The target entry is determined in the candidate entry; the first index information of the hot spot information and the identification information of the cold spot cache memory are recorded in the target entry.
The device according to claim 24, further comprising:

The setting module is configured to set the second identifier in the target entry as a hotspot label, and set the first identifier in the target entry as a valid label.
The device according to claim 23, further comprising:

The second monitoring module is used to monitor the access frequency of each entry in the redirection data table;

A first judging module, configured to judge whether the access frequency of the first entry is less than the third preset frequency, wherein the first entry is the entry whose second identifier is the hotspot mark;

A first modification module, configured to modify the second identifier of the first entry whose access frequency is less than the third preset frequency to a non-hot spot mark;

The second judgment module is configured to judge whether the access frequency of the second entry is greater than the fourth preset frequency, wherein the second entry is the entry whose second identifier is the non-hot spot mark;

A second modification module, configured to modify the second identifier of the second entry whose access frequency is greater than the fourth preset frequency to a hot spot mark;

Wherein, the fourth preset frequency is greater than the third preset frequency.
The device according to any one of claims 17 to 26, further comprising:

The filling module is used to fill the hot spot information into the cold spot buffer line in the cold spot cache memory.
The device according to claim 27, further comprising:

The third determining module is configured to determine any buffer line in the cold spot cache memory as the cold spot buffer line; or set the access frequency in the cold spot cache memory to be less than the fifth preset frequency The buffer line is determined as a cold-spot buffer line; or the buffer line with the smallest access frequency in the cold-spot cache memory is determined as a cold-spot buffer line.
The device according to any one of claims 17-28, further comprising:

The reading module is configured to read a first request, the first request is a request for obtaining information to be obtained, the first request carries second index information, and the second index information is for obtaining the information to be obtained Information index information;

A fourth determining module, configured to determine the first index information of the to-be-obtained information according to the second index information;

The first matching module is configured to match the first index information of the information to be obtained with the first index information in each entry in the redirection data table;

The fifth determining module is configured to, if the first index information in one of the entries matches the first index information of the information to be obtained, then select the entries that match the first index information of the information to be obtained The cache memory corresponding to the identification information of the cache memory is determined to be the first target cache memory;

The first sending module is configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the to-be-obtained information according to the second index information.
The device according to claim 29, further comprising:

The sixth determining module is configured to determine the first target according to the second index information and the mapping rule if the first index information in each entry does not match the first index information of the information to be obtained Cache memory

The second sending module is configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the to-be-obtained information according to the second index information.
The device according to claim 29 or 30, further comprising:

The receiving module is configured to receive the third index information sent by the first target cache, the third index information is calculated from the second index information and the storage interval, and the third index information is calculated from the first target The cache memory is generated when it is determined that the acquisition of the information to be acquired has not been completed according to the end identifier in the information to be acquired;

A seventh determining module, configured to determine the first index information of the to-be-obtained information according to the third index information;

The second matching module is configured to match the first index information of the information to be obtained with the first index information in each entry in the redirection data table;

The eighth determining module is configured to, if the first index information in one of the entries matches the first index information of the information to be obtained, then select the entries that match the first index information of the information to be obtained The cache memory corresponding to the identification information of the cache memory is determined to be the second target cache memory;

The third sending module is configured to send the third index information to the second target cache memory, so that the second target cache memory obtains the to-be-obtained information according to the third index information.
The device according to claim 31, further comprising:

A ninth determining module, configured to determine a second target according to the third index information and the mapping rule if the first index information in each entry does not match the first index information of the information to be obtained Cache memory

The fourth sending module is configured to send the third index information to the second target cache memory, so that the second target cache memory obtains the to-be-obtained information according to the third index information.
A computer-readable storage medium, comprising a computer program, which when executed on a computer, causes the computer to execute the method according to any one of claims 1-16.
A computer program, when the computer program is executed by a computer, it is used to execute the method of any one of claims 1-16.
A chip comprising a processor and a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the computer program described in any one of claims 1-16 method.