CN108427579A - A method of from SOC chip to a variety of external series flash memory loading codes - Google Patents
A method of from SOC chip to a variety of external series flash memory loading codes Download PDFInfo
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- CN108427579A CN108427579A CN201810171749.0A CN201810171749A CN108427579A CN 108427579 A CN108427579 A CN 108427579A CN 201810171749 A CN201810171749 A CN 201810171749A CN 108427579 A CN108427579 A CN 108427579A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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Abstract
The present invention provides a kind of from SOC chip to the method for a variety of external series flash memory loading codes, differentiation parameter between external series flash chip model described using a data structure, data structure contents include the ID of chip, chip data communication signal wire quantity, the addressable range of the operational order of chip and chip.The method of the present invention, the attribute of a variety of external series flash memory differentiation is all abstracted into a set, can support be carried out to the serial flash chip of different model well by configuring the set, when needing to load executable code from the various types of external series flash chips of different manufacturers, bootrom can be solved using the method for the present invention（bootrom）It is cured to after chip it is difficult to the problem of supporting the external series flash chip of the various different models of external connection.
Description
Technical field
It is specifically a kind of from SOC chip to the side of a variety of external series flash memory loading codes the invention belongs to chip field
Method.
Background technology
In embedded systems, serial flash is commonly used as code memory, serial flash is varied in the market,
Various serial flash may be connected as final design after chip manufacture, it is therefore desirable to which there are one methods to ensure in core
After piece manufacture, it can support to load executable code from the external series flash chip of different model.Serial flash chip according to
The difference of producer's model etc. reads erasable operational order, signal wire quantity, addressable address range and the sector that data communicate
Size be likely to have differences to varying degrees.When needing to the various types of external series flash chips of different manufacturers
When middle load executable code, there are bootroms（bootrom）Be cured to after chip be difficult support external connection it is various not
With model external series flash chip the problem of.
Invention content
In order to solve the above technical problems existing in the prior art, the present invention provides one kind from SOC chip to a variety of
The method of external series flash memory loading code, differentiation is joined between describing external series flash chip model using a data structure
Number, data structure contents include the ID of chip, the signal wire quantity of chip data communication, the operational order of chip and chip can
Addressing range.
Further, this method has the external series flash chip model list that acquiescence is supported, corresponding model list institute
Some external series flash chip model differentiation parameter groups constitute differentiation parameter list, each external series flash chip
Model has one's own one group of differentiation parameter, wherein being index with ID number, spreading parameter row are also store in OTP
Table, the support for the later stage to newly-increased serial flash chip.
Further, the differentiation parameter for giving tacit consent to the external series flash chip of support is stored in ROM.
Further, external serial flash chip read operation is specifically comprised the following steps：
（One）First determine whether currently whether initialization was carried out to external serial flash chip；If initialized, step is just jumped to
Suddenly（Six）；If no initializtion is put into step（Two）；
（Two）External serial flash chip is sent and reads id command acquisition chip id, is read and is corresponded to from parameter list according to chip id
Chip parameter, and be configured in the differentiation Parameters data structure body of driving；
（Three）According to the correspondence chip parameter got, judge whether to address using 4 bytes；If using, step is just jumped to（Four）；
If not using, step is just jumped to（Six）；
（Four）According to the correspondence chip parameter got, judge whether to give tacit consent to the addressing of 4 bytes；If so, just jumping to step（Six）；If
It is no, just jump to step（Five）；
（Five）The enabled order of 4 bytes addressing, and the 4 byte addressing of enabled external series flash chip are obtained from Parameters data structure body
Pattern；
（Six）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines.If using, step is just jumped to
（Seven）；If not using, step is just jumped to（Eight）；
（Seven）The enabled order of 4 data lines communication, and enabled 4 data line of external series flash chip are obtained from Parameters data structure body
Communication pattern；
（Eight）Read operation order is obtained from Parameters data structure body, executes read operation；
（Nine）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines；If using, step is just jumped to
（Ten）；If not using, just terminate；
（Ten）The communication disability order of 4 data lines, and 4 data line of external series flash chip that disables are obtained from Parameters data structure body
Communication pattern terminates.
Further, external serial flash chip write operation is specifically comprised the following steps：
（One）First determine whether currently whether initialization was carried out to external serial flash chip；If initialized, step is just jumped to
Suddenly（Six）；If no initializtion just jumps to step（Two）；
（Two）External serial flash chip is sent and reads id command acquisition chip id, is read and is corresponded to from parameter list according to chip id
Chip parameter, and be configured in the differentiation argument structure body of driving；
（Three）According to the correspondence chip parameter got, judge whether to address using 4 bytes；If using, step is just jumped to（Four）；
If not using, step is just jumped to（Six）；
（Four）According to the correspondence chip parameter got, judge whether to give tacit consent to the addressing of 4 bytes；If so, just jumping to step（Six）；If
It is no, just jump to step（Five）；
（Five）The enabled order of 4 bytes addressing is obtained from argument structure body, and enabled 4 byte of external series flash chip addresses mould
Formula；
（Six）Judge incoming erasable address whether sector alignment, sector-size can be by obtaining in argument structure body；If alignment, just
Jump to step（Seven）；If being misaligned, misprint is reported and is terminated；
（Seven）It is obtained from argument structure body and wipes operational order, executed and wipe operation；
（Eight）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines.If using, step is just jumped to
（Nine）；If not using, step is just jumped to（Ten）；
（Nine）The enabled order of 4 data lines communication, and the 4 data line communication of enabled external series flash chip are obtained from argument structure body
Pattern；
（Ten）Write operation order is obtained from argument structure body, executes write operation；
（11）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines；If using, step is just jumped to
Suddenly（12）；If not using, just terminate；
（12）The communication disability order of 4 data lines is obtained from argument structure body, and 4 data line of external series flash chip that disables is logical
Letter pattern terminates.
The method of the present invention, is all abstracted into a set by the attribute of a variety of external series flash memory differentiation, passes through and configure
The set can carry out support to the serial flash chip of different model well, various types of from different manufacturers when needing
When loading executable code in external series flash chip, bootrom can be solved using the method for the present invention
（bootrom）It is cured to after chip it is difficult to the problem of supporting the external series flash chip of the various different models of external connection.
Description of the drawings
Fig. 1 is the flow chart to external serial flash chip read operation；
Fig. 2 is the flow chart to external serial flash chip write operation.
Specific implementation mode
The invention will be further described below in conjunction with the accompanying drawings.
The present invention is abstracted the operating process of external serial flash chip, and external string is described using a data structure
Differentiation parameter between row flash chip model, including design parameter content refer to table 1.
1. differentiation Parameters data structure table of table
There are one the external series flash chip model lists that acquiescence is supported by the present invention, and there are a parameters to arrange for corresponding model list
Table.Each external series flash chip model has one's own one group of parameter, all external series flash chip types
Number parameter group constitutes parameter list, wherein being index with ID number.It also stores a spreading parameter list in OTP simultaneously, uses
In support of the later stage to newly-increased serial flash chip.The ID of current external serial flash chip is first obtained in module initialization
Number, the parameter group that matches corresponding model is then gone according to ID number in parameter list, to get relevant parameter.Work as when getting
After the parameter group of preceding external series flash chip, parameter group is configured into the abstraction framework of operating process, is then realized to working as
The support of preceding external series flash chip.
As shown in Figure 1, for the flow chart to external serial flash chip read operation, specifically comprise the following steps：
（One）First determine whether currently whether initialization was carried out to external serial flash chip.If initialized, step is just jumped to
Suddenly（Six）.If no initializtion is put into step（Two）.
（Two）External serial flash chip is sent and reads id command acquisition chip id, is read from parameter list according to chip id
Corresponding chip parameter, and be configured in the differentiation Parameters data structure body of driving.
（Three）According to the correspondence chip parameter got, judge whether to address using 4 bytes.If using, step is just jumped to
（Four）.If not using, step is just jumped to（Six）.
（Four）According to the correspondence chip parameter got, judge whether to give tacit consent to the addressing of 4 bytes.If so, just jumping to step
（Six）.If it is not, just jumping to step（Five）.
（Five）The enabled order of 4 bytes addressing, and enabled 4 byte of external series flash chip are obtained from Parameters data structure body
Addressing mode.
（Six）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines.If using, step is just jumped to
Suddenly（Seven）.If not using, step is just jumped to（Eight）.
（Seven）The enabled order of 4 data lines communication is obtained from Parameters data structure body, and enabled external series flash chip 4 counts
According to line communication pattern.
（Eight）Read operation order is obtained from Parameters data structure body, executes read operation.
（Nine）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines.If using, just jump to
Step（Ten）.If not using, just terminate.
（Ten）The communication disability order of 4 data lines, and the number of external series flash chip 4 that disables are obtained from Parameters data structure body
According to line communication pattern, terminate.
If Fig. 2 is to specifically comprise the following steps to the flow chart of external serial flash chip write operation：
（One）First determine whether currently whether initialization was carried out to external serial flash chip.If initialized, step is just jumped to
Suddenly（Six）.If no initializtion just jumps to step（Two）.
（Two）External serial flash chip is sent and reads id command acquisition chip id, is read from parameter list according to chip id
Corresponding chip parameter, and be configured in the differentiation argument structure body of driving.
（Three）According to the correspondence chip parameter got, judge whether to address using 4 bytes.If using, step is just jumped to
（Four）.If not using, step is just jumped to（Six）.
（Four）According to the correspondence chip parameter got, judge whether to give tacit consent to the addressing of 4 bytes.If so, just jumping to step
（Six）.If it is not, just jumping to step（Five）.
（Five）The enabled order of 4 bytes addressing, and the 4 byte addressing of enabled external series flash chip are obtained from argument structure body
Pattern.
（Six）Judge incoming erasable address whether sector alignment, sector-size can be by obtaining in argument structure body.If right
Together, step is just jumped to（Seven）.If being misaligned, misprint is reported and is terminated.
（Seven）It is obtained from argument structure body and wipes operational order, executed and wipe operation.
（Eight）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines.If using, step is just jumped to
Suddenly（Nine）.If not using, step is just jumped to（Ten）.
（Nine）The enabled order of 4 data lines communication, and enabled 4 data line of external series flash chip are obtained from argument structure body
Communication pattern.
（Ten）Write operation order is obtained from argument structure body, executes write operation.
（11）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines.If using, just redirect
To step（12）.If not using, just terminate.
（12）The communication disability order of 4 data lines, and 4 data of external series flash chip that disable are obtained from argument structure body
Line communication pattern terminates.
In the SPI flash drivings of multi-function printer chip, the SPI flash cores for supporting various different models are needed
Piece.The attribute of these differentiation has all been abstracted into a set, by configuring the set by method through the invention
Support is carried out to the serial flash chip of different model well.
Between general different types of SPI flash chips, often according to the difference of producer's model etc., erasable operation is read
Signal wire quantity, addressable address range and the size of sector that order, data communicate are likely to deposit to varying degrees
In difference.And the method for using the present invention, the denominator of the operating method of SPI flash chips is abstracted, and uses
One data structure carrys out differentiation parameter between abstractdesription SPI flash chip models.By the way that this data structure is stored in
In OTP, after multi-function printer chip dispatches from the factory, it can support to increase newly by the differentiation data structure in modification OTP outer
Portion's SPI flash chips.
Claims (5)
1. a kind of from SOC chip to the method for a variety of external series flash memory loading codes, it is characterised in that：Use a data knot
Structure describes differentiation parameter between external series flash chip model, and data structure contents include the ID of chip, chip data communication
Signal wire quantity, the addressable range of the operational order of chip and chip.
2. as described in claim 1 from SOC chip to the method for a variety of external series flash memory loading codes, it is characterised in that：
This method has the external series flash chip model list that acquiescence is supported, all external series flash memory cores of corresponding model list
Piece model differentiation parameter group constitutes differentiation parameter list, each external series flash chip model has one's own
One group of differentiation parameter also stores spreading parameter list wherein being index with ID number in OTP, for the later stage to newly-increased string
The support of row flash chip.
3. as described in claim 1 from SOC chip to the method for a variety of external series flash memory loading codes, it is characterised in that：
The differentiation parameter for giving tacit consent to the external series flash chip supported is stored in ROM.
4. as described in claim 1 from SOC chip to the method for a variety of external series flash memory loading codes, it is characterised in that：
External serial flash chip read operation is specifically comprised the following steps：
（One）First determine whether currently whether initialization was carried out to external serial flash chip；If initialized, step is just jumped to
Suddenly（Six）；If no initializtion is put into step（Two）；
（Two）External serial flash chip is sent and reads id command acquisition chip id, is read and is corresponded to from parameter list according to chip id
Chip parameter, and be configured in the differentiation Parameters data structure body of driving；
（Three）According to the correspondence chip parameter got, judge whether to address using 4 bytes；If using, step is just jumped to（Four）；
If not using, step is just jumped to（Six）；
（Four）According to the correspondence chip parameter got, judge whether to give tacit consent to the addressing of 4 bytes；If so, just jumping to step（Six）；If
It is no, just jump to step（Five）；
（Five）The enabled order of 4 bytes addressing, and the 4 byte addressing of enabled external series flash chip are obtained from Parameters data structure body
Pattern；
（Six）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines；
If using, step is just jumped to（Seven）；If not using, step is just jumped to（Eight）；
（Seven）The enabled order of 4 data lines communication, and enabled 4 data line of external series flash chip are obtained from Parameters data structure body
Communication pattern；
（Eight）Read operation order is obtained from Parameters data structure body, executes read operation；
（Nine）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines；If using, step is just jumped to
（Ten）；If not using, just terminate；
（Ten）The communication disability order of 4 data lines, and 4 data line of external series flash chip that disables are obtained from Parameters data structure body
Communication pattern terminates.
5. as described in claim 1 from SOC chip to the method for a variety of external series flash memory loading codes, it is characterised in that：
External serial flash chip write operation is specifically comprised the following steps：
（One）First determine whether currently whether initialization was carried out to external serial flash chip；If initialized, step is just jumped to
Suddenly（Six）；If no initializtion just jumps to step（Two）；
（Two）External serial flash chip is sent and reads id command acquisition chip id, is read and is corresponded to from parameter list according to chip id
Chip parameter, and be configured in the differentiation argument structure body of driving；
（Three）According to the correspondence chip parameter got, judge whether to address using 4 bytes；If using, step is just jumped to（Four）；
If not using, step is just jumped to（Six）；
（Four）According to the correspondence chip parameter got, judge whether to give tacit consent to the addressing of 4 bytes；If so, just jumping to step（Six）；If
It is no, just jump to step（Five）；
（Five）The enabled order of 4 bytes addressing is obtained from argument structure body, and enabled 4 byte of external series flash chip addresses mould
Formula；
（Six）Judge incoming erasable address whether sector alignment, sector-size can be by obtaining in argument structure body；If alignment, just
Jump to step（Seven）；If being misaligned, misprint is reported and is terminated；
（Seven）It is obtained from argument structure body and wipes operational order, executed and wipe operation；
（Eight）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines；
If using, step is just jumped to（Nine）；If not using, step is just jumped to（Ten）；
（Nine）The enabled order of 4 data lines communication, and the 4 data line communication of enabled external series flash chip are obtained from argument structure body
Pattern；
（Ten）Write operation order is obtained from argument structure body, executes write operation；
（11）According to the correspondence chip parameter got, judge whether to communicate using 4 data lines；If using, step is just jumped to
Suddenly（12）；If not using, just terminate；
（12）The communication disability order of 4 data lines is obtained from argument structure body, and 4 data line of external series flash chip that disables is logical
Letter pattern terminates.
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| CN201810171749.0A CN108427579B (en) | 2018-03-01 | 2018-03-01 | Method for loading codes from SOC chip to multiple external serial flash memories |
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| CN201810171749.0A CN108427579B (en) | 2018-03-01 | 2018-03-01 | Method for loading codes from SOC chip to multiple external serial flash memories |
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| CN108427579B CN108427579B (en) | 2021-02-02 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114489851A (en) * | 2022-01-20 | 2022-05-13 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114489852A (en) * | 2022-01-20 | 2022-05-13 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114579198A (en) * | 2022-01-20 | 2022-06-03 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050120163A1 (en) * | 2003-12-02 | 2005-06-02 | Super Talent Electronics Inc. | Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes |
| CN101867737A (en) * | 2010-04-06 | 2010-10-20 | 福建新大陆通信科技股份有限公司 | Software processing method capable of being compatible with various models of FLASH based on set-top box |
| CN102622243A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Method for executing solidified codes supporting various NAND flash memories |
-
2018
- 2018-03-01 CN CN201810171749.0A patent/CN108427579B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050120163A1 (en) * | 2003-12-02 | 2005-06-02 | Super Talent Electronics Inc. | Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes |
| CN101867737A (en) * | 2010-04-06 | 2010-10-20 | 福建新大陆通信科技股份有限公司 | Software processing method capable of being compatible with various models of FLASH based on set-top box |
| CN102622243A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Method for executing solidified codes supporting various NAND flash memories |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114489851A (en) * | 2022-01-20 | 2022-05-13 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114489852A (en) * | 2022-01-20 | 2022-05-13 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114579198A (en) * | 2022-01-20 | 2022-06-03 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114579198B (en) * | 2022-01-20 | 2024-02-20 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114489851B (en) * | 2022-01-20 | 2024-02-20 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
| CN114489852B (en) * | 2022-01-20 | 2024-03-01 | 飞腾信息技术有限公司 | Memory chip starting method and device, computer equipment and storage medium |
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